DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
Rev. 2.5 10/13 Micross Components reserves the right to change products or specifi cations without notice. SSRAM AS5SS256K18
FEATURES
- Fast access times: 8, 10, and 15ns
- Fast clock speed: 113, 100, and 66 MHz
- Fast clock and OE\\ access times
- Single +3.3V ± 5% power supply (V DD)
- SNOOZE MODE for reduced-power standby
- Common data inputs and data outputs
- Individual BYTE WRTIE control and GLOBAL WRITE
- Three chip enables for simple depth expansion and address pipelining
- Clock-controlled and registered addresses, data I/Os and control signals
- Interally self-timed WRITE cycle
- Burst control pin (interleaved or linear burst)
- Automatic power-down
- Low capacitive bus loading
- Available in Industrial, Enhanced, and Mil-Temperature Operating Ranges
- RoHs compliant options available OPTIONS MARKING
- Timing 7.5ns/8ns/113 MHz -8 8.5ns/10ns/100 MHz -9 10ns/15ns/66 MHz -10
- Packages TQFP DQ No. 1001
- Operating Temperature Ranges: - Military -55 oC to +125oC /IT - Enhanced -45 oC to +105oC /ET - Industrial -45 oC to +85oC /XT 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through PIN ASSIGNMENT (Top View) 100-pin TQFP (DQ) SASA CE\\ CE2NC NC bwB\\BWa\\ CE2\\ VDD V SS CLKGW\\ BWE\\OE\\ADSC\\ADSP\\ADV\\ SA SA 5131 32 33 34 35 36 37 38 39 40 41 42 43 44 4546 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81NC NC NC V DDQ VSS NC NC DQb DQb V SS VDDQ DQb DQb NC VDD NC VSS DQb DQb V DDQ VSS DQb DQb DQPb NC V SS VDDQ NC NC NC SA NC NC V DDQ VSS NC DQPa DQa DQa V SS VDDQ DQa DQa V SS NC VDD ZZ DQa DQa V DDQ VSS DQa DQa NC NC V SS VDDQ NC NC NC MODE SA SA SA SA SA1 SA0DNUDNU V SS V DD NFNFSASASA SASA SA SA GENERAL DESCRIPTION The Micross Components Synchronous Burst SRAM family employs high-speed, low power CMOS designs that are fabricated using an advanced CMOS process. The 4Mb Synchronous Burst SRAMs integrate a 256K x 18, SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE\\), two additional chip enables for easy depth expansion (CE2\\, CE2), burst control inputs (ADSC\\, ADSP\\, ADV\\), byte write enables (BWx\\) and global write (GW\\). Asynchronous inputs include the output enable (OE\\), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE\\, is also asynchronous. WRITE cycles can be from one to two bytes wide, as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP\\) or address status controller (ADSC\\) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV\\). Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on this x18 device BWa\\ controls DQa pins and DQPa; BWb\\ controls DQb pins and DQPb. GW\\ LOW causes all bytes to be written. Parity bits are available on this device. The 4Mb Synchronous Burst SRAMs operate from a +3.3V V DD power supply, and all inputs and outputs are TTL-compatible. The device is ideally suited for 486, Pentium®, and PowerPC systems and those systems that benefi t from a wide synchronous data bus. **pins 42,43 reserved for future address expansion for 8Mb, 16Mb densities.
Rev. 2.5 10/13 Micross Components reserves the right to change products or specifi cations without notice. SSRAM AS5SS256K18 PIN DESCRIPTIONS PIN NUMBERS SYM TYPE DESCRIPTION 80-82, 99, 100 SA0, SA1, SA Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. 93, 94 BWa\\ BWb\\ Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enables is LOW for a WRITE cycle and HIGH for a READ cycle. BWa\\ controls DQa pins and DQPa; BWb\\ controls DQb pins and DQPb.
87 BWE\\ Input Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet
the setup and hold times around the rising edge of CLK.
88 GW\\ Input Global Write: This active LOW input allows a full 18-bit WRITE to occur independent of the
BWE\\ and BWx\\ lines and must meet the setup and hold times around the rising edge of CLK. 89 CLK Input Clock: This signal registers the addresses, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s risin g edge.
98 CE\\ Input Synchronous Chip Enable: This active LOW input is used to enable the device and
Conditions the internal use of ADSP\\. CE\\ is sampled only when a new external address is loaded.
92 CE2\\ Input Synchronous Chip Enable: This active LOW input is used to enable the device and is
sampled only when a new external address is loaded.
97 CE2 Input Synchronous Chip Enable: This active HIGH input is used to enable the device and is
sampled only when a new external address is loaded. 86 OE\\ Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers.
83 ADV\\ Input Synchronous Address Advance: This active LOW input is used to advance the internal
burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait states to be generated (no address advance). To ensure use of correct address during WRITE cycle, ADV\\ must be HIGH at the rising edge of the first clock after an ADSP\\ cycle is initiated.
84 ADSP\\ Input Synchronous Address Status Processor: This active LOW input interrupts any ongoing
burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC\\, but dependent upon CE\\, CE2, and CE2\\. ADSP\\ is ignored if CE\\ is HIGH. Power-down state is entered if CE2 if LOW or CE2\\ is HIGH.
85 ADSC\\ Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing
burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE\\ is LOW. ADSC\\ is also used to place the chip into power- down state when CE\\ is HIGH. 31 MODE Input Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST. Do not alter input state while device is operating.
64 ZZ Input Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-
power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. 69, 72, 73 , 23 DQa DQb Input/ Output SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb pins. Input data must meet setup and hold times around the rising edge of CLK. 74, 24 NC/DQPa NC/DQPb NC/ I/O No Connect/Parity Data I/Os: Byte "a" is DQPa pins; Byte "b" is DQPb pins. 15, 41,65, 91 VDD Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. 70, 77 VDDQ Supply Isolated Output Buffer Supply: See DC Electrical Characterics and Operating Conditions for range. 40, 55, 60, 67 71, 76, VSS Supply Ground: GND 38, 39 DNU --- Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. 78, 79, 95, 96 NC ----- No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. 42, 43 NF No Function: These pins are internally connected to the die and will have the capacitance of input pins. It is allowable to leave these pins unconnected or driven by signals.
Rev. 2.5 10/13 Micross Components reserves the right to change products or specifi cations without notice. SSRAM AS5SS256K18 INTERLEAVED BURST ADDRESS TABLE (MODE=NC OR HIGH) LINEAR BURST ADDRESS TABLE (MODE=LOW) FUNCTIONAL BLOCK DIAGRAM NOTE: The Functional Block Diagram illustrates simplifi ed device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. 18 18 16 18 SA0, SA1, SA MODE ADV\\ CLK ADSC\\ ADSP\\ BWb\\ BWa\\ BWE\\ GW\\ CE\\ CE2 CE2\\ OE\\ 2 ADDRESS REGISTER BINARY COUNTER AND LOGIC BYTE "b" WRITE REGISTER BYTE "a" WRITE REGISTER ENABLE REGISTER CLR SA1' SA0' INPUT REGISTERS OUTPUT BUFFERS SENSE AMPS 256K x 9 x 2 MEMORY ARRAY BYTE "b" WRITE DRIVER BYTE "a" WRITE DRIVER 18 18 18 DQs DQPa DQPb
2 SA0-SA1
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X…X00 X…X01 X…X10 X…X11 X…X01 X…X00 X…X11 X…X10 X…X10 X…X11 X…X00 X…X01 X…X11 X…X10 X…X01 X…X00 FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X…X00 X…X01 X…X10 X…X11 X…X01 X…X10 X…X11 X…X00 X…X10 X…X11 X…X00 X…X01 X…X11 X…X00 X…X01 X…X10 PARTIAL TRUTH TABLE FOR WRITE COMMANDS FUNCTION GW\\ BWE\\ BWa\\ BWb\\ READ H H X X READ H L H H WRITE Byte "a" H L L H WRITE Byte "b" H L H L WRITE All Bytes H L L L WRITE All Bytes L X X X NOTE: Using BWE\\ and BWa\\ through BWb\\, any one or more bytes may be written.
Rev. 2.5 10/13 Micross Components reserves the right to change products or specifi cations without notice. SSRAM AS5SS256K18 TRUTH TABLE 2. For WRITE\\, L means any one or more byte write enable signals (BWa\\, BWb\\) and BWE\\ are LOW or GW\\ is LOW. WRITE\\ = H for all BWx\\, BWE\\, GW\\ HIGH. 3. BWa\\ enables WRITEs to DQas and DQPa. BWb\\ enables WRITEs to DQbs and DQPb. 4. All inputs except OE\\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE\\ must be HIGH before the input data setup time and held HIGH throughou t the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP\\ LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE\\ LOW or GW\\ LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clari fi cation. OPERATION ADDRESS USED CE\\ CE2\\ CE2 ZZ ADSP\\ ADSC\\ ADV\\ WRITE\\ OE\\ CLK DQ DESELECT Cycle, Power-Down NONE H X X L X L X X X L-H High-Z DESELECT Cycle, Power-Down NONE L X L L L X X X X L-H High-Z DESELECT Cycle, Power-Down NONE L H X L L X X X X L-H High-Z DESELECT Cycle, Power-Down NONE L X L L H L X X X L-H High-Z DESELECT Cycle, Power-Down NONE L H X L H L X X X L-H High-Z SNOOZE MODE, Power-Down NONE X X X H X X X X X X High-Z READ Cycle, Begin Burst EXTERNAL L L H L L X X X L L-H Q READ Cycle, Begin Burst EXTERNAL L L H L L X X X H L-H High-Z WRITE Cycle, Begin Burst EXTERNAL L L H L H L X L X L-H D READ Cycle, Begin Burst EXTERNAL L L H L H L X H L L-H Q READ Cycle, Begin Burst EXTERNAL L L H L H L X H H L-H High-Z READ Cycle, Continue Burst NEXT X X X L H H L H L L-H Q READ Cycle, Continue Burst NEXT X X X L H H L H H L-H High-Z READ Cycle, Continue Burst NEXT H X X L X H L H L L-H Q READ Cycle, Continue Burst NEXT H X X L X H L H H L-H High-Z WRITE Cycle, Continue Burst NEXT X X X L H H L L X L-H D WRITE Cycle, Continue Burst NEXT H X X L X H L L X L-H D READ Cycle, Suspend Burst CURRENT X X X L H H H H L L-H Q READ Cycle, Suspend Burst CURRENT X X X L H H H H H L-H High-Z READ Cycle, Suspend Burst CURRENT H X X L X H H H L L-H Q READ Cycle, Suspend Burst CURRENT H X X L X H H H H L-H High-Z WRITE Cycle, Suspend Burst CURRENT X X X L H H H L X L-H D WRITE Cycle, Suspend Burst CURRENT H X X L X H H L X L-H D
Rev. 2.5 10/13 Micross Components reserves the right to change products or specifi cations without notice. SSRAM AS5SS256K18 ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifi cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airfl ow. DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC < TA < +125oC, -40oC < TA < +105oC and -40oC<TA<+85oC; VDD = +3.3V ± 5% unless otherwise noted) DESCRIPTION CONDITIONS SYMBOL MIN MA X UNITS NOTES Input High (Logic 1) Voltage VIH 2.0 VDD +0.3 V1 , 2 Input Low (Logic 0) Voltage VIL -0.3 0.8 V 1, 2 Input Leakage Current (0V<VIN<VDD) ILI -2 2 P$ 3 Output Leakage Current Output(s) disabled; 0V<VIN<VDD ILO -2 2 P$ Output High Voltage IOH = -4.0mA V OH 2.4 -- V 1, 4 Output Low Voltage IOL = 8.0 mA V OL -- 0.5 V 1, 4 Supply Voltage VDD 3.135 3.465 V 1 Isolated Output Buffer Supply VDDQ 3.135 3.465 V 1, 5 NOTES: 1. All voltages referenced to VSS (GND) 2. Overshoot: V IH < +4.6V for t < tKC/2 for I < 20mA Undershoot: V IL > -0.7V for t < tKC/2 for I < 20mA Power-up: V IH < +3.465V and VDD<3.135V for t < 200ms 3. MODE pin has an internal pull-up, and input leakage = ±10 μA. 4. The load used for V OH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher then the stated DC values. 5. V DDQ should never exceed VDD. VDD and VDDQ can be connected together, for 3.3V I/O operation only. 6. This parameter is sampled. CAPACITANCE DESCRIPTION CONDITIONS SYM MAX UNITS NOTES Control Input Capacitance CI 6p F6 Input/Output Capacitance (DQ) CO 8p F6 TA = 25°C; f = 1MHz; VDD = 3.3V THERMAL RESISTANCE DESCRIPTION CONDITIONS SYM DQ Package DQC Package UNITS NOTES Thermal Resistance (Junction to Ambient) TJA 30.32 35.25 °C/W 6 Thermal Resistance (Junction to Top of Case) TJC 6.85 7.96 °C/W 6 Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51
Rev. 2.5 10/13 Micross Components reserves the right to change products or specifi cations without notice. SSRAM AS5SS256K18 IDD ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC < TA < +125oC, -40oC < TA < +105oC and -40oC<TA<+85oC; VDD = +3.3V ±5% unless otherwise noted) CONDITIONS SYM -8 -9 -10 UNITS NOTES Device selected; all inputs < VIL or > VIH; Cycle time > tKC (MIN); VDD = MAX; Outputs Open IDD 225 205 185 mA 2, 3, 4 CMOS Standby Device deselected; VDD = MAX; All inputs < Vss +0.2 or > VDDQ -0.2; All inputs static; CLK frequency =0 ISB2 90 90 90 mA 3, 4 TTL Standby Device deselected; VDD = MAX; All inputs < VIL or > VIH; All inputs static; CLK frequency = 0 ISB3 120 120 120 mA 3, 4 Power Supply Current: Operating PARAMETER MAX NOTES: 2. I DD is specifi ed with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 3. “Device deselected” means device is in power-down mode as de fi ned in the truth table. “Device selected” means device is active (not in power-down mode). 4. Typical values are measured at 3.3V , 25°C and 15ns cycle time.
Rev. 2.5 10/13 Micross Components reserves the right to change products or specifi cations without notice. SSRAM AS5SS256K18 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) -55oC < TA < +125oC, -40oC < TA < +105oC and -40oC<TA<+85oC; VDD = +3.3V ± 5% unless otherwise noted) MIN MAX MIN MAX MIN MAX Clock cycle time tKC 8.8 10 15 ns Clock frequency tKF 113 100 66 MHz Clock HIGH time tKH 2.5 3.0 4.0 ns 2 Clock LOW time tKL 2.5 3.0 4.0 ns 2 Clock to output valid tKQ 7.5 8.5 10 ns Clock to output invalid tKQX 1.5 3.0 3.0 ns 3 Clock to output in Low-Z tKQLZ 1.5 3.0 3.0 ns 3, 4, 5 Clock to output in High-Z tKQHZ 4.2 5.0 5.0 ns 3, 4, 5 OE\\ to output valid tOEQ 4.2 5.0 5.0 ns 6 OE\\ to output in Low-Z tOELZ 000 ns 3, 4, 5 OE\\ to output in High-Z tOEHZ 4.2 5.0 5.0 ns 3, 4, 5 Address tAS 1.5 1.8 2.0 ns 7, 8 Address status (ADSC\\, ADSP\\) tADSS 1.5 1.8 2.0 ns 7, 8 Address advance (ADV\\) tAAS 1.5 1.8 2.0 ns 7, 8 Byte write enables (BWa\\-BWb\\, GW\\, BWE\\) tWS 1.5 1.8 2.0 ns 7, 8 Data-in tDS 1.5 1.8 2.0 ns 7, 8 Chip enable (CE\\) tCES 1.5 1.8 2.0 ns 7, 8 Address tAH 0.5 0.5 0.5 ns 7, 8 Address status (ADSC\\, ADSP\\) tADSH 0.5 0.5 0.5 ns 7, 8 Address advance (ADV\\) tAAH 0.5 0.5 0.5 ns 7, 8 Byte write enables (BWa\\-BWb\\, GW\\, BWE\\) tWH 0.5 0.5 0.5 ns 7, 8 Data-in tDH 0.5 0.5 0.5 ns 7, 8 Chip enable (CE\\) tCEH 0.5 0.5 0.5 ns 7, 8 OUTPUT TIMES SETUP TIMES HOLD TIMES NOTESUNITSSYMBOL CLOCK DESCRIPTION -9-8 -10 NOTES: 1. Test conditions as specifi ed with the output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V ± 5%) unless otherwise noted. 2. Measured as HIGH above VIH and LOW below VIL. 3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O. 4. This parameter is sampled. 5. Transition is measured ±500mV from steady state voltage. 6. OE\\ is a “Don’t Care” when a byte write enable is sampled LOW. 7. A READ cycle is defi ned by byte write enables all HIGH or ADSP\\ LOW for the required setup and hold times. A WRITE cycle is defi ned by at least one byte write enable LOW and ADSP\\ HIGH for the required setup and hold times. 8. This is a synchronous device. All addresses must meet the specifi ed setup and hold times for all rising edges of CLK when either ADSP\\ or ADSC\\ is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP\\ or ADSC\\ is LOW to remain enabled.
Rev. 2.5 10/13 Micross Components reserves the right to change products or specifi cations without notice. SSRAM AS5SS256K18 AC TEST CONDITIONS OUTPUT LOADS VIH = (VDD/2.2) + 1.5V VIL = (VDD/2.2) - 1.5V Input rise and fall times 1ns Input timing reference levels V DD/2.2 Output reference levels VDDQ/2.2 Output load See Figures 1 and 2 Input pulse levels 3.3v DQ Fig. 2 OUTPUT LOAD EQUIV ALENT 351 5 pF 317 Fig. 1 OUTPUT LOAD EQUIV ALENT DQ 50 Z0=50 Vt = 1.5V LOAD DERATING CURVES The 256K x 18 Synchronous Burst SRAM timing is dependent upon the capacitive loading on the outputs. SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced to I SB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, I SB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not quaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. * Except ZZ Don’t Care SNOOZE MODE WAVEFORM DESCRIPTION CONDITIONS SYM MIN MAX UNITS NOTES Current during SNOOZE MODE ZZ > VIH ISB2Z 45 mA ZZ active to input ignored tZZ tKC ns 1 ZZ inactive to input sampled tRZZ tKC ns 1 ZZ active to snooze current tZZI tKC ns 1 ZZ inactive to exit snooze current tRZZI 0n s 1 SNOOZE MODE ELECTRICAL CHARACTERISTICS NOTE: 1. This parameter is sampled. tZZ tRZZ tZZI ISB2 tRZZI CLK ZZ ISUPPLY ALL INPUTS*
Rev. 2.5 10/13 Micross Components reserves the right to change products or specifi cations without notice. SSRAM AS5SS256K18 READ TIMING NOTE: 1. Q(A2) referes to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2. 2. CE2\\ and CE2 have timing identical to CE\\. On this diagram, when CE\\ is LOW, CE2\\ is LOW and CE2 is HIGH. When CE\\ is HI GH, CE2\\ is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. 4. Outputs are disabled t KQHZ after deselect. CLK ADSP\\ ADSC\\ ADDRESS A2 BWE\\, GW\\, BWa\\-BWb\\ CE\\ (Note 2) ADV\\ OE\\ SINGLE READ BURST READ Q Q(A2) Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) Q(A2+2) Q(A1) Q(A2+1) tADSS tADSH tAS tAH tKC tKL tKH tADSS tADSH tWS tWH tCES tCEH tAAS tAAH ADV\\ suspends burst. High-Z tOEHZtKQLZ tKQ tOEQ tOELZ tKQ tKQX tKQHZ Burst wraps around to its initial state. (NOTE 1) Deselect Cycle (Note 4)
Rev. 2.5 10/13 Micross Components reserves the right to change products or specifi cations without notice. SSRAM AS5SS256K18 NOTE: 1. D(A2) refers to output from address A2. D(A2+1) refres to output from the next internal burst address following A2. 2. CE2\\ and CE2 have timing identical to CE\\. On this diagram, when CE\\ is LOW, CE2\\ is LOW and CE2 is HIGH. When CE\\ is HIG H, CE2\\ is HIGH and CE2 is LOW. 3. OE\\ must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable inputs being sampled. 4. ADV\\ must be HIGH to permit a WRITE to the loaded address. 5. Full-width WRITE can be initiated by GW\\ LOW; or GW\\ HIGH and BWE\\, BWa\\ and BWb\\ LOW. WRITE TIMING CLK ADSP\\ ADSC\\ ADDRESS A2 BEW\\, BWa\\ - BWb\\ CE\\ (NOTE 2) ADV\\ OE\\ SINGLE WRITE BURST WRITE GW\\ D Extended BURST WRITE A1 A3 D(A2) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2) D(A1) D(A2+1) tADSS tADSH tKC tKL tKH tAS tAH tADSS tADSH ADSC\\ extends burst. BYTE WRITE signals are ignored when ADSP\\ is LOW. tWS tWH tWS tWH(Note 5) tCES tCEH tAAS tAAH (Note 4) ADV\\ suspends burst. (Note 3) Q tOEHZ D(A2+1) (Note 1) High-Z BURST READ Don’t Care tDS tDH
Rev. 2.5 10/13 Micross Components reserves the right to change products or specifi cations without notice. SSRAM AS5SS256K18 NOTE: 1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the next internal burst address following A4. 2. CE2\\ and CE2 have timing identical to CE\\. On this diagram, when CE\\ is LOW, CE2\\ is LOW and CE2 is HIGH. When CE\\ is HIG H, CE2\\ is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP\\, ADSC\\, or ADV\\ cycle is performed. 4. GW\\ is HIGH. 5. Back-to-back READs may be controlled by either ADSP\\ or ADSC\\. 6. Timing is shown assuming that the device was not enabled before entering into this sequence. READ/WRITE TIMING6 CLK ADSP\\ ADSC\\ ADDRESS A2 BWE\\, GW\\ BWa\\ - BWb\\ CE\\ (Note 2) ADV\\ OE\\ Back-to-Back READS (NOTE 5) BURST READ D Back-to-Back WRITE’s D(A5) D(A6) D(A3) A1 A3 A4 SINGLE WRITE tKC tKL tKH tADSS tADSH tAS tAH tCES tCEH tWS tWH Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)Q High-Z tDS tDH tOELZ tKQ (NOTE 1) Don’t Care Undefi ned tOEHZ
Rev. 2.5 10/13 Micross Components reserves the right to change products or specifi cations without notice. SSRAM AS5SS256K18 MECHANICAL DEFINITIONS 100-Pin TQPF, Micross Case #1001 (Package Designator DQ) 16.00 +0.20/-0.05 14.00 + 0.10 22.10 + 0.10/-0.15 20.10 + 0.10 0.62 Pin #1 ID NOTE: 1. All dimensions in Millimeters (MAX/MIN) or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protursion is 0.25mm per side.
1.00 TYP
0.10 +0.10/-0.05 Gage Plane 0.25 1.50 + 0.10 1.40 + 0.05 0.10 See Detail A 0.15 +0.03/-0.02
Rev. 2.5 10/13 Micross Components reserves the right to change products or specifi cations without notice. SSRAM AS5SS256K18
ORDERING INFORMATION
*AVAILABLE PROCESSES IT = Industrial Temperature Range -40 oC to +85oC ET = Enhanced Temperature Range -40 oC to +105oC XT = Military Temperature Range -55 oC to +125oC 100-Pin TQFP EXAMPLE: AS5SS256K18DQ-8/IT Device Number Package Type Speed ns Process AS5SS256K18 DQ -8 /* AS5SS256K18 DQ -9 /* AS5SS256K18 DQ -10 /*
Rev. 2.5 10/13 Micross Components reserves the right to change products or specifi cations without notice. SSRAM AS5SS256K18 DOCUMENT TITLE 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through
REVISION HISTORY
Rev # History Release Date Status
2.2 Updated Micross Information January 2010 Release
2.3 Added copper lead frame and RoHS May 2011 Release
compliant options. Changed: From To C I 4pF 6pF C O 5pF 8pF I SB2Z 10mA 45mA I DDMax (-8) 375mA 225mA (-9) 325mA 205mA (-10) 250mA 185mA I SB2 Max 10mA 90mA I SB3 Max 25mA 120mA Deleted C A &CCK specifi cations. Corrected pin-out, pin 14 is NC not VSS. Changed V DD tolerance from +0.3V/-0.165V to ±5%. Deleted I DDI and IDD4 specs.
2.4 Added DQC package on the Thermal September 2011 Release
Resistance table, page 5.