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Technical content
Rev. 2.4 10/13 Micross Components reserves the right to change products or specifi cations without notice.
FEATURES
- Ultra High Speed Asynchronous Operation
- Fully Static, No Clocks
- Multiple center power and ground pins for improved noise immunity
- Easy memory expansion with CE\\ and OE\\ options
- All inputs and outputs are TTL-compatible
- Single +3.3V Power Supply +/- 0.3V
- Data Retention Functionality Testing
- Cost Ef fi cient Plastic Packaging
- Extended Testing Over -55ºC to +125ºC for plastics
- RoHS Compliant Options Available OPTIONS MARKING
- Timing 10ns access -10 12ns access -12 15ns access -15 20ns access -20 25ns access -25
- Operating Temperature Ranges 883C (-55 oC to +125oC) /883C Military (-55 oC to +125oC) /XT Industrial (-40 oC to +85oC) /IT
- Package(s) Ceramic Flatpack F No. 307 Ceramic LCC EC No. 210 Plastic SOJ (400 mils wide) DJ
- 2V data retention/low power* L PIN ASSIGNMENT (Top View) 36-Pin PSOJ (DJ) 36-Pin CLCC (EC) 36-Pin Flat Pack (F) AVAILABLE AS MILITARY SPECIFICATIONS
- MIL-STD-883 for Ceramic
- Extended Temperature Plastic (COTS) 512K x 8 SRAM
3.3 VOLT HIGH SPEED SRAM with
For more products and information please visit our web site at www.micross.com
Rev. 2.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. FUNCTIONAL BLOCK DIAGRAM TRUTH TABLE MODE OE\\ CE\\ WE\\ I/O POWER STANDBY X H X HIGH-Z STANDBY READ L L H Q ACTIVE NOT SELECTED H L H HIGH-Z ACTIVE WRITE X L L D ACTIVE SNOITCNUFNIP 81A-0As tupnIsserddA \\EWe lbanEetirW \\ECe lbanEpihC \\EOe lbanEtuptuO O/I 0 O/I- 7 stuptuO/stupnIataD V CC rewoP V SS dnuorG CNn oitcennoCoN X = Don’t Care VCC GND INPUT BUFFER 4,194,304-BIT MEMORY ARRAY
1024 ROWS X
4096 COLUMNS
*POWER DOWN CE\\ OE\\ WE\\ DQ8 DQ1 A0-A18 *On the low voltage Data Retention option. GENERAL DESCRIPTION The AS5LC512K8 is a 3.3V high speed SRAM. It offers fl ex- ibility in high-speed memory applications, with chip enable (CE\\) and output enable (OE\\) capabilities. These features can place the outputs in High-Z for additional fl exibility in system design. Writing to these devices is accomplished when write enable (WE\\) and CE\\ inputs are both LOW. Reading is accomplished when WE\\ remains HIGH and CE\\ and OE\\ go LOW. As a option, the device can be supplied offering a reduced power standby mode, allowing system designers to meet low standby power requirements. This device operates from a single +3.3V power supply and all inputs and outputs are fully TTL-compatible. The AS5LC512K8DJ offers the convenience and reliability of the AS5LC512K8 SRAM and has the cost advantage of a plastic en- capsulation. TSOPII with copper lead frames offers superior thermal performance.
Rev. 2.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. ABSOLUTE MAXIMUM RATINGS* V oltage on Vcc Supply Relative to Vss *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specifi cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airfl ow, and humidity. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TA < +125oC & -40oC < TA < +85oC ; Vcc = 3.3V +0.3%) CAPACITANCE DESCRIPTION SYM -10 -12 -15 -20 -25 UNITS NOTES ICCSP 90 80 70 60 55 mA "L" Version Only ICCLP -6 05 04 03 5 m A ISBTSP 30 20 20 20 20 mA "L" Version Only ISBTLP -1 51 51 51 5 m A ISBCSP 20 15 15 15 15 mA "L" Version Only ISBCLP - 9999 m A MAX 3, 2 Power Supply Current: Standby CONDITIONS CE\\ < VIL; Vcc = MAX f = MAX = 1/tRC Outputs Open CE\\ > VIH, All other inputs < VIL, Vcc = MAX, f = 0, Outputs Open CE\\ > Vcc -0.2V; Vcc = MAX VIN<Vss +0.2V or VIN>Vcc -0.2V; f = 0 Power Supply Current: Operating µ µ PARAMETER CONDITIONS SYMBOL MA X UNITS NOTES Input Capacitance CI 8p F4 Output Capactiance Co 6 pF 4 TA = 25oC, f = 1MHz VIN = 0
Rev. 2.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3%) MIN MA X MIN MA X MIN MA X MIN MA X MIN MA X READ CYCLE Read Cycle Time tRC 10 12 15 20 25 ns Address Access Time tAA 10 12 15 20 25 ns Chip Enable Access Time tACE 10 12 15 20 25 ns Output Hold From Address Change tOH 22222n s Chip Enable to Output in Low-Z tLZCE 22222n s 4 , 6 , 7 Chip Disable to Output in High-Z tHZCE 4 6 7 8 9 ns 4, 6, 7 Output Enable Acess Time tAOE 4.5 6 7 8 9 ns Output Enable to Output in Low-Z tLZOE 00000n s 4 , 6 , 7 Output Disable to Output in High-Z tHZOE 4 6 7 8 9 ns 4, 6, 7 WRITE CYCLE WRITE Cycle Time tWC 10 12 15 20 25 ns Chip Enable to End of Write tCW 8 8 10 12 13 ns Address Valid to End of Write tAW 8 8 10 12 13 ns Address Setup Time tAS 00000n s Address Hold From End of Write tAH 00000n s WRITE Pulse Width tWP 8 1 01 21 51 5 n s Data Setup Time tDS 66788n s Data Hold Time tDH 11111n s Write Disable to Output in Low-Z tLZWE 22222n s 4 , 6 , 7 Write Enable to Output in High-Z tHZWE 5 5 6 7 7 ns 4, 6, 7 UNITS NOTESSYMDESCRIPTION -20-15-12 -25-10
Rev. 2.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. NOTES 1. All voltages referenced to V SS (GND). 2. I CC limit shown is for absolute worst case switching of ADDR, ADDR\\, ADDR, etc. 3. I CC is dependent on output loading and cycle rates. 4. This parameter is guaranteed but not tested. 5. Test conditions as speci fi ed with the output loading as shown in Fig. 1 unless otherwise noted. tLZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE are speci fi ed with CL = 5pF as in Fig. 2. Transition is measured ±200mV from steady state voltage. 7. At any given temperature and voltage condition, t HZCE is less than tLZCE, and tHZWE is less than t LZWE. 8. WE\\ is HIGH for READ cycle. 9. Device is continuously selected. Chip enables and output enables are held in their active state. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. t RC = Read Cycle Time. 12. Chip enable and write enable can initiate and terminate a WRITE cycle. 13. Output enable (OE\\) is inactive (HIGH). 14. Output enable (OE\\) is active (LOW). 15. ASI does not warrant functionality nor reliability of any product in which the junction temperature exceeds 150°C. Care should be taken to limit power to acceptable levels. Fig. 1 Output Load Equivalent Fig. 2 Output Load Equivalent DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) AC TEST CONDITIONS DESCRIPTION SYM MIN MAX UNITS NOTES Vcc for Retention Data VDR 2V Data Retention Current Vcc = 2.0V ICCDR 6.5 mA Chip Deselect to Data tCDR 0n s 4 Operation Recovery Time tR 20 ms 4, 11 CONDITIONS CE\\ > VCC -0.2V VIN > VCC -0.2 or 0.2V 3.3V Q 353 5 pF 319 Q 30 pF RL = 50 VL = 1.5V ZO=50
Rev. 2.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. LOW VCC DATA RETENTION WAVEFORM READ CYCLE NO. 11, 2 (Address Controlled, CE\\ = OE\\ = VIL, WE\\ = VIH) READ CYCLE NO. 2 (WE\\ = VIH) Don’t Care Undefi ned DATA RETENTION MODE 3.0V 3.0V VDR > 2V VDR tCDR tR VCC CE\\ VIH- VIL- ADDRESS tRC tOH tAA Previous Data Valid Data ValidI/O, DATA IN & OUT V ALID ADDRESS tRC tAOE CE\\ tLZOE tACE Data ValidHigh-Z tHZOE tHZCE tPD I/O, DATA IN & OUT Icc tLZCE tPU NOTES: 1. WE\\ is HIGH for READ cycle. 2. Device is continuously selected. Chip enables and output enables are held in their active state.
Rev. 2.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. WRITE CYCLE NO. 11 (CE Controlled) WRITE CYCLE NO. 21, 2 (Write Enabled Controlled) ADDRESS tWC tCW CE\\ tAW Data Valid tAH tAS I/O, DATA OUT tWP1 tDS tDH WE\\ I/O, DATA IN High-Z High-Z ADDRESS tWC tCW CE\\ tAW Data Valid tAH tAS I/O, DATA OUT tWP1 tDH WE\\ I/O, DATA IN High-Z High-Z NOTES: 1. Chip enable and write enable can initiate and terminate a WRITE cycle. 2. Output enable (OE\\) is inactive (HIGH).
Rev. 2.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. WRITE CYCLE NO. 31, 2, 3 (WE Controlled) ADDRESS tWC tCW CE\\ tAW Data Valid tAH tAS DATA OUT Data Undefi ned tWP2 tDS tDH tHZWE tLZWE WE\\ DATA IN High-Z NOTES: 1. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE. 2. Chip enable and write enable can initiate and terminate a WRITE cycle. 3. Output enable (OE\\) is active (LOW).
Rev. 2.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. MECHANICAL DEFINITIONS* Micross Case #307 (Package Designator F) Bottom View 36 1 c A Q *All measurements are in inches. D e b Top View S EL Pin 1 identifi er area MIN MA X A 0.096 0.125 b 0.015 0.022 c 0.003 0.009 D 0.910 0.930 D1 0.840 0.860 E 0.505 0.515 E2 0.385 0.397 e L 0.250 0.370 Q 0.020 0.045 SYMBOL MICROSS SPECIFICATIONS
0.050 BSC
Rev. 2.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. *All measurements are in inches. MECHANICAL DEFINITIONS* Package Designator DJ MIN MA X A 0.128 0.148 A1 0.025 --- A2 0.082 --- B 0.015 0.020 b 0.026 0.032 C 0.007 0.013 D 0.920 0.930 E 0.435 0.445 E1 0.395 0.405 e SYMBOL MICROSS SPECIFICATIONS
0.370 BSC
Rev. 2.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. MECHANICAL DEFINITIONS* Micross Case #210 (Package Designator EC) D E Pin 1 identifi er area L e B R *All measurements are in inches. A P MIN MA X A 0.080 0.100 A1 0.054 0.066 B 0.022 0.028 D 0.910 0.930 D1 0.840 0.860 E 0.445 0.460 e L L2 0.115 0.135 P --- 0.006 R 0.009 TYP MICROSS SPECIFICATIONS SYMBOL
0.100 TYP
Rev. 2.4 10/13 Micross Components reserves the right to change products or specifi cations without notice.
ORDERING INFORMATION
*AVAILABLE PROCESSES IT = Industrial Temperature Range -40 oC to +85oC XT = Extended Temperature Range -55 oC to +125oC 883C = Full Military Processing1 -55 oC to +125oC OPTIONS DEFINITIONS L = 2V Data Retention / Low Power NOTES: 1. 883C process available with ceramic packaging only. 36-Pin Ceramic Flat Pack Device Number Package Type Speed ns Options Process AS5LC512K8 F -10 L /* AS5LC512K8 F -12 L /* AS5LC512K8 F -15 L /* AS5LC512K8 F -25 L /* 36-Pin Plastic PSOJ Device Number Package Type Speed ns Options** Process AS5LC512K8 DJ -12 L /* AS5LC512K8 DJ -15 L /* AS5LC512K8 DJ -20 L /* AS5LC512K8 DJ -25 L /* 36-Pin Ceramic CLCC Device Number Package Type Speed ns Options** Process AS5LC512K8 EC -12 L /* AS5LC512K8 EC -15 L /* AS5LC512K8 EC -20 L /* AS5LC512K8 EC -25 L /* EXAMPLE: AS5LC512K8F-12L/XT EXAMPLE: AS5LC512K8DJ-20L/IT EXAMPLE: AS5LC512K8EC-15L/IT
Rev. 2.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. DOCUMENT TITLE 512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM with CENTER POWER PINOUT Rev # History Release Date Status 2.1 Pg 1: Changed 0.3% to 0.3V August 2009 Release
2.2 Updated Micross Information January 2010 Release
2.3 Expanded package offering to include March 2011 Release
Copper Lead Frames and RoHS Compliancy, added -10 speed option, Reduced C L from 9pF to 8pF, corrected t HZWE from min’s to max’s on page 4, corrected 4.5V reference points on data retention waveform to 3.0V, pg. 6