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Rev. 1.4 10/13 Micross Components reserves the right to change products or specifi cations without notice.
FEATURES
- High-speed access times of 10, 12, 15 and 20 ns
- High-performance, low-power CMOS process
- Multiple center power and ground pins for greater noise immunity
- Easy memory expansion with CE\\ and OE\\ options
- CE\\ power-down
- Fully static operation: no clock or refresh required
- TTL compatible inputs and outputs
- Single 3.3V power supply
- RoHS compliant options available GENERAL DESCRIPTION 128K x 8 SRAM High-Speed CMOS SRAM with 3.3V Revolutionary Pinout PIN ASSIGNMENT (Top View) 32-Pin, 400-mil Plastic SOJ (DJ) & Plastic TSOPII (DGC & DGCR) The AS5LC1008 is a very high-speed, low power, 131,072-word by 8-bit CMOS static RAM in revolutionary pinout. The AS5LC1008 is fabricated using high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE\\ is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250μW (typical) with CMOS input levels. The AS5LC1008 operates from a single 3.3V power supply and all inputs are TTL-compatible. OPTIONS MARKING
- Timing 10ns access -10 12ns access -12 15ns access -15 20ns access -20
- Package Plastic SOJ (32-pin, 400-mil) DJ No. 906
- Operating Temperature Ranges -Military (-55 oC to +125oC) /XT -Industrial (-40 oC to +85oC) /IT
- 2V Data Retention / Low Power L For more products and information please visit our web site at www.micross.com PIN FUNCTIONS CE\\ I/O 0 I/O 1 Vcc GND I/O 2 I/O 3 WE\\ A16 A15 A14 A13 OE\\ I/O 7 I/O 6 GND Vcc I/O 5 I/O 4 A12 A11 A10 PIN DESCRIPTION A0 - A16 Address Inputs CE\\ Chip Enable Input OE\\ Output Enable Input WE\\ Write Enable Input I/O0 - I/O7 Bidirectional Ports VCC Power GND Ground
Rev. 1.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specifi cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL BLOCK DIAGRAM TRUTH TABLE Mode WE \\ CE\\ OE\\ I/O Operation Not Selected (Power-down) X H X High-Z Output Disabled H L H High-Z Read H L L D OUT Write L L X DIN A0 - A16 VCC GND I/O0 - I/O7 CE\\ OE\\ WE\\ DECODER 128K x 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O CONTROL CIRCUIT
Rev. 1.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Output HIGH Voltage VOH VCC = Min., IOH = -4.0mA 2.4 --- V Output LOW Voltage VOL VCC = Min., IOL = 8.0mA --- 0.4 V Input HIGH Voltage VIH 2.2 VCC + 0.3 V Input LOW Voltage1 VIL -0.3 0.8 V Input Leakage ILI GND < VIN < VCC -5 5 μA Output Leakage ILO GND < VOUT < VCC; Outputs Disabled -5 5 μA NOTE: 1. VIL = -3.0V for pulse width less than 10ns. POWER SUPPLY CHARACTERISTICS1 (-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V) NOTE: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE1,2 PARAMETER SYMBOL CONDITIONS MAX UNIT Input Capacitance CIN VIN = 0V 6p F Input/Output Capacitance CI/O VOUT = 0V 8p F NOTE: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1MHz, VCC = 3.3V . PARAMETER SYM CONDITIONS MIN MA X MIN MA X MIN MA X MIN MA X UNIT VCC Dynamic Operating Supply Current ICC VCC = Max, CE\\ = VIL, IOUT = 0 mA, f = Max ISB VCC = Max, VIN = VIH or VIL CE\\ > VIH, f = Max ISB1 VCC = Max, VIN = VIH or VIL CE\\ > VIH, f = 0 CMOS Standby Current (CMOS Inputs) ISB2 VIN > VCC - 0.2V, or VIN < 0.2V, f = 0 -10 -12 -20 TTL Standby Current (TTL Inputs) -15
Rev. 1.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. DATA RETENTION SWITCHING CHARACTERISTICS (Low Power “L” Version) Symbol Parameter Test Condition Min. Typ. Max. Unit VDR VDDforDataRetention SeeDataRetentionWaveform 2.0 Ͳ 3.6 V IDR DataRetentionCurrent VDD=2.0V,CE\\шVDDͲ0.2V Ͳ Ͳ 2m A ISDR DataRetentionSetupTime See DataRetentionWaveform 0 Ͳ Ͳ ns IRDR RecoveryTime See DataRetentionWaveform tRC Ͳ Ͳ ns NOTES: 1. Typical values are measured at VDD=3.0V , TA=25oC and not 100% tested. VDD CE ≥ VDD - 0.2V tSDR tRDR VDR CE GND Data Retention Mode DATA RETENTION SWITCHING WAVEFORM (CE\\ Controlled)
Rev. 1.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. READ CYCLE #11,2 READ CYCLE #21,3 NOTES: 1. WE\\ is HIGH for a Read Cycle. 2. The device is continuously selected. OE\\, CE\\ = VIL. 3. Address is valid prior to or coincident with CE\\ LOW transitions.
Rev. 1.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. WRITE CYCLE SWITCHING CHARACTERISTICS1,3 (-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V) WRITE CYCLE #11,2 (CE\\ Controlled, OE\\ = HIGH or LOW) NOTES: 1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V , input pulse levels of 0 to 3.0V and output loading specifi ed in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defi ned by the overlap of CE\\ LOW and WE\\ LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. -10 PARAMETER SYMBOL MIN MA X MIN MA X MIN MA X MIN MA X UNITS Write Cycle Time tWC 10 --- 12 --- 15 --- 20 --- ns CE\\ to Write End tSCE 7 --- 8 --- 9 --- 10 --- ns Address Setup Time to Write End tAW 8 --- 9 --- 10 --- 12 --- ns Address Hold from Write End tHA 0 --- 0 --- 0 --- 0 --- ns Address Setup Time tSA 0 --- 0 --- 0 --- 0 --- ns WE\\ Pulse Width (OE\\ HIGH) tPWE1 WE\\ Pulse Width (OE\\ LOW) tPWE2 Data Setup to Write End tSD 5 --- 6 --- 7 --- 8 --- ns Data Hold to Write End tHD 0 --- 0 --- 0 --- 0 --- ns WE\\ LOW to High-Z Output tHZWE WE\\ HIGH to Low-Z Output tLZWE -20-12 -15
Rev. 1.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. NOTES: 1. The internal write time is defi ned by the overlap of CE\\ LOW and WE\\ LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE\\ • VIH. WRITE CYCLE #3 (WE\\ Controlled, OE\\ = LOW during Write Cycle) WRITE CYCLE #21 (WE\\ Controlled, OE\\ = HIGH during Write Cycle)
Rev. 1.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. Micross Case #906 (Package Designator DJ) MECHANICAL DEFINITION* * All measurements are in inches. MIN MAX A 0.128 0.148 A1 0.025 --- A2 0.082 --- B 0.015 0.020 b 0.026 0.032 C 0.007 0.013 D 0.820 0.830 E 0.435 0.445 E1 0.395 0.405 e
0.370 BSC
0.050 BSC
Rev. 1.4 10/13 Micross Components reserves the right to change products or specifi cations without notice.
ORDERING INFORMATION
*AVAILABLE PROCESSES IT = Industrial Temperature Range -40 oC to +85oC XT = Military Temperature Range -55 oC to +125oC OPTION DEFINITIONS L = 2V Data Retention / Low Power Plastic SOJ Device Number Package Type Speed ns Options Process AS5LC1008 DJ -10 L /* AS5LC1008 DJ -12 L /* AS5LC1008 DJ -15 L /* AS5LC1008 DJ -20 L /* EXAMPLE: AS5LC1008DJ-12/XT
Rev. 1.4 10/13 Micross Components reserves the right to change products or specifi cations without notice. DOCUMENT TITLE 128K x 8 SRAM High-Speed CMOS SRAM with 3.3V Revolutionary Pinout Rev # History Release Date Status
1.2 Added Micross Information January 2010 Release
1.3 Added TSOPII Copper Lead Frame March 2011 Release
and RoHS compliant parts, pg 1 &10, Reduced Power Supply Currents: Parameter Speed From (mA) To (mA) ICC -10 160 105 ICC -12 140 100 ICC -15 130 95 ICC -20 120 90 ISB -10 45 35 ISB -12 40 30 ISB -15 35 25 ISB -20 30 20 ISB1 -10 30 20 ISB1 -12 30 20 ISB1 -15 30 20 ISB1 -20 30 20 ISB2 -10 10 2 ISB2 -12 10 2 ISB2 -15 10 2 ISB2 -20 10 2 Added “L” Versions