AS5C1008 MICROSS | Alldatasheet
Document overview
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Technical content
Rev. 3.9 10/10 Micross Components reserves the right to change products or specifi cations without notice.
FEATURES
- Access times of 15, 20, 25 and 35 ns
- Fast output enable (tAOE) for cache applications
- Low active power
- Low standby power
- Fully static operation, no clock or refresh required
- TTL Compatible Inputs and Outputs
- Single +5V power supply
- Package in Industry-standard 32-pin SOJ 128K x 8 SRAM RUGGEDIZED PLASTIC HIGH SPEED SRAM PIN ASSIGNMENT (Top View) 32-Pin Plastic SOJ (DJ) GENERAL DESCRIPTION The AS5C1008 is a high speed, low power, 128K by 8-bit ruggedized plastic (COTS) CMOS Static RAM. It is fabricated using high performance, CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 15ns (Max) over the military and industrial temperature ranges. When Chip Enable (CE\\) is HIGH, the device assumes a standby mode at which the power dissipation can be reduced down to 125mW (max) at CMOS input levels. Easy memory expansion is provided by using asserted LOW CE\\ and asserted HIGH CE2, and asserted LOW write en- able (WE\\) controls both writing and reading of the memory. TheAS5C1008 is pin-compatible with other 128K x 8 SRAM’s in the SOJ package. *For ceramic versions of this product, please see the MT5C1008 datasheet. OPTIONS MARKING
- Timing 15ns access -15 20ns access -20 25ns access -25 35ns access -35
- Package Plastic SOJ* DJ No. 905
- Operating Temperature Ranges -Military (-55 oC to +125oC) XT -Industrial (-40 oC to +85oC) IT For more products and information please visit our web site at www.micross.com PIN FUNCTIONS A0 - A16 Address Inputs WE\\ Write Enable CE\\1, CE2 Chip Enable OE\\ Output Enable I/O0 - I/O7 Data Inputs/Outputs VCC Power VSS Ground NC No Connection NC A16 A15 A14 A13 I/O0 I/O1 I/02 Vss Vcc CE WE\\ A10 A11 OE\\ A12 CE\\ I/O7 I/O6 I/O5 I/O4 I/O3
Rev. 3.9 10/10 Micross Components reserves the right to change products or specifi cations without notice. ABSOLUTE MAXIMUM RATINGS* oC to +125oC *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operation section of this specifi cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL BLOCK DIAGRAM Address A16 I/O0 Data I/O7 CE\\1 CE2 WE\\ OE\\ Decoder Input Data Control Memory Matrix Column I/O
Rev. 3.9 10/10 Micross Components reserves the right to change products or specifi cations without notice. PARAMETER CONDITIONS SYMBOL MIN MA X MIN MA X MIN MA X MIN MA X UNITS Dynamic Operating Current Vcc=MAX, IOUT = 0mA, CE1 = VIL and CE2 = VIH, f = fmax ICC1 180 150 140 125 mA TTL Standby Current - TTL Inputs Vcc=MAX, VIN = VIH or VIL, CE\\1> VIH and CE2 > VIL, f = fmax ISB1 90 75 70 60 mA CMOS Standby Current - CMOS Inputs Vcc=MAX, CE\\1 > Vcc -0.2V, or CE2 < 0.2V, VIN > Vcc -0.2V and VIN < 0.2V, f = 0 ISB2 10 10 10 10 mA Input Leakage Current GND < VIN < Vcc I LI -10 10 -10 10 -10 10 -10 10 PA Output Leakage Current GND < VOUT < Vcc Output Disabled ILO -10 10 -10 10 -10 10 -10 10 PA Input High Voltage V IH 2.2 Vcc +0.5 2.2 Vcc +0.5 2.2 Vcc +0.5 2.2 Vcc +0.5 V -15 -20 -25 -35 ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC<TA<+125oC or -40oC to +85oC; Vcc = 5V+10%) PIN DESCRIPTIONS A0 - A16: Address Inputs These 17 address inputs select one of the 131,072 8-bit words in the RAM. CE\\ 1: Chip Enable 1 Input CE\\1 is asserted LOW to read from or write to the device. If Chip Enable 1 is deasserted, the device is deselected and is in standby power mode. The I/O pins will be in the high- impedance state when the device is deselected. CE 2: Chip Enable 2 Input CE2 is asserted HIGH to read from or write to the device. If Chip Enable 2 is deasserted, the device is deselected and is in standby power mode. The I/O pins will be in the high- impedance state when the device is deselected. OE\\: Output Enable Input The Output Enable Input is asserted LOW. If asserted LOW while CE\\ 1 is asserted (LOW) and CE2 is asserted (HIGH) and WE\\ is deasserted (HIGH), data from the SRAM will be present on the I/O pins. The I/O pins will be in the high-impedance state when OE\\ is deasserted. WE\\: Write Enable Input The Write Enable input is asserted LOW and controls read and write operations. When CE\\ 1 and WE\\ are both asserted (LOW) and CE2 is asserted (HIGH) input data present on the I/O pins will be written into the selected memory location.
Rev. 3.9 10/10 Micross Components reserves the right to change products or specifi cations without notice. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (-55oC<TA<+125oC or -40oC to +85oC; Vcc = 5V+10%) NOTE: 1. tLZCE, tLZWE, tHZCE, tLZOE, and tHZOEare simulated values. DESCRIPTION SYMBOL1 MIN MAX MIN MAX MIN MAX MIN MAX UNIT READ CYCLE Read Cycle Time t RC 15 20 25 35 ns Address Access Time t AA 15 20 25 35 ns Chip Enable Access Time t ACE 15 20 25 35 ns Output Hold from Address Change t OH 333 3 ns Chip Enable to Output in Low-Z t LZCE 333 3 ns Chip Disable to Output in High-Z t HZCE 7 8 10 15 ns Output Enable Access Time t AOE 7 7 10 15 ns Output Enable to Output in Low-Z t LZOE 0000n s Output Disable to Output in High-Z t HZOE 7 8 10 15 ns WRITE CYCLE Write Cycle Time t WC 15 20 25 35 ns Chip Enable to End of Write t CW 12 15 20 25 ns Address Valid to End of Write t AW 12 15 20 25 ns Address Set-up Time t AS 0000n s Address Hold from End of Write t AH 0000n s Write Pulse Width (OE\\ > VIH) tWP 12 15 20 30 ns Data Set-up Time t DS 81 0 1 5 2 0n s Data Hold Time t DH 0000n s Write Disable to Output in Low-Z t LZWE 5555n s Write Enable to Output in High-Z t HZWE 7 9 10 15 ns -15 -20 -25 -35
Rev. 3.9 10/10 Micross Components reserves the right to change products or specifi cations without notice. AC TEST CONDITIONS Fig. 1 OUTPUT LOAD EQUIVALENT +5V Q 255Ω 30 480Ω +5V Q 255Ω 5 pF 480Ω for tLZCE, tHZCE, tLZWE, tHZWE, tLZOE, and tHZOE CAPACITANCE (TA = +25oC, f = 1.0 MHz) PARAMETER CONDITION SYMBOL MAX UNIT Input Capacitance VIN = 0V C IN 6p F Output Capacitance VOUT = 0V C OUT 8p F
Rev. 3.9 10/10 Micross Components reserves the right to change products or specifi cations without notice. READ CYCLE TIMING 1(1) NOTE: 1. CE\\ is HIGH for READ cycle. READ CYCLE TIMING 2 (1) tRC tAAtOH ADDR DOUT DATA V ALIDPREVIOUS DATA V ALID NOTES: 1. CE\\ is HIGH for READ cycle. 2. At any given temperature and voltage condition, t HZCE is less than tLZCE. DATA V ALID tRC tACE tAOE tLZCE tL- High-Z tHZCE tHZCE (2) CE\\1 CE2 OE\\ DOUT WRITE CYCLE TIMING (WE\\ CONTROLLED, OE\\ = LOW) DATA High-Z tWC tAW tCW tAH tAS tWP2 tDS tDH tLZWE tHZ- UNDEFINED DON’T CARE ADDR CE\\1 CE2 WE\\ DIN DOUT
Rev. 3.9 10/10 Micross Components reserves the right to change products or specifi cations without notice. WRITE CYCLE TIMING (CE\\1 CONTROLLED, OE\\ = LOW) UNDEFINED DON’T CARE DATA V ALID High-Z tAW tCW tAH tDH ADDR CE\\1 CE2 WE\\ DIN DOUT WRITE CYCLE TIMING (CE2 CONTROLLED, OE\\ = LOW) DATA V ALID High-Z tWC tAW tCW tAH tAS tWP1 tDS tDH ADDR CE\\1 CE2 WE\\ DIN DOUT tWC tAS tWP1 tDS
Rev. 3.9 10/10 Micross Components reserves the right to change products or specifi cations without notice. Micross Case #905 (Package Designator DJ) MECHANICAL DEFINITION* * All measurements are in inches. D E A A1 A2 e1 e e2b C B MIN MAX A A1 0.105 0.115 B 0.082 ͲͲͲ b C D 0.820 0.880 E 0.430 0.445 E1 0.395 0.405 E2 0.360 0.380 e 0.025 0.032 e2 ͲͲͲ 0.045 0.050TYP MICROSSPACKAGESPECIFICATION S SYMBOL 0.140BSC 0.027TYP 0.018TYP 0.010TYP
Rev. 3.9 10/10 Micross Components reserves the right to change products or specifi cations without notice.
ORDERING INFORMATION
*AVAILABLE PROCESSES IT = Industrial Temperature Range -40 oC to +85oC XT = Extended Temperature Range -55 oC to +125oC Device Number Package Type Speed ns Process AS5C1008 DJ -15 /* AS5C1008 DJ -20 /* AS5C1008 DJ -25 /* AS5C1008 DJ -35 /* EXAMPLE: AS5C1008DJ-25/XT
Rev. 3.9 10/10 Micross Components reserves the right to change products or specifi cations without notice. DOCUMENT TITLE 128K x 8 SRAM RUGGEDIZED PLASTIC HIGH SPEED SRAM
REVISION HISTORY
Rev # History Release Date Status