AS5181

AS5181 MICROSS | Alldatasheet

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Technical content

Rev. 0.4 01/10 Micross Components reserves the right to change products or specifi cations without notice.

FEATURES

• +2.7V to +3.3V Single-Supply Operation
• Wide Spurious-Free Dynamic Range: 70dB at f OUT = 2.2MHz
• Fully Differential Output
• Low-Current Standby or Full Shutdown Modes
• Internal +1.2V , Low-Noise Bandgap Reference
• Small 24-Pin Flat-pack Package OPTIONS MARKING
• Package(s) 24-Pin Flat-pack F
• Operating Temperature Ranges Extended Temperature (-55 oC to +125oC) XT Industrial Temperature (-40°C to +85°C) IT Military Processing (-55°C to +125°C) MIL Space Processing (-55 oC to +125oC) SPACE

10 Bit, 40MHz

For more products and information please visit our web site at www.micross.com GENERAL DESCRIPTION The AS5181 is a 10-bit, current-output digital-to-analog converter (DAC) designed for superior performance in signal reconstruction or arbitrary waveform generation applications requiring analog signal reconstruction with low distortion and low-power operation. The AS5181 are designed for a 10pVs glitch operation to minimize unwanted spurious signal components at the output. An on-board 1.2V bandgap circuit provides a well-regulated, low-noise reference that can be disabled for external reference operation. The devices are designed to provide a high level of sig- nal integrity for the least amount of power dissipation. They operate from a single 2.7V to 3.3V supply. Additionally, these DACs have three modes of operation: normal, low- power standby, and full shutdown, which provides the lowest possible power dissipation with a 1μA (max) shutdown current. A fast wake-up time (0.5μs) from standby mode to full DAC operation facilitates power conservation by activating the DAC only when required. PIN ASSIGNMENT (Top View) 24-Pin Flat Pack (F)

Rev. 0.4 01/10 Micross Components reserves the right to change products or specifi cations without notice. *Stresses at or greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this speci fi cation is not implied. Exposure to absolute maximum rating conditions for extended periods will affect reliability. ABSOLUTE MAXIMUM RATINGS* V AV Continuous Power Dissipation (TA = +70°C) 24-Pin Flatpack (derate 9.50mW/°C above +70°C) ...762mW ELECTRICAL CHARACTERISTICS (AVDD = DVDD = +3V ±10%, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400Ω differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (continued) PARAMETER SYM MIN TYP MA X UNITS STATIC PERFORMANCE Resolution N 10 Bits Intergral Nonlinearity INL -2 ±0.5 +2 LSB Differential Nonlinearity DNL -1 ±0.5 1 LSB Zero-Scale Error -2 +2 LSB Full-Scale Error -40 ±15 +40 LSB DYNAMIC PERFORMANCE Output Settling Time 25 ns Glitch Impulse 10 pVs fOUT = 550kHz 72 TA = +25°C fOUT = 2.2MHz 57 70 fOUT = 550kHz -70 TA = +25°C fOUT = 2.2MHz -68 -63 fOUT = 550kHz 61 TA = +25°C fOUT = 2.2MHz 56 59 Clock and Data Feedthrough 50 nVs Output Noise 10 pA/Hz ANALOG OUTPUT Full-Scale Output Voltage VFS 400 mV Voltage Compliance of Output -0.3 0.8 V Output Leakage Current -1 1 μA Full-Scale Output Current IFS 0.5 1 1.5 mA DAC External Output Resistor Load RL 400 Ω dB dB dBc DACEN = 0 SFDR THD SNR All 0s to all 1s Signal-to-Noise Ratio to Nyquist To ±0.5LSB error band fCLK = 40MHz fCLK = 40MHz fCLK = 40MHz Spurious-Free Dynamic Range to Nyquist Total Harmonic Distortion to Nyquist CONDITION Guaranteed monotonic

Rev. 0.4 01/10 Micross Components reserves the right to change products or specifi cations without notice. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = +3V ±10%, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400Ω differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (continued) PARAMETER CONDITION SYM MIN TYP MA X UNITS REFERENCE Output Voltage Range VREF 1.12 1.2 1.28 V Output Voltage Temperature Drift TCVREF 50 ppm/°C Reference Output Drive Capability IREFOUT 10 μA Reference Supply Rejection 0.5 mV/V Current Gain (IFS/IREF) 8 mA/mA POWER REQUIREMENTS Analog Power-Supply Voltage AVDD 2.7 3.3 V Analog Supply Current PD = 0, DACEN = 1, digital inputs at 0 or DVDD IAVDD 1.7 4.0 mA Digital Power-Supply Voltage DV DD 2.7 3.3 V Digital Supply Current PD = 0, DACEN = 1, digital inputs at 0 or DV DD IDVDD 4.2 5.0 mA Standby Current PD = 0, DACEN = 1, digital inputs at 0 or DV DD ISTANDBY 11 . 5 m A Shutdown Current PD = 1, DACEN = X, digital inputs at 0 or DVDD (X = don't care) ISHDN 0.5 1 μA LOGIC INPUTS AND OUTPUTS Digital Input Voltage High VIH 2V Digital Input Voltage Low VIL 0.8 V Digital Input Current VIN = 0 or DVDD IIN ±1 μA Digital Input Capacitance CIN 10 pF TIMING CHARACTERISTICS DAC DATA to CLK Rise Setup Time tDS 10 ns DAC CLK Rise to DATA Hold Time tDH 0n s CS\\ Fall to CLK Rise Time 5n s CS\\ Fall to CLK Fall Time 5n s DACEN Rise Time to VOUT 0.5 μs PD Fall Time to VOUT 50 μs Clock Period tCLK 25 ns Clock High Time tCH 10 ns Clock Low Time tCL 10 ns

Rev. 0.4 01/10 Micross Components reserves the right to change products or specifi cations without notice. TYPICAL OPERATING CHARACTERISTICS (AVDD = DVDD = +3V, AGND = DGND = 0, IFS = 1mA, 400Ω differential output, CL = 5pF, TA = +25°C, unless otherwise noted.)

Rev. 0.4 01/10 Micross Components reserves the right to change products or specifi cations without notice. TYPICAL OPERATING CHARACTERISTICS (AVDD = DVDD = +3V, AGND = DGND = 0, IFS = 1mA, 400Ω differential output, CL = 5pF, TA = +25°C, unless otherwise noted.) (continued)

Rev. 0.4 01/10 Micross Components reserves the right to change products or specifi cations without notice. TYPICAL OPERATING CHARACTERISTICS (AVDD = DVDD = +3V, AGND = DGND = 0, IFS = 1mA, 400Ω differential output, CL = 5pF, TA = +25°C, unless otherwise noted.) (continued)

Rev. 0.4 01/10 Micross Components reserves the right to change products or specifi cations without notice. PIN DESCRIPTION PIN NAME FUNCTION

1 CREF REFO

2 OUTP Positive Analog Output, Current Output

3 OUTN Negative Analog Output, Current Output

4 AGND Analog Ground

DD Analog Positive Supply, +2.7V to +3.3V

6 DACEN

DAC Enable, Digital Input 0: Enter DAC standby mode with PD = DGND 1: Power-up DAC with PD = DGND X: Enter shutdown mode with PD = DV DD (X = Don't Care) 7P D Power-Down Select 0: Enter DAC standby mode (DACEN = DGND) or power-up DAC (DACEN = DVDD) 1: Enter shutdown mode

8 CS\\ Active-Low Chip Select

9 CLK Clock Input

10 REN\\ Active-Low Reference Enable. Connect to DGND to activate on-chip +1.2V reference.

11 D0 Data Bit D0 (LSB)

12 - 19 D1 - D8 Data Bits D1 - D8

20 D9 Data Bit D9 (MSB)

21 DV DD Digital Supply, +2.7V to +3.3V

22 DGND Digital Ground

23 REFR Reference Input

24 REFO Reference Output

Rev. 0.4 01/10 Micross Components reserves the right to change products or specifi cations without notice. DETAILED DESCRIPTION The AS5181 is a 10-bit digital-to-analog converters (DACs) capable of operating with clock speeds up to 40MHz. Each converter consists of separate input and DAC registers, followed by a current source array capable of generating up to 1.5mA full-scale output current (Figure 1). An integrated 1.2V voltage reference and control ampli fi er determine the data converters’ full-scale output currents/voltages. Careful reference design ensures close gain matching and excellent drift characteristics. Internal Reference and Control Amplifi er The AS5181 provide an integrated 50ppm/°C, 1.2V , low-noise bandgap reference that can be disabled and overridden by an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN\\ is connected to DGND, the internal reference is selected and provides a +1.2V output. Due to its limited 10μA output drive capability, REFO must be buffered with an external amplifi er, if heavier loading is required. The AS5181 also employ a control ampli fi er designed to regulate simultaneously the full-scale output current (I FS) for both outputs of the devices. The output current is calculated as follows: I FS = 8 . IREF where IREF is the reference output current (IREF = VREFO/RSET) and IFS is the full-scale output current. R SET is the reference resistor that determines the ampli fi er’s output current on the AS5181 (Figure 2). This current is mirrored into the current source array, where it is equally distributed between matched current segments and summed to valid output current readings for the DACs. FIGURE 1: Functional Diagram

Rev. 0.4 01/10 Micross Components reserves the right to change products or specifi cations without notice. POWER-DOWN MODE SELECTION PD (POWER-DOWN SELECT) DACEN (DAC ENABLE) POWER-DOWN MODE OUTPUT STATE 0 0 Standby High-Z 0 1 Wake-Up Last state prior to standby mode

1 X Shutdown High-Z

X = Don’t Care FIGURE 3: AS5181 with External Reference APPLICATIONS INFORMATION Static and Dynamic Performance Defi nitions Integral Nonlinearity Integral nonlinearity (INL) (Figure 5a) is the deviation of the values on an actual transfer function from either a best- straight-line fi t (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullifi ed. For a DAC, the deviations are measured every single step. Differential Nonlinearity Differential nonlinearity (DNL) (Figure 5b) is the differ- ence between an actual step height and the ideal value of 1LSB. A DNL error speci fi cation of less than 1LSB guarantees no missing codes and a monotonic transfer function. Offset Error Offset error (Figure 5c) is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero. This error affects all codes by the same amount and can usually be compensated by trimming. Gain Error Gain error (Figure 5d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Settling Time Settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the converter’s specifi ed accuracy.

Rev. 0.4 01/10 Micross Components reserves the right to change products or specifi cations without notice. Digital Feedthrough Digital feedthrough is the noise generated on a DAC’s output when any digital input transitions. Proper board layout and grounding will signi fi cantly reduce this noise, but there will always be some feedthrough caused by the DAC itself. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal’s fi rst four harmonics to the fundamental itself. This is expressed as: where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component. Differential to Single-Ended Conversion A low-distortion, high-input bandwidth ampli fi er may be used to generate a voltage from the array current output of the AS5181. The differential voltage across OUTP and OUTN is converted into a single-ended voltage by designing an appropriate operational amplifi er confi guration (Figure 6). I/Q Reconstruction in a QAM Application The low-distortion performance of two AS5181s supports analog reconstruction of in-phase (I) and quadrature (Q) carrier components typically used in quadrature amplitude modulation (QAM) architectures where two separate buses carry the I and Q data. A QAM signal is both amplitude (AM) and phase modulated, created by summing two independently modulated carriers of identical frequency but different phase (90° phase difference). In a typical QAM application (Figure 7), the modulation occurs in the digital domain, and two DACs such as the AS5181 may be used to reconstruct the analog I and Q components. The I/Q reconstruction system is completed by a quadrature modulator that combines the reconstructed components with in-phase and quadrature carrier frequencies and then sums both outputs to provide the QAM signal. FIGURE 4: TIMING DIAGRAM

Rev. 0.4 01/10 Micross Components reserves the right to change products or specifi cations without notice. Using the AS5181 for Arbitrary Waveform Generation Designing a traditional arbitrary waveform generator (AWG) requires fi ve major functional blocks (Figure 8a): clock generator, counter, waveform memory, DAC for wave- form reconstruction, and output fi lter. The waveform memory contains the sequentially stored digital replica of the desired analog waveforms. This memory shares a common clock with the DAC. For each clock cycle, a counter adds one count to the address for the waveform memory. The memory then loads the next value to the DAC, which generates an analog output voltage corresponding to that data value. A DAC output fi lter can either be a simple or complex lowpass fi lter, depending on the AWG requirements for waveform function and frequen- cies. The main limitations of the AWG’s fl exibility are DAC resolution and dynamic performance, memory length, clock frequency, and the fi lter characteristics. Although the AS5181 offer high-frequency operation and excellent dynamics, they are suitable for relaxed requirements in resolution (10-bit AWGs). To increase an AWG’s high- frequency accuracy, temperature stability, wide-band tuning, and past phase-continuous frequency switching, the user may approach a direct digital synthesis (DDS) AWG (Figure 8b). This DDS loop supports standard waveforms that are repetitive, such as sine, square, TTL, and triangular waveforms. DDS allows for precise control of the data-stream input to the DAC. Data for one complete output waveform cycle is sequentially stored in a RAM. As the RAM addresses are changing, the DAC converts the incoming data bits into a corresponding voltage waveform. The resulting output signal frequency is proportional to the frequency rate at which the RAM addresses are changed. FIGURES 5 A thru D

Rev. 0.4 01/10 Micross Components reserves the right to change products or specifi cations without notice. Grounding and Power-Supply Decoupling Grounding and power-supply decoupling strongly infl uence the AS5181’s performance. Unwanted digital cross- talk may couple through the input, reference, power-supply, and ground connections, which may affect dynamic specifi cations like SNR or SFDR. In addition, electromagnetic interference (EMI) can either couple into or be generated by the AS5181. Therefore, grounding and power-supply decoupling guidelines for high-speed, high-frequency applications should be closely followed. First, a multilayer PC board with separate ground and power-supply planes is recommended. High-speed signals should be run on controlled impedance lines directly above the ground plane. Since the AS5181 has separate analog and digital ground buses (AGND and DGND, respectively), the PC board should also have separate analog and digital ground sections with only one point connecting the two. Digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. The device has two power-supply inputs: analog V DD (A VDD) and digital V DD (DV DD). Each A VDD input should be decoupled with parallel 10 μF and 0.1 μF ceramic-chip capacitors. These capacitors should be as close to the pin as possible, and their opposite ends should be as close as possible to the ground plane. The DV DD pins should also have separate 10μF and 0.1μF capacitors adjacent to their respec- tive pins. Try to minimize analog load capacitance for proper operation. For best performance, bypass with low-ESR 0.1μF capacitors to A V DD. The power-supply voltages should also be decoupled with large tantalum or electrolytic capacitors at the point they enter the PC board. Ferrite beads with additional decoupling capaci- tors forming a pi network can also improve performance. FIGURES 8A and 8B

Rev. 0.4 01/10 Micross Components reserves the right to change products or specifi cations without notice. 24-Pin Flat Pack (Package Designator F) MECHANICAL DEFINITIONS* *All measurements are in inches.

Rev. 0.4 01/10 Micross Components reserves the right to change products or specifi cations without notice. *AVAILABLE PROCESSES XT = Extended Temperature Range -55 oC to +125oC IT = Industrial Temperature Range -40 oC to +85oC MIL = Military Processing -55°C to +125°C SPACE = Space Processing -55 oC to +125oC

ORDERING INFORMATION

Temp. AS5181 F -* AS5181 F -* AS5181 F -* EXAMPLE: AS5181F-MIL