AS3722

AS3722 AMSOSRAM | Alldatasheet

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Technical content

[v1-01] 2015-Sep-07 Document Feedback AS3722 Multi-Phase DCDC Controller PMIC The AS3722 is a compact System PMU supporting up to 20 high current rails. The device offers advanced power management functions. All necessary ICs and peripherals in a battery powered mobile device are supplied by the AS3722. It features 4 DCDC buck converters as well as 11 low noise LDOs. The different regulated supply voltages are programmable via the serial control interface. 3-4MHz operation with 0.47uH coils is reducing cost and PCB space. AS3722 further features 3 DCDC buck controller which are ideal to support processor currents ranging from 5A up to 32A depending on the used power stages. The multi-phase topology operating on 3MHz ensures fast load transient responses and reduces the footpr int for external components. The single supply voltage may vary from 2.7V to 5.5V. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of AS3722, Multi-Phase DCDC Controller PMIC are listed below: Figure 1: Added Value of Using AS3722 Benefits Features

• Compact design due to small coils for IO and memory voltage generation
• 4 DCDC step down regulators (3-4MHz)
• Output (0.6V-3.35V; 1x5A, 1x2A, 2x1.5A)
• High current generation with external power stages to minimize PMIC power dissipation
• 3 DCDC step down controller
• DVM (0.6V-1.5V; 1x6A, 1x12A, 1x24A)
• Multiple independent voltage rails for general purpose IO supplies
• 11 universal LDOs
• 9x universal IO range(0.8-3.3V; 0.3A)
• 1x low output range (0.6-1.5V; 0.3A)
• 1x extended input range (0.8-1.2V; 0.3A)
• Ultra low-power oscillator and no external caps needed
• RTC
• 1μA total power consumption
• Programmable alarm
• Auto wake-up, repeating alarms
• 32kHz output to peripherals General Description

Document Feedback [v1-01] 2015-Sep-07 AS3722 − General Description

Applications

The device is suitable for:

• Mobile Phones
• Tablet PCs
• NetBooks
• Portable Media Players
• Portable Navigat ion Devices
• Mobile Internet Devices
• Safe supervision in HW which works also without a processor
• Supervisor with interrupt generation and selectable warning levels
• Automatic battery monitoring
• Automatic temperature monitoring
• Automatic over-current monitoring
• Power supply supervision for DCDC
• Flexible multi-purpose IOs for general control tasks
• General Purpose IOs
• A D C i n p u t
• W a k e - u p / s t a n d - b y i n p u t
• PWM input/output
• Low battery and power good status
• Enables the processor to check the actual system state in detail • ADC with internal and external sources
• Flexible and fast adaptation to different processors/applications
• OTP programmable Boot and Power-down sequence
• Power saving control according to the processor needs
• Stand-by function with programmable sequence and voltages
• Self-contained start-up and control for single and multi-cell battery applications. Safety shutdown feature
• Control Interface
• I2C/SPI control lines with watchdog
• ONKEY with 4/8s emergency shut-down
• P O R w i t h R E S E T I / O
• 5V pre-regulator enable
• Dedicated packages for specific applications. Optimization for PCB cost or size
• Package
• 124-pin CTBGA (8x8mm), 0.5mm pitch
• 108-pin WL-CSP (4.8x3.6mm), 0.4mm pitch Benefits Features

[v1-01] 2015-Sep-07 Document Feedback AS3722 − General Description Block Diagram The functional blocks of this device are shown below: Figure 2: AS3722 Block Diagram (CTBGA) Block Diagram: Shows the main function blocks of the AS3722 including basic external components. AS3722 VSUP_SD2 LX_SD2 FB_SD2 VSS_SD2 1uH 2.2uF 33uF VSUP_SD3 LX_SD3 FB_SD3 PVSS_SD3 1uH 22uF VSUP_SD4 LX_SD4 FB_SD4 VSS_SD4 1uH 10uF 2.2uF 2.2uF ONKEY XRES_IN CREF V2_5 1µF 220k GNDSENSE XRES_OUT ENABLE1 EN5V AC_OK LID XINT CTRL2_SD1 FB_SD1 (diff) TEMP1_SD1 CTRL3_SD0 FB_SD0 (diff) CTRL1_SD0 CTRL2_SD0 THERM LDO7 2.2uF 1.7V input LDO10 2.2uF 1.7V input LDO9 2.2uF VIN_LDO9_10 2.2uF 1.7V input LDO5 2.2uF 1.7V input LDO2 2.2uF VIN_LDO2_5_7 2.2uF 1.7V input LDO4 2.2uF VIN_LDO3_4 1.7V input LDO6 2.2uF 1.7V input LDO1 2.2uF VIN_LDO1_6 2.2uF 1.7V input LDO0 2.2uF VIN_LDO0 2.2uF 1.15V input VSUP_SD5 LX_SD5 FB_SD5 VSS_SD5 1uH 10uF 2.2uF CTRL1_SD1 CTRL7_SD0 TEMP1_SD0 CTRL5_SD0 CTRL6_SD0 CTRL4_SD0 OC_PG VBAT CTRL8_SD0 TEMP2_SD0 TEMP3_SD0 TEMP4_SD0 CTRL2_SD6 FB_SD6 (diff) TEMP1/2_SD6 CTRL1_SD6 LDO11 2.2uF VIN_LDO11 2.2uF 1.7V input bypass RBIAS max. 4 sub dies (8 phases) max. 1 sub die (2 phases) max. 2 sub die (2 phases) VSSA PWM control (SD0 & SD6) PWM_CLK1 PWM_DAT1 VSUP_ANA PWM_CLK2_ADC1 PWM_DAT2_ADC2 0v40 100nF Boot ROM (OTP) Interrupt Overtemp Protection Watchdog ADC General Purpose Voltage Monitor Reset Standby Control RTC Alarm XIN32 XOUT32 CLK32K VBACKUP Charger VBAT_BKUP VSUP_GPIO SPI/I2C GPIO Input: ADC, INT, wtdg, Stand-by, REGenable Output: VSUPlow, PWRGOOD, PWM, INT, OSC32K GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 VDD_GPIO_lv System Control References LDO7 PMOS_1 0.8-3.3V 300mA LDO10 PMOS_1 0.8-3.3V 300mA LDO9 PMOS_1 0.8-3.3V 300mA LDO5 PMOS_1 0.8-3.3V 300mA LDO2 PMOS_1 0.8-3.3V 300mA LDO4 PMOS_1 0.8-3.3V 150mA LDO6 PMOS_1 0.8-3.3V 300mA LDO1 PMOS_1 0.8-3.3V 300mA LDO0 NMOS_1 0.8-1.2V 300mA LDO11 PMOS_1 0.8-3.3V 300mA DCDC2 0.6V-3.3V 1.5-4A (5A) DCDC3 0.6V-3.3V 1.2-2A DCDC4 0.6V-3.3V 0.7-1.5A DCDC1 0.6V-1.5V DCDC0 0.6V-1.5V DCDC5 0.6V-3.3V 0.7-1.5A DCDC6 0.6V-1.5V SCL/SCLK SDA/SDI ENABLE3_SDO SCSB ENABLE2 LDO3 2.2uF VIN_LDO3_4 2.2uF LDO3 PMOS 0.6-1.5V 300mA 1.7V input lv_mode DCDC1/6 tracking LDO3 NMOS 0.6-1.0V 100mA VIN_LDO3_LV LDO3 SW 350mOhm VIN_LDO3_SW sw_mode 2.2uF

Document Feedback [v1-01] 2015-Sep-07 AS3722 − General Description Figure 3: AS3722 Block Diagram (WL-CSP) Block Diagram: Shows the main function blocks of the AS3722 in WL-CSP package. AS3722 (:/CSP) VSUP_SD2 LX_SD2 FB_SD2 VSS_SD2 1uH 2.2uF 33uF VSUP_SD3 LX_SD3 FB_SD3 PVSS_SD3 1uH 22uF VSUP_SD4 LX_SD4 FB_SD4 VSS_SD4 1uH 10uF 2.2uF 2.2uF ONKEY XRES_IN CREF V2_5 1μF 220k GNDSENSE XRES_OUT ENABLE1 EN5V AC_OK LID XINT CTRL2_SD1 FB_SD1 (diff) TEMP1_SD1 CTRL3_SD0 FB_SD0 (diff) CTRL1_SD0 CTRL2_SD0 THERM LDO7 2.2uF 1.7V input LDO10 2.2uF 1.7V input LDO9 2.2uF VIN_LDO9_10 2.2uF 1.7V input LDO5 2.2uF 1.7V input LDO2 2.2uF VIN_LDO2_5_7 2.2uF 1.7V input LDO4 2.2uF VIN_LDO3_4 1.7V input LDO6 2.2uF 1.7V input LDO1 2.2uF VIN_LDO1_6 2.2uF 1.7V input LDO0 2.2uF VIN_LDO0 2.2uF 1.15V input VSUP_SD5 LX_SD5 FB_SD5 VSS_SD5 1uH 10uF 2.2uF CTRL1_SD1 CTRL7_SD0 TEMP1_SD0 CTRL5_SD0 CTRL6_SD0 CTRL4_SD0 OC_PG VBAT CTRL8_SD0 TEMP2_SD0 TEMP3_SD0 TEMP4_SD0 CTRL2_SD6 FB_SD6 (diff) TEMP1/2_SD6 CTRL1_SD6 LDO11 2.2uF VIN_LDO11 2.2uF 1.7V input bypass RBIAS max. 4 sub dies (8 phases) max. 1 sub die (2 phases) max. 2 sub die (2 phases) VSSA PWM control (SD0 & SD6) PWM_CLK1 PWM_DAT1 VSUP_ANA PWM_CLK2_ADC1 PWM_DAT2_ADC2 0v40 100nF Boot ROM (OTP) Interrupt Overtemp Protection Watchdog ADC General Purpose Voltage Monitor Reset Standby Control RTC Alarm XIN32 XOUT32 CLK32K VBACKUP Charger VBAT_BKUP VSUP_GPIO SPI/I2C GPIO Input: ADC, INT, wtdg, Stand-by, REGenable Output: VSUPlow, PWRGOOD, PWM, INT, OSC32K GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 VDD_GPIO_lv System Control References LDO7 PMOS_1 0.8-3.3V 300mA LDO10 PMOS_! 0.8-3.3V 300mA LDO9 PMOS_1 0.8-3.3V 300mA LDO5 PMOS_1 0.8-3.3V 300mA LDO2 PMOS_1 0.8-3.3V 300mA LDO4 PMOS_1 0.8-3.3V 150mA LDO6 PMOS_1 0.8-3.3V 300mA LDO1 PMOS_1 0.8-3.3V 300mA LDO0 NMOS_1 0.8-1.2V 300mA LDO11 PMOS_1 0.8-3.3V 300mA DCDC2 0.6V-3.3V 1.5-4A (5A) DCDC3 0.6V-3.3V 1.2-2A DCDC4 0.6V-3.3V 0.7-1.5A DCDC1 0.6V-1.5V DCDC0 0.6V-1.5V DCDC5 0.6V-3.3V 0.7-1.5A DCDC6 0.6V-1.5V SCL/SCLK SDA/SDI ENABLE3_SDO SCSB ENABLE2 LDO3 2.2uF VIN_LDO3_4 2.2uF LDO3 PMOS 0.6-1.5V 300mA 1.7V input lv_mode DCDC1/6 tracking LDO3 NMOS 0.6-1.0V 100mA VIN_LDO3_LV LDO3 SW 350mOhm VIN_LDO3_SW sw_mode 2.2uF

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Pin Assignment Figure 4: Pin Assignment (CTBGA124) Pin Assignment: Shows the top view pin assignment of the AS3722 in the CTBGA124. 1 2 3456 789 1 0 1 1 1 2 1 3 1 4 A VSSA LDO4 VIN_ LDO3_ VIN_ LDO3_ SW LDO9 VIN_ LDO9_ LDO6 VIN_ LDO1_ LDO2 LDO5 LDO7 VIN_ LDO2_ 5_7 LDO0 VSSA B VIN_ LDO11 GPIO4 GPIO6 LDO11 VIN_ LDO3_ LV LDO3 LDO10 LDO1 ONKEY PWM_ CLK2_ ADC1 PWM_ DAT2_ ADC2 VIN_ LDO0 C XINT GPIO5 CTRL1 _SD6 CTRL2 _SD6 D CLK 32K GPIO7 GPIO2 GPIO0 LID THERM PWM_ CLK1 PWM_ DAT1 CTRL1 _SD1 CTRL2 _SD1 E OC_PG ENABLE 3_SDO GPIO3 ENABL CTRL1 _SD0 CTRL2 _SD0 F VSS_ GPIO VDD_ GPIO_ LV SDA_ SDI VSSA ENABL FB_ SD6_P CTRL3 _SD0 CTRL4 _SD0 G XIN32K XOUT 32K SCL_ SCLK GPIO1 FB_ SD1_P FB_ SD6_N CTRL5 _SD0 CTRL6 _SD0 H VSUP_ ANA V2_5 VBAT_ BKUP SCSB FB_ SD1_N FB_ SD0_P CTRL7 _SD0 CTRL8 _SD0 J FB_SD

5 RBIAS CREF VSSA XRES_

FB_ SD0_N TEMP2 _SD0 TEMP 1_SD0 K FB_SD FB_SD GND SENSE TEMP4 _SD0 TEMP3 _SD0 TEMP _SD1 L VSUP_ SD3 VSUP_ SD3 XRES_ OUT EN5V VBAT AC_OK VSUP_ GPIO FB_SD TEMP2 _SD6 TEMP 1_SD6 M LX_ SD3 LX_ SD3 VSS_ SD4 VSS_ SD4 N LX_ SD3 VSS_ SD3 VSS_ SD2 LX_ SD2 VSUP_ SD2 LX_ SD2 VSS_ SD2 VSS_ SD5 LX_ SD5 VSUP_ SD5 VSUP_ SD4 LX_ SD4 P VSSA VSS_ SD3 VSS_ SD3 VSS_ SD2 LX_ SD2 VSUP_ SD2 LX_ SD2 VSS_ SD2 VSS_ SD5 LX_ SD5 VSUP_ SD5 VSUP_ SD4 LX_ SD4 VSSA Pin Assignment

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Pin Assignment Figure 5: Ball Assignment (WL-CSP108) Ball Assignment: Shows the top view pin assignment of the AS3722 in the WL-CSP108. 1 2 3 4 5 6 7 8 9 10 11 12 A PWM_ DAT2_ ADC1 ONKEY LDO7 LDO5 LDO6 LDO1 LDO9 LDO3 LDO4 GPIO0 GPIO5 XINT B PWM_ CLK2_ ADC1 THERM VIN_LDO VIN_LDO 2_5_7 LDO2 VIN_LDO 1_6 VIN_LDO 9_10 VIN_LDO 3_SW VIN_LDO

11 GPIO4 CLK32K GPIO7

C CTRL1_ SD6 ENABLE

1 XRES_IN LDO0 PWM_

PWM_ CLK1 VIN_LDO 3_LV LDO11 GPIO3 VSUP_ GPIO OC_PG SCL_ SCLK D CTRL2_ SD6 CTRL1_ SD1 ENABLE2 AC_OK CTRL2_ SD1 LDO10 VIN_LDO 3_4 GPIO2 VBAT VDD_ GPIO_LV SDA_SDI V2_5 E CTRL5_ SD0 CTRL2_ SD0 CTRL1_ SD0 CTRL3_ SD0 CTRL4_ SD0 VSSA GPIO1 EN5V XOUT 32K XIN32K CREF VSUP_ ANA F TEMP2_ SD0 CTRL6_ SD0 VSUP_ GPIO TEMP1_ SD0 TEMP3_ SD0 FB_SD0_ P GPIO6 XRES_ OUT VSSA FB_SD5 RBIAS FB_SD2 G FB_SD6 FB_SD6 TEMP_ SD1 FB_SD1_ P FB_SD1 _N VSSA VSSA LX_SD2 LX_SD2 FB_SD3 VSS_ SD3 VSS_ SD3 H TEMP1_ SD6 FB_SD4 FB_SD0_ N VSUP_ SD4_5 LX_SD5 VSS_ SD5 VSS_ SD2 VSUP_ SD2 LX_SD2 VSS_ SD2 LX_SD3 VSUP_ SD3 J TEMP2_ SD6 VSS_ SD4 LX_SD4 VSUP_ SD4_5 LX_SD5 VSS_ SD5 VSS_ SD2 VSUP_ SD2 LX_SD2 VSS_ SD2 LX_SD3 VSUP_ SD3

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Pin Assignment Pin Description Figure 6: Pin Description Pin Number Pin Name I/O Description Maximum Voltage If Not Used CTBGA WL-CSP F4 D11 SDA_SDI DI SPI digital input in SPI mode; Data IO in I2C mode. VSUP Open G4 C12 SCL_SCLK DI SPI clock input in SPI mode; SCK input in I2C mode. VSUP Open E2 ENABLE3_SDO DIO SPI digital output in SPI mode VSUP Define level H6 SCSB DI SPI chip-select in SPI mode; connect to VSS in I2C mode. VSUP VSS B14 B3 VIN_LDO0 S Supply pad for LDOs 5.5V Mandatory A8 B6 VIN_LDO1_6 S Supply pad for LDOs 5.5V Mandatory A6 B7 VIN_LDO9_10 S Supply pad for LDOs 5.5V Mandatory A3 D7 VIN_LDO3_4 S Supply pad for LDOs 5.5V Mandatory A12 B4 VIN_LDO2_5_7 S Supply pad for LDOs 5.5V Mandatory A4 B8 VIN_LDO3_SW S Supply pad for LDO3 switch function 3.6V Mandatory B1 B9 VIN_LDO11 S Supply pad for LDOs 5.5V Mandatory A13 C4 LDO0 AO Output voltage of LDO - NMOS_0.6 VIN_LDO0 Open B9 A6 LDO1 AO Output voltage of LDO - PMOS_1 VIN_LDO1_

6 Open

A9 B5 LDO2 AO Output voltage of LDO - PMOS_1 VIN_LDO2_ 5_7 Open B6 C7 VIN_LDO3_LV S Supply pad for LDO3 NMOS function 3.6V Open A2 A9 LDO4 AO Output voltage of LDO - PMOS_0.6 VIN_LDO3_

4 Open

A10 A4 LDO5 AO Output voltage of LDO - PMOS_0.6 VIN_LDO2_ 5_7 Open A7 A5 LDO6 AO Output voltage of LDO - PMOS_0.6 VIN_LDO1_ A11 A3 LDO7 AO Output voltage of LDO - PMOS_0.6 VIN_LDO2_ 5_7 Open

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Pin Assignment B7 A8 LDO3 AO Output voltage of LDO - PMOS_1 VIN_LDO8 Open A5 A7 LDO9 AO Output voltage of LDO - PMOS_1 VIN_LDO9_

10 Open

B8 D6 LDO10 AO Output voltage of LDO - PMOS_1 VIN_LDO9_ B5 C8 LDO11 AO Output voltage of LDO - PMOS_1 VIN_LDO11 Open B10 A2 ONKEY DI Input pin to startup (no pullup/pull down) 5.5V Define level F8 C2 ENABLE1 DI Input pin for transition into and out of deep-sleep mode VSUP Define level E11 D3 ENABLE2 DI Input pin for control of DCDC0 VSUP Define level D8 B2 THERM DI Input pin for thermal event 5.5V Define level J8 C3 XRES_IN DI Input pin for reset during active and stand-by state VSUP Define level L5 F8 XRES_OUT DO Push pull to VDD_GPIO_lv VSUP Open L8 D4 AC_OK DI Pin to indicate, that the AC adaptor is present 5.5V Define level D7 LID DI Input pin to indicates LID status of Device 5.5V Define level C1 A12 XINT DO Push-Pull or open drain output for interrupt detection VSUP Open L9 C10, F3 VSUP_GPIO S Supply pin for GPIOs (connect to other VSUP pins) 5.5V Mandatory F2 D10 VDD_GPIO_lv S Supply pin for GPIOs (connect to typical 1.8V or 3.3) VSUP Mandatory F1 VSS_GPIO AIO Analog GND input - Mandatory D6 A10 GPIO0 DIO General purpose input/output pin VSUP Open G6 E7 GPIO1 DIO General purpose input/output pin VSUP Open Pin Number Pin Name I/O Description Maximum Voltage If Not Used CTBGA WL-CSP

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Pin Assignment D5 D8 GPIO2 DIO General purpose input/output pin VSUP Open E4 C9 GPIO3 DIO General purpose input/output pin VSUP Open B3 B10 GPIO4 DIO General purpose input/output pin VSUP Open C2 A11 GPIO5 DIO General purpose input/output pin VSUP Open B4 F7 GPIO6 DIO General purpose input/output pin VSUP Open D2 B12 GPIO7 DIO General purpose input/output pin VSUP Open H2 D12 V2_5 AO Output voltage of low power LDO V2_5 3.6V Mandatory J4 E11 CREF AIO Bypass capacitor for the internal voltage reference; connect 100nF V2_5 Mandatory J2 F11 RBIAS AIO External resistor; always connect a resistor of 220kΩ (±1%) to VSSA V2_5 Mandatory H4 VBAT_BKUP AIO Backup battery input 3.6V Open A1 G7 VSSA AIO Analog GND input - Mandatory A14 G6 VSSA AIO Analog GND input - Mandatory J7 E6 VSSA AIO Analog GND input - Mandatory P1 F9 VSSA AIO Analog GND input - Mandatory P14 VSSA AIO Analog GND input - Mandatory F7 VSSA AIO Analog GND input - Mandatory D1 B11 CLK32K DO 32kHz clk output push/pull to VDD_GPIO_lv VSUP Open G1 E10 XIN32K AIO Connect to 32kHz crystal oscillator V2_5 Open G2 E9 XOUT32K AIO Connect to 32kHz crystal oscillator V2_5 Open K4 GNDSENSE AIO Analog sense GND input (connect to VSSA on WL-CSP) -M a n d a t o r y Pin Number Pin Name I/O Description Maximum Voltage If Not Used CTBGA WL-CSP

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Pin Assignment E1 C11 OC_PG DO Digital Output open drain to indicate over-current/ power_good VSUP Open H1 E12 VSUP_ANA S System supply voltage input (connect to other VSUP pins) 5.5V Mandatory N6 H8 VSUP_SD2 S System supply voltage input of Stepdown2 (connect to other VSUP pins) 5.5V Mandatory P6 J8 VSUP_SD2 S System supply voltage input of Stepdown2 (connect to other VSUP pins) 5.5V Mandatory N5 G8 LX_SD2 AIO LX node of Stepdown2 VSUP Open N7 G9 LX_SD2 AIO LX node of Stepdown2 VSUP Open P5 H9 LX_SD2 AIO LX node of Stepdown2 VSUP Open P7 J9 LX_SD2 AIO LX node of Stepdown2 VSUP Open N4 H7 VSS_SD2 AIO Power GND pin of Stepdown2 -M a n d a t o r y N8 J7 VSS_SD2 AIO Power GND pin of Stepdown2 -M a n d a t o r y P4 H10 VSS_SD2 AIO Power GND pin of Stepdown2 -M a n d a t o r y P8 J10 VSS_SD2 AIO Power GND pin of Stepdown2 -M a n d a t o r y K1 F12 FB_SD2 AIO Analog Feedback pin of SD2 3.6V Open L1 H12 VSUP_SD3 S System supply voltage input of Stepdown3 (connect to other VSUP pins) 5.5V Mandatory L2 J12 VSUP_SD3 S System supply voltage input of Stepdown3 (connect to other VSUP pins) 5.5V Mandatory M1 H11 LX_SD3 AIO LX node of Stepdown3 VSUP Open M2 J11 LX_SD3 AIO LX node of Stepdown3 VSUP Open N1 LX_SD3 AIO LX node of Stepdown3 VSUP Open Pin Number Pin Name I/O Description Maximum Voltage If Not Used CTBGA WL-CSP

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Pin Assignment N3 G11 VSS_SD3 AIO Power GND pin of Stepdown3 -M a n d a t o r y P2 G12 VSS_SD3 AIO Power GND pin of Stepdown3 -M a n d a t o r y P3 VSS_SD3 AIO Power GND pin of Stepdown3 -M a n d a t o r y K2 G10 FB_SD3 AIO Analog Feedback pin of SD3 3.6V Open N12 H4 VSUP_SD4 S System supply voltage input of Stepdown4 (connect to other VSUP pins) 5.5V Mandatory P12 J4 VSUP_SD4 S System supply voltage input of Stepdown4 (connect to other VSUP pins) 5.5V Mandatory L10 H2 FB_SD4 AIO Analog Feedback pin of SD4 3.6V Open N14 J3 LX_SD4 AIO LX node of Stepdown4 VSUP Open P13 LX_SD4 AIO LX node of Stepdown4 VSUP Open M13 J2 VSS_SD4 AIO Power GND pin of Stepdown4 -M a n d a t o r y M14 VSS_SD4 AIO Power GND pin of Stepdown4 -M a n d a t o r y N11 H4 VSUP_SD5 S System supply voltage input of Stepdown5 (connect to other VSUP pins) 5.5V Mandatory P11 J4 VSUP_SD5 S System supply voltage input of Stepdown5 (connect to other VSUP pins) 5.5V Mandatory J1 F10 FB_SD5 AIO Analog Feedback pin of SD5 3.6V Open N10 H5 LX_SD5 AIO LX node of Stepdown5 VSUP Open P10 J5 LX_SD5 AIO LX node of Stepdown5 VSUP Open P9 H6 VSS_SD5 AIO Power GND pin of Stepdown5 -M a n d a t o r y N9 J6 VSS_SD5 AIO Power GND pin of Stepdown5 -M a n d a t o r y H11 F6 FB_SD0_P AIO Positive Feedback of SD0 3.6V Open Pin Number Pin Name I/O Description Maximum Voltage If Not Used CTBGA WL-CSP

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Pin Assignment J11 H3 FB_SD0_N AIO Negative Feedback of SD0 3.6V Open E13 E3 CTRL1_SD0 AIO Bidirectional control pin of SD0, phase 1 VSUP Open E14 E2 CTRL2_SD0 AIO Bidirectional control pin of SD0, phase 2 VSUP Open F13 E4 CTRL3_SD0 AIO Bidirectional control pin of SD0, phase 3 VSUP Open F14 E5 CTRL4_SD0 AIO Bidirectional control pin of SD0, phase 4 VSUP Open G13 E1 CTRL5_SD0 AIO Bidirectional control pin of SD0, phase 5 VSUP Open G14 F2 CTRL6_SD0 AIO Bidirectional control pin of SD0, phase 6 VSUP Open H13 CTRL7_SD0 AIO Bidirectional control pin of SD0, phase 7 VSUP Open H14 CTRL8_SD0 AIO Bidirectional control pin of SD0, phase 8 VSUP Open J14 F4 TEMP1_SD0 AIO Temperature control pin of subdie1 for SD0 VSUP Open J13 F1 TEMP2_SD0 AIO Temperature control pin of subdie2 for SD0 VSUP Open K13 F5 TEMP3_SD0 AIO Temperature control pin of subdie3 for SD0 VSUP Open K11 TEMP4_SD0 AIO Temperature control pin of subdie4 for SD0 VSUP Open G9 G4 FB_SD1_P AIO Positive Feedback of SD1 3.6V Open H9 G5 FB_SD1_N AIO Negative Feedback of SD1 3.6V Open D 1 3D 2C T R L 1 _ S D 1 A I O Bidirectional control pin of SD1, phase 1 VSUP Open D 1 4D 5C T R L 2 _ S D 1 A I O Bidirectional control pin of SD1, phase 2 VSUP Open Pin Number Pin Name I/O Description Maximum Voltage If Not Used CTBGA WL-CSP

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Pin Assignment Pin Description: This table shows the pin description for the CTBGA as well as the WL-CSP package including information of the I/O type, protection and handling if the function block is not used. K14 G3 TEMP_SD1 AIO Temperature control pin of subdie1 for SD1 VSUP Open F11 G2 FB_SD6_P AIO Positive Feedback of SD6 3.6V Open G11 G1 FB_SD6_N AIO Negative Feedback of SD6 3.6V Open C13 C1 CTRL1_SD6 AIO Bidirectional control pin of SD6, phase 1 VSUP Open C14 D1 CTRL2_SD6 AIO Bidirectional control pin of SD6, phase 2 VSUP Open L14 H1 TEMP1_SD6 AIO Temperature control pin of subdie1 for SD6 VSUP Open L13 J1 TEMP2_SD6 AIO Temperature control pin of subdie2 for SD6 VSUP Open D9 C6 PWM_CLK1 DI PWM input pin for DVM control of SD0 VSUP Define level D10 C5 PWM_DAT1 DI PWM input pin for DVM control of SD0 VSUP Define level B11 B1 PWM_CLK2_ ADC1 DI PWM input pin for DVM control of SD6 or ADC input pin VSUP Define level B12 A1 PWM_DAT2_ ADC2 DI PWM input pin for DVM control of SD6 or ADC input pin VSUP Define level L7 D9 VBAT S High Voltage Supply pin for RTC, and voltage detection 30V Connect to VSUP L6 E8 EN5V DO Enable pin for external 5V HV stepdown to supply VSUP rails V2_5 Open Pin Number Pin Name I/O Description Maximum Voltage If Not Used CTBGA WL-CSP

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Absolute Maximum Ratings Stresses beyond th ose listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics is not implied. Exposu re to absolute maximum rating conditions for periods may affect device reliability. Figure 7: Absolute Maximum Ratings Symbol Parameter Min Max Units Comments Electrical Parameters Supply Voltage to Ground 30V pins -0.5 32 V Applicable for pin VBAT Supply Voltage to Ground 5V pins -0.5 7.0 V Applicable for pins VSUP_SDx, VSUP_ANA, ONKEY, VSUP_GPIO, VIN_LDOx, LDO6 (switch mode), THERM, AC_OK, LID 5V pins with protection to VSUP -0.5 VSUP_x V Applicable for pins SCL_SCLK, SDA_SDI, SCSB, SDO, XINT, VDD_GPIO_LV, GPIOx, CLK32K, OC_PG, LX_SDx, CTRLx, XRES_IN/OUT, ENABLEx, PWMx Supply Voltage to Ground 3V pins -0.5 5.0 V Applicable for pins V2_5, VBAT_BKUP , VIN_LDO3_LV/SW 3V pins with protection to VIN_LDOx -0.5 5.0 or VIN_LDOx VA p p l i c a b l e f o r p i n s L D O x 3V pins with protection to VSUP -0.5 5.0 or VSUP_x V Applicable for pins TEMPx, FB_SDx 3V pins with protection to V2_5 -0.5 V2_5 V Applicable for pins CREF, RBIAS, XIN32K, XOUT32K, EN5V Voltage Difference between Ground Terminals -0.3 0.3 V Applicable for pins VSSx, VSSA, GNDSENSE I SCR Input Current (latch-up immunity) -100 100 mA Norm: JEDEC JESD78 Absolute Maximum Ratings

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Absolute Maximum Ratings Note(s) and/or Footnote(s): 1. Depending on actual PCB layout and PCB used 2. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensiti vity Classification for Nonhermetic Solid State Surface Mount Devices” Continuous Power Dissipation (TA = 70°C) PT Continuous power dissipation 1.4 W PT (1) for CTBGA124 package (RTHJA ~ 38K/W) PT Continuous power dissipation 1.3 W PT (1) for WL-CSP108 package (RTHJA ~ 40K/W) Electrostatic Discharge ESDHBM Electrostatic Discharge HBM ±1.5 kV Norm: JEDEC JESD22-A114F Temperature Ranges and Storage Conditions TA Operating Temperature -40 85 °C TJ Junction Temperature 125 °C TSTRG Storage Temperature Range -55 125 °C TBODY Package Body Temperature 260 °C Norm IPC/JEDEC J-STD-020(2) RHNC Relative Humidity non-condensing 58 5 % MSL Moisture Sensitivity Level 3 for CTBGA, represents a max. floor life time of 168h for WL-CSP , represents an unlimited max. floor life time Bump Temperature (CTBGA Soldering) T PEAK Soldering Profile 235 245 °C Peak Temperature tWELL 30 45 s Well Time above 217°C Symbol Parameter Min Max Units Comments

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Electrical Characteristics All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 8:

Electrical Characteristics

Symbol Parameter Conditions Min Typ Max Unit VBAT Battery Voltage 2.5 3.6 30 V VSUPx Supply Voltage 2.5 3.6 5.5 V VBAT_BKUP Backup-Battery Voltage 2.5 3 3.6 V VDD_GPIO_lv Alternative GPIO Supply Voltage 1.7 1.8 3.6 V VINLDO0 Supply Voltage for LDO0 1.15 3.6 5.5 V VINLDO1-11 Supply Voltage for LDO1 to LDO11 1.7 3.6 5.5 V VINLDO3_LV Supply Voltage for LDO3 NMOS 1.2 3.6V V VINLDO3_SW Supply Voltage for LDO3 switch 0.6 1.5V V V2_5 Voltage on Pin V2_5 2.4 2.5 2.6 V Iquiescent Quiescent current @ VSUPx = 3.8V, no regulator enabled only V2_5 on, digital part, bias and references running 310 μA I low_power1 Low Power current as above but, low_power=1 265 μA Ilow_power2 Low Power current As above, but low_power=1; clk_div=1 160 μA Ipower_off Power-Off current All regulators off V2_5 on 10 μA

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Electrical Characteristics Digital Input Pin Characteristics VIL Low Level input voltage ONKEY, XRES_IN –0.3 0.4 V VIH High Level input XRES_IN, ENABLEx 1.4 VVSUP_ GPIO V VIH_noprot High Level input ONKEY, THERM, AC_OK, LID 1.4 5.5V V Digital Output Pin Characteristics VOL XRES_OUT Low-Level Output Voltage XRES_OUT; XINT, OC_PG at 2.0mA 0.2 x V VDD_G PIO_lv V VOH XRES_OUT High-Level Output Voltage XRES_OUT; XINT (if on push pull mode), OC_PG, SDO at -1.0mA 0.8 x V VDD_GPIO_ lv V VOL_EN5V Low-Level Output Voltage EN_5V at 0.1mA 0.2 x VV2_5 V VOH_EN5V High-Level Output Voltage EN_5V at -0.1mA 0.8 x VV2_5 V ILEAKAGE Leakage current high impedance 10 μA RPULLUP Internal pull-up to VDD_GPIO_lv XINT=2V, VDD_GPIO_LV=3V (XINT in open-drain mode) 33 91 k Ω Symbol Parameter Conditions Min Typ Max Unit

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Electrical Characteristics unless otherwise specified. GPIO Pin Characteristics VIL Low level input voltage digital input -0.3 0.4 V VIH High level input voltage digital input 1.4 VVDD_G PIO_lv or VVSUP_ GPIO V VOL Low level output voltage GPIO, IOL=+2mA; digital output 0.2 x VVDD_G PIO_lv or VVSUP_ GPIO V VOH High level output voltage GPIO, IOH=–1mA; digital push-pull output 0.8 xVVDD_GPIO _lv or VVSUP_GPIO VVDD_G PIO_lv or VVSUP_ GPIO V ILEAKAGE Leakage current high impedance 10 μA Rpull-up Pull-up resistance if enabled; VSUP_GPIO=3.6V 300 k Ω Rpull-down Pull-down resistance if enabled; VSUP_GPIO=3.6V 300 k Ω RNMOS NMOS resistance VSUP_GPIO>=3.3V 50 Ω Symbol Parameter Conditions Min Typ Max Unit

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Typical Operating Characteristics This page is intentionally left blank.Typical Operating Characteristics

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- Power Management Functions DCDC Step-Down Converter

Description

The step-down converter is a high efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS switches efficiency up to 95% can be achieved. The fast switching frequency allows using small inductors, without increasing the current ripple. The unique feedback and regulation circuit guarantees op timum load and line regulation over the whole output voltage range, up to an output current of 1.5A (SD4, SD5), 2A (SD3) and 5A for SD2, with an output capacitor of only 8-27μF. The implemented current limitation protects the DCDC and the coil during overload condition. Figure 9: Step Down DC/DC Converter Block Diagram DCDC Step Down Converter Block Diagram: Shows the internal structure of the DCDC bucks. Detailed Descriptions- Power Management Functions LOGIC Zero Comp 1.2/1.8/2.9A Ilimit 250/400/600mAImin sdx_low_noise clk Ref +8% Overvoltage Comp skip Ref -5% IsenseP IsenseN Ref=0.6Vskip PWM Comp Slope Compensation sdX_lv VSUP_SDx LX_SDx VSS_SDx FB_SDx softstart

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- Power Management Functions Mode Settings Low Ripple, Low Noise Operation Bit settings: sdX_low_noise =1 In this mode there is no minimu m coil current necessary before switching off the PMOS. As long as the load current is superior to the ripple current the device operates in continuous mode. Figure 10: DC/DC Buck Continuous Mode DC/DC Buck Continuous Mode: Shows the DC/DC switching waveforms of for SD5 at about 500mA. When the load current gets lower, the discontinuous mode is triggered. As result, the auto-z ero comparator stops the NMOS conduction to avoid load disc harger and the duty cycle is reduced down to tmin_on to keep the regulation loop stable. This results in a very low ri pple and noise, but decreased efficiency, at light loads, especially at low input to output voltage differences.

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- Power Management Functions It’s possible to switch between these two modes during operation. Power Save Operation (Automatically Controlled) As soon as the output voltage stays above the desired target value for a certain time, some internal blocks will be powered down leaving the output floating to lower the power consumption. Normal operation starts as soon as the output drops below the target value for a similar amount of time. To minimize the accuracy error some internal circuits are kept powered to assure a minimized output voltage ripple. Two addition guard bands, based on comparators, are set at ±5% of the target value to react quickly on large over/under-shoots by immediately turning on the output drivers without the normal ti me delays. This ensures a minimized ripple also in very extreme load conditions. Fast Regulation Mode This mode can be used to react faster on sudden load changes and thus minimize the over-/unde rshoot of the output voltage. This mode needs a bigger output capacitor to guarantee the stability of the regulator. The mode is enabled by setting sdX_fast =1. Selectable Frequency Operation Especially for very low load conditions, e.g. during a sleep mode of a processor, the switching frequency can be reduced to achieve a higher efficiency. The frequency for SD2, SD3, SD4 and SD5 can be set to 3 or 4MHz. This mode is selected by setting sdX_freq to the appropriate value. 100% PMOS ON Mode for Low Dropout Regulation For low input to output voltage difference the DCDC converter can use 100% duty cycle for the PMOS transistor, which is then in LDO mode. Step-Down Converter Configuration Modes The step down dc/dc converters have two configuration modes to deliver different output currents for the applications. The operating mode is selected by setting the bit sd3_slave , sd4_slave and sd5_slave (the default is set by the Boot-OTP). It’s not allowed to set sd3_slave and sd4_slave at the same time.

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- Power Management Functions DC/DC Buck Converter Parameter: Shows the key electrical parameter of the internal DC/DC buck converters SD4, SD5 1.8 A RPSW P-Switch ON resistance incl. bonds, substrate, etc SD2; VSUP_SDx=3.0V 78 100 mΩ SD3; VSUP_SDx=3.0V 156 200 mΩ SD4, SD5; VSUP_SDx=3.0V 225 300 mΩ RNSW N-Switch ON resistance incl. bonds, substrate, etc SD2; VSUP_SDx=3.0V 50 70 mΩ SD3; VSUP_SDx=3.0V 100 130 mΩ SD4, SD5; VSUP_SDx=3.0V 140 190 mΩ fSW Switching frequency sdX_frequ=1; fclk_int =4MHz 4M H z sdX_frequ=0; fclk_int =4MHz 3M H z ηeff Efficiency see figures below % IVDD Current consumption Operating current without load 60 μA RDIS discharge resistance SD2 off; Vout=1V 90 Ω SD3/4/5 off; Vout=1V 160 Ω Symbol Parameter Conditions Min Typ Max Unit

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- Power Management Functions DCDC Step-Down Controller The Step-Down controller SD1 and SD6 are dual phase controller using an external power-stage incorporating 2 phases to achieve higher output currents. The maximum output current when using the AS3729 power stage is 6A (peak) with having 3A (peak) per phase. When using the AS3729B power stage, the current can be up to 4A (peak) per phase. This allows the use of low profile coils without compromising on performance. Figure 23: SD1 DC/DC Buck Controller 8A Peak Block Diagram SD1 DC/DC Buck Controller: Shows basic connection of the SD1 controller to the external power stage (AS3729B) for 8Apeak output current. When using the AS3728 power stage a dual phase controller can support up to 8A (4A per phase). The AS3728 is a HV power stage being capable of operating from input voltage up to 14V for multi-cell designs. TEMP CTRL 1 CTRL 2 LX2 LX 1 PVSS PVSS 0.47uH 0. 47uH FB _SDx Vout (0 .6-1.5V@8A) DVM, 10mV steps 47uF VSUP 10 uF 47uF AS3729B SD controller TEMP_SDx CTRL 1_SDx CTRL 2_SDx FB_SDx VSUP 10 uF

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- Power Management Functions The Step-Down controller SD0 is a multi-phase controller which can use up to 4 power stages (8 phases) with a maximum output current of 20Arms. The output current is easily scalable by varying the number of phases and power-stages from 2.5Arms to 20Arms. Figure 26: SD0 DC/DC Buck Controller 16A Block Diagram SD0 DC/DC Buck Controller: Shows basic connection of the SD0 controller to two external power stages (AS3729B) for 16A output current. TEMP CTRL 1 CTRL 2 LX2 LX1 PVSS 0.47 uH 0.47 uH FB_SDx Vout (0.4-1.5V@16A) DVM, 10mV steps 47uF VSUP 10uF 47uF AS3729B SD controller TEMP1_SDx CTRL 1_SDx CTRL 2_SDx FB_SDx VSUP 10uF TEMP CTRL 1 CTRL 2 LX 2 LX1 PVSS PVSS 0. 47uH 0.47 uH 47uF VSUP 10uF 47uF AS3729B VSUP 10uF TEMP2_SDx CTRL 3_SDx CTRL 4_SDx PVSS TEMP3_SDx CTRL 5_SDx CTRL 6_SDx TEMP4_SDx CTRL 7_SDx CTRL 8_SDx

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- Power Management Functions Figure 27: SD0 DC/DC Buck Controller 24A Block Diagram SD0 DC/DC Buck Controller: Shows basic connection of the SD0 controller to three external power stages (AS3729B) for 24A output current. FB_SDx Vout (0.4-1.5V@24A) DVM, 10mV steps SD controller TEMP1_SDx CTRL 1_SDx CTRL 2_SDx FB_SDx TEMP2_SDx CTRL 3_SDx CTRL 4_SDx TEMP3_SDx CTRL 5_SDx CTRL 6_SDx TEMP4_SDx CTRL 7_SDx CTRL 8_SDx TEMP CTRL 1 CTRL 2 LX2 LX1 0.47uH 0.47uH 47uF AS3729B VSUP 10uF PVSS 47uF VSUP 10uF TEMP CTRL 1 CTRL 2 LX2 LX1 0.47uH 0.47uH 47uF AS3729B VSUP 10uF PVSS 47uF VSUP 10uF TEMP CTRL 1 CTRL 2 LX2 LX1 0.47uH 0.47uH 47uF AS3729B VSUP 10uF PVSS 47uF VSUP 10uF

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- Power Management Functions Figure 28: SD0 DC/DC Buck Controller 32A Block Diagram SD0 DC/DC Buck Controller: Shows basic connection of the SD0 controller to four external power stages (AS3729B) for 32A output current. Mode Settings Low Ripple, Low Noise Operation Bit settings: sdX_low_noise =1 In this mode there is no minimu m coil current necessary before switching off the PMOS. As long as the load current is superior to the ripple current the device operates in continuous mode. When the load current gets lower, the discontinuous mode is triggered. As result, the auto-z ero comparator stops the NMOS conduction to avoid load disc harger and the duty cycle is reduced down to tmin_on to keep the regulation loop stable. This results in a very low ri pple and noise, but decreased efficiency, at light loads, especially at low input to output voltage differences. FB_SDx Vout (0.4-1.5V@32A) DVM, 10mV steps SD controller TEMP1_SDx CTRL1_SDx CTRL2_SDx FB_SDx TEMP2_SDx CTRL3_SDx CTRL4_SDx TEMP3_SDx CTRL5_SDx CTRL6_SDx TEMP4_SDx CTRL7_SDx CTRL8_SDx TEMP CTRL1 CTRL2 LX2 LX1 0.47uH 0.47uH 47uF AS3729B VSUP 10uF PVSS 47uF VSUP 10uF TEMP CTRL1 CTRL2 LX2 LX1 0.47uH 0.47uH 47uF AS3729B VSUP 10uF PVSS 47uF VSUP 10uF TEMP CTRL1 CTRL2 LX2 LX1 0.47uH 0.47uH 47uF AS3729B VSUP 10uF PVSS 47uF VSUP 10uF TEMP CTRL1 CTRL2 LX2 LX1 0.47uH 0.47uH 47uF AS3729B VSUP 10uF PVSS 47uF VSUP 10uF

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- Power Management Functions Only in the case the load current gets so small that less than the minimum on-time of the PMOS would be needed to keep the loop in regulation the regulator will enter low power mode operation. The crossover poin t is about ~1% of the DCDC current limit. High Efficiency Operation (Default Setting) Bit settings: sdX_low_noise =0 In this mode there is a minimu m coil current necessary before switching off the PMOS. As a result there are less pulses necessary at low output loads, and therefore the efficiency at low output load is increased. As drawback this mode increases the ripple up to a higher output current. The crossover point to low power mode is already reached at reasonable high output currents (~10% of the DCDC current limit). It’s possible to switch between these two modes during operation. Low Power Operation (sdX_low_power=1) In this mode the controller is only running on a single phase. Only one output stage of the external power stage is used to reduce the power consumption for e.g. a stand-by mode operation. Power Save Operation (Automatically Controlled) As soon as the output voltage stays above the desired target value for a certain time, some internal blocks will be powered down leaving the output floating to lower the power consumption. Normal operation starts as soon as the output drops below the target value for a similar amount of time. To minimize the accuracy error some internal circuits are kept powered to assure a minimized output voltage ripple. Two addition guard bands, based on comparators, are set at ±5% of the target value to react quickly on large over/under-shoots by immediately turning on the output drivers without the normal ti me delays. This ensures a minimized ripple also in very extreme load conditions. Force PWM Mode Operation Even in the case the load current gets so small that less than the minimum on-time of the PMOS would be needed to keep the loop in regulation the regulator will still stay on the fixed switching frequency without en tering low power mode. To guarantee a stable output voltage also negative coil currents are possible. This mode guarantees the lowest possible ripple and a fixed frequency over all load conditions for powering noise sensitive RF circuits, but is compromising on the efficiency. The mode is enabled by setting sdX_force_pwm =1.

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- Power Management Functions Fast Regulation Mode This mode can be used to react faster on sudden load changes and thus minimize the over-/unde rshoot of the output voltage. This mode needs a bigger output capacitor to guarantee the stability of the regulator. The mode is enabled by setting sdX_fast =1. 100% PMOS ON Mode for Low Dropout Regulation For low input to output voltage difference the DCDC converter can use 100% duty cycle for the PMOS transistor, which is then in LDO mode. DVS (Dynamic Voltage Setting) For a quick change of output voltage a dedicated PWM interface can be used for SD0 and SD6. Please refer to PWM Control Interface chapter for more details. DVM (Dynamic Voltage Management) To minimize the over-/undersho ot during a change of the output voltage, the DVM can be enabled. With DVM the output voltage will ramp up/down with a selectable slope after the new value was written to the registers. Without DVM the slew rate of the output voltage is only determined by external components like the coil and load capacitor as well as the load current. DVM can be selected for all step-down controllers, but only for one at a time. (see dvm_time_SDx description) Automatic Phase Shedding SD0, SD1 and SD6 allow automa tic phase shedding which can be enabled with sdX_phsw_on . For SD0 a minimum number of phases for this automatic phase shedding can be defined with sd0_nph_min . Parameter Figure 29: DC/DC Buck Controller Parameter DC/DC Buck Controller Parameter: Shows the key electrical parameter of the DC/DC buck controller Symbol Parameter Conditions Min Typ Max Unit VIN Input voltage Pin VSUP_SDx 2.5 5.5 V VOUT Regulated output voltage 0.61 1.5 V VOUT_tol Output voltage tolerance min. 20mV -2 +2 % fSW Switching frequency fclk_int = 4MHz 2.7 3 MHz

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- Power Management Functions Figure 30: DC/DC Buck Controller External Components DC/DC Buck Controller External Components: Shows the external component parameter of the DC/DC buck controllers Symbol Parameter Conditions Min Typ Max Unit External Components 6A AS3729 # power stages 1 CFB Output capacitor Ceramic X5R or X7R, high performance 40 47 μF Ceramic X5R or X7R, cost optimized 20 22 μF CVSUP_SDx Input capacitor Ceramic X5R or X7R 6 10 μF LSDx Inductor 4A rated, 3MHz operation, low Ron 0.3 0.47 μH External Components 8A (HV) AS3728 # power stages 1 CFB Output Capacitor Ceramic X5R or X7R / 6.3V high performance 64 82 μF Ceramic X5R or X7R / 6.3V cost optimized 32 47 μF CHVSUP HV Input Capacitor Ceramic X5R or X7R / 25V 10 22 μF CBOOST Boost Capacitor Ceramic X5R or X7R / 6.3V 100 nF C5VSUP 5V Supply Capacitor Ceramic X5R or X7R / 6.3V 1 μF LI n d u c t o r 5A rated, 1MHz operation, low RON 0.5 1 μH

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- Power Management Functions LDO Regulators 11 universal IO range LDOs offer a wide input (1.7V to 5.5V) as well as a wide output (0.8 to 3. 3V) voltage range to be used for general purpose peripheral supply. LDO3 is intended to be used for tracking the output voltage of SD1 or SD6, step-size and range are matching those of SD1 and SD6. The extended input range LDO (LDO0) can work down to 1.15V on the input side, to be used as a post regulator after a DCDC with low output voltage (e.g. 1.2V). Up to 300mA possible output currents are offered with good noise and regulation performance and very low quiescent current even suitable for stand-by power supply. Figure 38: Universal IO LDO Block Diagram Universal IO LDO Block Diagram: Shows the internal structure of the PMOS linear regulators. PMOS Power Device 0.6ƣ VIN_LDOxError Amplifier LDOx VSS Vref 1.6V or 0.8V low noise CLOAD_LDOx

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- Power Management Functions LDO Parameter: Shows the key electrical parameter of the linear regulators Note(s) and/or Footnote(s): 1. Guaranteed by design and verified by laboratory evaluation and characterization; not production tested Figure 43: LDO External Components LDO External Components: Shows the external component parameter of the linear regulators LDO3 SW; VSUP>=3.3V, VOUT=1.0V0-11 250 mΩ PSRR Power supply rejection ratio f=1kHz 60 dB f=100kHz 30 IOFF Shut down current 100 nA IVDD Supply current without load 30 43 μA tSTART Startup time low current used during start-up 500 μs VLineReg Line regulation Static 0.07 %/V Transient; Slope: tr=15μs; delta 1V 20 mV VLoadReg Load regulation Static 0.014 %/m A Transient; Slope: tr=15μs; 1mA->300mA 30 mV RDIS discharge resistance LDO1-11 off; Vout=1V 720 Ω LDO0 off; Vout=1V 360 Ω Symbol Parameter Conditions Min Typ Max Unit COUT_LDO0 Output capacitor Ceramic X5R or X7R 1 μF COUT_LDO1-11 Output capacitor Ceramic X5R or X7R 0.7 μF CVIN_LDO0-11 Input capacitor Ceramic X5R or X7R 1 μF Symbol Parameter Conditions Min Typ Max Unit

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- Power Management Functions Backup Battery Charger The backup battery charger operates as a programmable voltage limited current source with a selectable output resistor. It is enabled by setting BBCMode in the Backup Battery Charger register to a value other than ‘00’b and offers the following features:

• Backup battery presence detection
• Selectable output resistor (R BBCOUT ) to reduce the current at higher voltages
• Programmable charge current I BBC
• Programmable maximum charging voltage V BBC
• Reverse current protection turns off backup battery charger automatically if V SUP<VVBAT_BKUP ; as soon as V SUP exceeds V VBAT_BKUP charging is started again automatically
• Charging is stopped automatically as soon as the backup battery is fully charged; if the voltage on pin V BAT_BKUP drops charging is started again automatically
• In case the main supply voltage V SUP or VBAT is larger than VBAT_BKUP charging of the backup battery is possible in state “Off” as well; the device will check V VBAT_BKUP every minute to determine if charging is required. Figure 46: Backup Battery Charger Block Diagram Backup Battery Charger Block Diagram: Shows the internal structure of the charger for the backup battery. Voltage limited Current Source VBAT_BKUP Digital Control VSUP

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- Power Management Functions Parameter Figure 47: Backup-Battery Charger Parameter Backup-Battery Charger Parameter: Shows the key electrical parameter of the charger for the backup battery Symbol Parameter Conditions Min Typ Max Unit VSUP Supply voltage range BBCVolt=’0’ 3.0 5.5 V BBCVolt=’1’ 3.3 5.5 VBBC Maximum charging voltage BBCVolt=’0’ 2.4 2.5 2.6 V BBCVolt=’1’ 2.9 3.0 3.1 IBBC Charge current Value is set by BBCCur in the Backup Battery Charger register -30% BBCCur +30% A V DELTA Delta voltage for resistive mode BBCResOff=’0’ 160 220 300 mV IVSUP Supply current BBCResOff=’0’ 20 μA BBCResOff=’1’ BBCPwrSave=’1’; backup battery full.

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Start-Up Figure 48: Start-Up Flow Chart 1/2 Start-Up Flow Chart 1/2: Shows the main state transitions during start-up Detailed Descriptions- System Functions Start-Up VBAT rising 1. V2_5 power up 2. Readout ROM fuse wait 200ms for RTC startup , if RTC_ON =1 skip with any I 2C command auto _off =1 POWER OFF state V2_5 power up RTC running if enabled Quiescent current < 10uA Pin ONKEY, LID, AC_OK debounce time=20msec Y Exit power _off state , if vbat _is_alive=1 only ONKEY=1 OR RTC alarm OR (LID =1 and lid _pwr_on and li _rising_en=0) OR (lid_rise/fall and lid _pwr_on=1) OR OR (ac_ok_rise/fall and ac _ok_pwr_on=1) OR (AC _OK =1 and ac _ok _pwr_on and ac_ok_rising_en=0) OR RTC wakeup bg_pd is 1 if vbat _is_alive=0 N Die Temp > 110°C OR THERM =1 VSUP debounce state Measuring VSUP, VBAT Quiesent current ~200uA N N Y NOBAT state vbat _is not alive vbat _is_alive VBAT >ResVoltRise VSUP>VSUP_min auto _off =1 or power _off_at _vsuplow =1 N N ON=1 or AC_OK =1 N Y VBAT <ResVoltFall or VSUP <VSUP_min for more than 500ms Y N Y DCDC calibrate calibrate currentsense of SD0, SD1 and SD6 VBAT <ResVoltRise or VSUP<VSUP_min once during calibrate Y Y wait 1ms N Run startup sequence Y

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions Figure 49: Start-Up Flow Chart 2/2 Start-Up Flow Chart 2/2: Shows the main state transitions during operation and stand-by power_of f=1 OR Die temp>140°C OR THERM=1 OR (VS UP<ResV oltFall && po wer_of f_at_vsuplow) OR (on key_lpress_rese t=0 && ONKEY lpress) N Y OFF delay wait off_delayN Reset all Registers Switch off Regulators reset registers and reload fuse s expect: ac_ok_pwr, rtc_on, lid_pwr_on, pwr_off_at_vsup_low RUN startup sequence regulator startup sequnece GPIO programming during sequence startup delay programmable set sdX_sequ_on=1 or ldoX_sequ_on=1 if regulator selected during startup RESET Timer regulator startup executed waiting time to release XRES pin 10..150ms ACTIVE state XRES=1 soft_reset=1 Y XRES is low or f orce_reset=1 or VS UP<VS UP_min or VBAT<ResVoltFall or emer gency_pd=1 or ONKE Y lpress or N standby_mode_on=1 or G PIOx=1 if GP IOx_iosf=6 or (ENAB LE1=0 an d enable1_deepsleep=1) OFF delay wait off_delay if enable1_enable=0 or wait until (ENABLE1=0 if enable1_deepsleep=1) N force_reset=1 or or (XRES is low if stdby_reset_disable=0) or V BAT<ResV oltFall or VSU P<VSU P_mi n or emer gency_pd=1 power down Sequence Down has to be written to E0-F3h before entering stand-by; reg0_select_stby to reg9_select_stby keep regulators on if regX_stby_on=1, force regulator voltage to regX_voltage_stby; „force off“ all other regulators STAND-BY state V2_5 power up all regulators with regX_stby_on=1 enalbed power down? N power down? N any inte rrupt applied or if e nable1_deepsleep=1 (ENALBE1=1 or lid_int or a c_ok_int) power down? N N Y VS UP debo unce st ate XINT=0 if an interrupt occuredY remove „stand-by force off“ of all regulat ors Sequence Up reg9_select_stby to reg0_select_stby remove regX_voltage_stby force (original voltage selection used) Sequence Down Switch OFF regulators where sdX_sequ_on=0 or ldoX_sequ_on=0 then write 00h to registers addressed by reg17_sel down to reg0_sel Power Off stat e Y Y Y THERM=1 Die temp>140°C VSUP_lo_deb=1 VB AT_lo_deb=1 bat_ov_de b=1 eme rgency power down em_shutdown _direct = 1 N Y e mer ge ncy power down? N e mer ge ncy power down? N Y Y power_of f=1 N Y emer gency_pd=1

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Normal Start-Up The following gives a brief description on a start-up from scratch (battery insertion). More details can be found in the start-up flow charts.

• Powering up V2_5 (wait till it’s above V POR)
• The external capacitor on CREF is charged to 1.6V.
• Check if VBAT is above ResVoltRise and VSUP above VSUP_min
• Configuration of DCDC controller (number of phases) and SD2/SD3/SD4/SD5 (combined mode or separated) is automatically detected during start-up detection phase.
• Current-sense calibration of SD0/SD1 and SD6 is performed
• Startup State machine reads out the internal Boot-OTP. The start-up sequence of Step -Down Converter, LDO’s and GPIOs are controlled by the Boot-OTP.
• Reset-Timer is set by the Boot-OTP
• The reset is released when the Reset Timer expires (external pin XRES_OUT)

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions Figure 50: Regulator Power-Up Sequence Regulator Power-Up Sequence: Shows timing relationships of the regulators and corresponding control signals during power-up Reg0_select<4:0> 0msec(If Reg1_delay=0) 1msec(If Reg1_delay=1 and del_time=0) 4msec(If Reg1_delay=1 and del_time=1) regulator power up sequence Reg1_select<4:0> Reg17_select<4:0> ... ENABLE2 CLK32k pin enabled SD0 If enable2_enable=1 XRES_OUT 1..15msec (res_timer) Reg0_v<7:0> Reg1_v<7:0> Reg17_v<7:0> Startup controlled I2C/SPI controlled 0msec(If Reg0_delay=0) 1msec(If Reg0_delay=1 and del_time=0) 4msec(If Reg0_delay=1 and del_time=1) 0msec(If Reg17_delay=0) 1msec(If Reg17_delay=1 and del_time=0) 4msec(If Reg17_delay=1 and del_time=1)

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Start-Up Reasons A Start-up can be activated from 8 different sources:

• VPOR has been reached (VSUP/ VBAT rising from scratch)
• ONKEY has been pulled high in power_off mode
• AC_OK has been pulled high in power_off mode
• LID has been pulled high in power_off mode
• RTC wake_up has been detected in power_off mode
• Reset cycle
• Soft Reset cycle
• ResVoltRise was reached Start-Up From Multiple Batteries If the system is powered by a single battery the start-up looks like below. Figure 51: Start-Up From Single Cell Batteries Start-Up From Single Cell Batteries: Shows basic start-up from a single cell battery (VBAT and VSUP tied together) For multi cell batteries or supplies greater 5V, the system needs a 5V pre-regulator to power the AS3722. The AS3722 is monitoring the battery voltage (VBAT) and controls the enable signal (EN5V) for the external 5V pre-regulator for generating a 5V system supply (VSUP). VBAT rise = ResVoltRise programmed in OTP Start-up sequence t (not to scale) VBAT/VSUP ncells=0 Regulator Voltages XRES serial communication possible res_timer 1-15ms ~4ms debounce

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions Figure 52: Start-Up From Multi Cell Batteries Start-Up From Multi Cell Batteries: Shows basic start-up from a multi cell battery including a 5V pre-regulator Reset XRES_IN and XRES_OUT are low active pins. An external pull-up to the periphery supply has to be added to XRES_IN. XRES_OUT is a push/pull output to VDD_GPIO_lv. During each reset cycle the following states are controlled by the AS3722:

• Power-down sequence of the regulators
• Pin XRES_OUT is forced to GND
• All registers are set to their default values after power-on, except the reset control- and status-registers.
• Normal startup with progra mmable power-on sequence and regulator voltages (see chapter Start-up)
• Reset is active until the programmable reset timer expires (set by register bits res_timer<2:0> ) Start-up sequence t (not to scale) VBAT ncells>0 Regulator Voltages XRES serial communication possible res_timer 1-15ms VBAT rise = ResVoltRise * (ncells +1) programmed in OTP EN5V enable external 5V regulator VSUP VSUP rise = vsup_min programmed in OTP ~4ms debounce ~4ms debounce

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Reset Reasons Reset can be activated from 10 different sources:

• VPOR has been reached (VSUP/ VBAT rising from scratch)
• VSUP low or VBAT low, ResVoltFall (2.5V) has been reached
• Software forced reset by force_reset (soft or hard)
• Software forced Power off mode by power_off
• ONKEY long press has been detected
• External triggered through the pin XRES_IN
• External triggered through the pin THERM
• Over-temperature T140 (d ie, SD0, SD1 or SD6)
• Watchdog
• VSUP overvoltage reached
• Transition to standby_mode Voltage Detection There are two types of voltage dependent resets: V POR and VRESRISE . VPOR monitors the voltage on V2_5 and V RESRISE monitors the voltage on VBAT/VSUP . The linear regulator for V2_5 is always on and uses the voltage VBAT/VSUP as its source. The pin XRES_OUT is only released if V2_5 is above V POR, VBAT is above ResVoltRise and VSUP is above vsup_min . VRESFALL is only accepted if the re set condition is longer than VRESMASK . This guard time is used to avoid a complete reset of the system in case of short drops of VBAT. Figure 53: VSUP Supervision VSUP Supervision: Describes the behavior of the PMIC when VSUP drops below ResVoltFall depending on OTP bit settings. SupResEn power_off_at_vsuplow auto_off Behavior if VSUP<ResVoltFall 0 x x LowBat interrupt is generated 10 0 Reset cycle is initiated, PMIC will move to “VSUP debonce” state and start-up if VSUP>ResVoltRise 10 1 Reset cycle is initiated, PMIC will move to “VSUP debonce” state and try to start-up if VSUP>ResVoltRise, if not it will go to the “Power off” state 11 x Reset cycle is initiated, PMIC will move to “Power off” state

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions Power Off To put the chip into ultralow power mode, write ‘1’ into power_off . The chip stays in power off mode until he gets a wakeup signal from either the ONKEY, LID or the AC_OK pin or from the RTC. For more detail s see the start-up flowchart (see Start-up Flow Chart). The bit power_off is automatically cleared by this reset cycle. During power_off state all circuits are shut-off except the Low Power LDO (V2_5) and the RTC oscillator (if enabled). Thus the current consumption of AS3722 is reduced to less than 10μA. The digital part is supplied by V2_5, all other circuits are turn ed off in this mode, including references and oscillator. Except the reset control registers all other registers are set to their default value after power-on. Software Forced Reset Writing ‘1’ into the register bit force_reset immediately starts a reset cycle. The bit force_reset is automatically cleared by this reset. External Triggered Reset If the pin XRES_IN is pulled from high to low by an external source (e.g. microprocessor or button) a reset cycle is started as well. Over-Temperature Reset The reset cycle can be started by over-temperature conditions. (see chapter Supervisor) Watchdog Reset If the watchdog is armed (register bit wtdg_on = 1 and wtdg_res_on = 1) and the timer expires it causes a reset. (see chapter Watchdog).

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Long ONKEY Press When applying a high level on the ONKEY input pin for 2s/4s/8s (depending on on_shutdown_delay ) a power_off is initiated. With the bit onkey_lpress_reset = 1 the chip will generate a reset cycle. This is thought as a safety feature when the SW hangs up and no watchdog is used. Powering down of the regulators can be done immediately or according to the power-off sequence depending on the em_shutdown_direct OTP bit. Figure 54: ONKEY Longpress Behavior ONKEY Longpress Behavior: Shows the selectable options for behaving on a long pressReset and Power-Off Sequence The regulator power-down sequence is inverted to the power-up sequence programmed in the OTP . It can be slightly modified by setting or clearing the sdX_sequ_on and ldoX_sequ_on bits. The bit is set automatically for all the regulators defined in the OTP start-up sequence.

• Regulators which have the corresponding sequ_on bit cleared will be shut down before the power-down sequence starts.
• Regulators which have the bit set and are in the power-up sequence of the OTP will shut down in an inverted order.
• Regulators which have the bit set and are not part of the power-up sequence will shut down after the sequence has been completed onkey_lpress_reset onkey_shutdown_delay Longpress Behavior 0 00 long press feature disabled 0 01 power_off after 2s long press delay 0 10 power_off after 4s long press delay 0 11 power_off after 8s long press delay 1 00 long press feature disabled 1 01 reset_cycle after 2s long press delay 1 10 reset_cycle after 4s long press delay 1 11 reset_cycle after 8s long press delay

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions Figure 55: Regulator Power-Down Sequence Regulator Power-Down Sequence: Shows timing relationships of the regulators and corresponding control signals during power-down 0msec(If Reg17_delay=0) 1msec(If Reg17_delay=1 and del_time=0) 4msec(If Reg17_delay=1 and del_time=1) regulator power down Reg16_select<4:0> sd/ldoX_sequ_on=1 Reg17_select<4:0> sd/ldoX_sequ_on=1 ... CLK32k pin enabled XRES_OUT Power down sequence controlled I2C/SPI controlled Start power down sequence, by I2C/SPI, Reset or Power downLDOs with ldoX_sequ_on=0 DCDCs with sdX_sequ_on=0 Reg1_select<4:0> sd/ldoX_sequ_on=1 Reg0_select<4:0> sd/ldoX_sequ_on=1 0msec(If Reg1_delay=0) 1msec(If Reg1_delay=1 and del_time=0) 4msec(If Reg1_delay=1 and del_time=1) All (other) LDOs/DCDCs sd/ldoX_sequ_on=1 off_delay (0..32msec) RESET or POWER off Clk32 pin shutdown at reset 0msec(If Reg16_delay=0) 1msec(If Reg16_delay=1 and del_time=0) 4msec(If Reg16_delay=1 and del_time=1) 0msec(If Reg2_delay=0) 1msec(If Reg2_delay=1 and del_time=0) 4msec(If Reg2_delay=1 and del_time=1) 0msec(If Reg0_delay=0) 1msec(If Reg0_delay=1 and del_time=0) 4msec(If Reg0_delay=1 and del_time=1) reset all registers

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Parameter Figure 56: Reset levels Reset Levels: Shows the electrical parameter of the voltage supervisors controlling start-up and reset cycles. Note(s) and/or Footnote(s): 1. It’s recommended to set the ResVoltRise level 200m V above the ResVoltFall level to have a hysteresis. 2. XRES signal is de-bounced with the specified mask time for rising- and falling slope of VBAT. Stand-By Stand-by allows shutting down a part or the complete system. Stand-by can be terminated by every possible interrupt or ENABLE1of the PMU. The interrupt has to be before going to stand-by. Symbol Parameter Conditions Min Typ Max Unit VPOR Overall power on reset Monitor voltage on V2_5; power on reset for all internal functions 1.5 2.0 2.3 V V RESRISE Reset level for VSUP/VBAT rising Monitor voltage on VBAT; rising level ResVoltRise(1) V Monitor voltage on VSUP; rising level vsup_min V VRESFALL Reset level for VSUP/VBAT falling Monitor voltage on VSUP/VBAT; falling level 2.5 V if SupResEn=1 ResVoltFall or vsup_min V V RESMASK Mask time for VRESFALL. Duration for VBAT<ResVoltFall or VSUP<vsup_min until a reset cycle is started (2) FastResEn = 0 4 ms FastResEn = 1 4 μs

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions Figure 57: Stand-By State Description Enter via ENABLE1 To enter stand-by mode the following settings have to be done:

• Enable just these IRQ sources which should lead to leave stand-by mode.
• Make sure that IRQ is inactive (IRQ flags get cleared by register reading)
• Enable ENABLE1 (enable1_deepsleep=1)
• Set regX_select_stby to define the sequence for going into stand-by for up to 10 regulators
• Set regX_voltage_stby if another voltage is needing during stand-by
• Define which regulators should be kept powered during stand-by (sdX_stby_on and ldoX_stby_on)
• Define the delay between the regulators when going into stand-by (regX_delay_stdby and delay_time_stby)
• Activate ENABLE1 (pull LOW) Enter via GPIO To enter stand-by mode the following settings have to be done:
• Enable just these IRQ sources which should lead to leave stand-by mode.
• Make sure that IRQ is inactive (IRQ flags get cleared by register reading)
• Set the GPIO to input (gpioX_mode = 0)
• Set the GPIO for stand-by control (gpioX_iosf = 5)
• Set regX_select_stby to define the sequence for going into stand-by for up to 10 regulators
• Set regX_voltage_stby if another voltage is needing during stand-by
• Define the regulators to be controlled by a specific GPIO (gpio_ctrl_sdX and gpio_ctrl_ldoX)
• Define which regulators should be kept powered during stand-by (sdX_stby_on and ldoX_stby_on)
• Define the delay between the regulators when going into stand-by (regX_delay_stdby and delay_time_stby)
• Set the delay for going into stand-by after GPIO activation (off_delay)
• Activate the selected GPIO (set to HIGH) Enter via SW To enter stand-by mode the following settings have to be done:
• Enable just these IRQ sources which should lead to leave stand-by mode.
• Make sure that IRQ is inactive (IRQ flags get cleared by register reading)
• Set regX_select_stby and regX_voltage_stby if another voltage is needing during stand-by for up to 10 regulators
• Define which regulators should be kept powered during stand-by (sdX_stby_on and ldoX_stby_on)
• Set the delay for going into stand-by after the SW command (off_delay)
• set standby_mode_on to 1 Stand-by V2_5 chip supply is kept ON All other regulators are switched OFF dependent on the bits sdX_stby_on and ldoX_stby_on XRES_OUT goes active (can be disabled with stdby_reset_disable) and pwr_good goes inactive

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Stand-By: Shows different options to enter and leave the stand-by state. Stand-By Sequence

• Regulators which have the sdX/ldoX_stby_on bit set will stay active during stand-by
• Regulators which have the sdX/ldoX_stby_on bit set and are part of the sequence ( regX_select_stby ) with a regX_voltage_stby >0 will change to the defined voltage in the sequence and stay on this voltage during stand_by
• Regulators which are part of the sequence (regX_select_stby ) with a regX_voltage_stby =0 will be turned off in the sequence.
• Regulators which have the sdX/ldoX_stby_on bit cleared and are part of the sequence ( regX_select_stby ) with a regX_voltage_stby >0 will change to the defined voltage in the sequence and be turned off at the end of the sequence
• Regulators which have the sdX/ldoX_stby_on bit cleared and are not part of the sequence will be turned off at the end of the sequence Figure 58: Stand-By Leave Stand-By Leave: Describes the possibilities of the PMIC to leave the stand-by state Leave The chip will come out of stand-by with any IRQ activation (it’s not possible to leave with the same GPIO you entered stand-by) If enable1_deepsleep=1 the chip will come out of stand-by with ENABLE1 going HIGH or the LID or AC_OK interrupt. Start-Up sequence is provided defined by regX_select_stby, regX_delay_stdby and delay_time_stby State Description ENABLE1 any interrupt enable1_deepsleep wakeup from stand-by/deep- sleep 1•1 interrupt masking •1 any interrupt not masked set XINT output lid_int oc_ok_int disable_stby_lid_int disable_stby_acok_int

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions Figure 59: Regulator Stand-By Entry Sequence Regulator Stand-By Entry Sequence: Shows timing relationships of the regulators and corresponding control signals during entering stand-by mode regulator stand_by entry Reg0_select_stby<4:0> ... CLK32k pin enabled XRES_OUT Power down sequence controlled I2C/SPI controlled 0msec(If Reg1_delay_stby=0) 1msec(If Reg1_delay_stby=1 and delay_time_stby=0) 4msec(If Reg1_delay_stby=1 and delay_time_stby=1) 0msec(If Reg0_delay_stby=0) 1msec(If Reg0_delay_stby=1 and delay_time_stby=0) 4msec(If Reg0_delay_stby=1 and delay_time_stby=1) All (other) LDOs/DCDCs still active off_delay (0..32msec) only if enable1_stby_en=0 if enable2_enable=1 ENABLE2 SD0 Stand-by start 0msec(If Reg8_delay_stby=0) 1msec(If Reg8_delay_stby=1 and del_time_stby=0) 4msec(If Reg8_delay_stby=1 and del_time_stby=1) sd/ldoX_stby_on=1 Reg1_select_stby<4:0> Reg8_select_stby<4:0> Reg9_select_stby<4:0> low if stby_reset_enable=1 0msec(If Reg5_delay_stby=0) 1msec(If Reg5_delay_stby=1 and delay_time_stby=0) 4msec(If Reg5_delay_stby=1 and delay_time_stby=1) 0msec(If Reg9_delay_stby=0) 1msec(If Reg9_delay_stby=1 and del_time_stby=0) 4msec(If Reg9_delay_stby=1 and del_time_stby=1) via SPI/I2C if standby_mode_on=1 via GPIO if gpioX_iosf = 5 and GPIOx going HIGH via ENABLE1 (going LOW) if enable1_deepsleep=1 sd/ldoX_stby_on=0 Reg0_voltage_stby>0 sd/ldoX_stby_on=0 sd/ldoX_stby_on=1

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Figure 60: Regulator Stand-By Exit Sequence Regulator Stand-By Exit Sequence: Shows timing relationships of the regulators and corresponding control signals during exiting stand-by mode regulator stand-by exit Reg9_select_stby<4:0> ... CLK32k pin enabled XRES_OUT Power up sequence controlled start power up sequence, by any interrupt or ENALBE1=HIGH or ac_ok_int or lid_int if enable1_deepsleep=1 0msec(If Reg8_delay_stby=0) 1msec(If Reg8_delay_stby=1 and delay_time_stby=0) 4msec(If Reg8_delay_stby=1 and delay_time_stby=1) I2C/SPI controlled if eanble2_enable=1 ENABLE2 SD0 Interrupt/ENABLE1 0msec(If Reg0_delay_stby=0) 1msec(If Reg0_delay_stby=1 and delay_time_stby=0) 4msec(If Reg0_delay_stby=1 and delay_time_stby=1) Reg7_voltage_stby>0 Reg6_voltage_stby>0 Reg1_voltage_stby>0 Reg0_voltage_stby>0 Caution! No I2C/SPI command allowed as long as the sequence is not finished All (other) LDOs/DCDCs which have been deactivated during standby Reg8_select_stby<4:0> Reg1_select_stby<4:0> Reg0_select_stby<4:0> low if stby_reset_enable=1 res_timer (if stby_reset_enable=1) 0msec(If Reg9_delay_stby=0) 1msec(If Reg9_delay_stby=1 and delay_time_stby=0) 4msec(If Reg9_delay_stby=1 and delay_time_stby=1)

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Digital IO Supply Concept GPIOs can be switched between VSUP_GPIO and VDD_GPIO_lv supply for the output function. All other digital outputs are supplied with VDD_GPIO_lv. Figure 63: Digital IO Supply Concept Digital IO Supply Concept: Shows the supply concept for digital inputs and outputs. GPIO Pins The device contains 8 GPIO pins. Each of the pins can be configured as digital input, digital input (with pull-up or pull-down), ADC input (tri-state), push-pull output (selectable lower or higher GPIO supply), or open drain output (with or without pull-up). When configured as output the output source can be a register bit, or the PWM generator. The polarity of the input and output signals can be inverted with the corresponding gpioX_invert bit, all further descriptions refer to normal (non-inverted) mode. AS3722 VSUP_GPIO 2.5 … 5.5V VDD_GPIO_lv 1.7 … 3.6V GPIO<7:0> XRES_OUT XINT CLK32K OC_PG EN5V ENABLEx THERM XRES_IN AC_OK LID PWM_CLK PWM_DAT Outputs Inputs V2_5 GPIOs Digital Core

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions Figure 64: GPIO Block Diagram GPIO Block Diagram: Shows the internal structure of the IO pads IO Functions Normal IO Operation If set to input, the logic level of the signal present at the GPIOx pin can be read from gpioX_in . If the output mode is chosen, gpioX_out specifies the logic level of the GPIOx pin. This mode is also used for the on/off control of the DCDC and LDOs. The selection which regu lator is controlled by which GPIO, is done with the gpio_ctrl_sdX or gpio_ctrl_ldoX bits. The gpioX_mode should be set to input. Interrupt Output GPIOx pin logic state is derived from the interrupt signal INT. Whenever an interrupt is present, the GPIOx pin is pulled high. The gpioX_mode should be set to output. VSUP_VBAT_Low Output (not de-bounced) GPIOx pin will go high if VSUP falls below vsup_min or VBAT falls below ResVoltFa ll and SupResEn = 0. The gpioX_mode should be set to output. GPIO Interrupt Input A falling or rising edge will set the gpio_int bit. The gpioX_mode should be set to input. VSUP_GPIOgpioX_out: 0 Interrupt output: 1 VSUP_VBAT_low output: 2 GPIO interrupt input: 3 PWM input: 4 vselect_stdby input: 5 OC_PG_SD0: 6 pwr_good output: 7 Q32k output: 8 watchdog input: 9 PWM output: 12 VSUP_VBAT_low (debounced): 13 n/a: 10 Soft reset input: 11 OC_PG_SD6 low output: 14 n/a: 15 gpioX_iosf gpioX_invert gpioX_iosf gpioX_in: 0 gpioX_mode = 0,2,4,5 or 6 gpioX_mode = 1 or 7 gpioX_mode = 1, 2 or 6 GPIOx gpioX_mode = 4 or 6 gpioX_mode = 5 300k 300k VDD_GPIO_lv gpioX_mode = 1 gpioX_mode = 4, 6 or 7

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions PWM Input With this input the PWM signal of the internal PWM generator can be over-ruled. This input is then used to drive the PWM output function of a GPIO if selected. The gpioX_mode should be set to input. Voltage_sdtby + Restart Input As long as the GPIOx pin is high the DCDC/LDOs operate with the normal register settings. If the GPIOx pin goes low the settings will change to the ones stored in regX_voltage_stby . In addition the chip is se t into stand-by mode. regX_select_stby defines the order of the regulators for going into stand_by. All other regulators not defined in sdX_stby_on or ldoX_stdby_on will be put into stand_by simultaneously at the end of the sequence. Pulling GPIOx pin high will wake-up the chip. The sequence is reversed to going into stand_by. Delays for the sequence can be set with regX_stby_delay and delay_time_stby . The gpioX_mode should be set to input. OC_PG_SD0 Output Please see section OC_PG pin fu nction description in chapter OC_PG ( Output Pins ) for a detailed description. PWRGOOD Output This signal will go high at the end of the start-up sequence. This can be used as a second reset si gnal to the processor to e.g. start oscillators. The gpioX_mode should be set to output. Q32k Output When selected the GPIOx will provide the 32kHz RTC crystal frequency. If the oscillator is not enabled or not assembled an internal RC oscillator based clock will be used for the output. The gpioX_mode should be set to output. Watchdog Input When pulling the GPIO high the watchdog will be triggered to avoid a reset cycle initiated by the watchdog. The gpioX_mode should be set to input. Soft-Reset Input This will perform a start-up sequence to reset all voltage registers. The gpioX_mode should be set to input. PWM Output The GPIO block includes an internal programmable PWM generator (can be connected to any of the GPIO outputs). Its timing is defined by pwm_h_time , pwm_l_time and pwm_div . The gpioX_mode should be set to output.

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions Vsup_vbat_low Output (de-bounced) GPIOx pin will go high if VSUP falls below vsup_min or VBAT falls below ResVoltFall and SupResEn = 0. The gpioX_mode should be set to output. OC_PG_SD6 Output GPIOx pin will go high if DCDC6 is disabled. GPIOx pin will be low during start-up of DCDC6. After start-up of DCDC6 the GPIOx pin will be high as long DCDC6 is not in a low voltage or overcurrent operation. The inputs may be masked with pg_powergood_sd6_mask and pg_ovcurr_sd6_mask. There is no 90us black-out time like for DCDC0. The gpioX_mode should be set to output. ADC_reference Output By setting adc_buf_on the buffered 1.6V ADC reference is available on GPIO7. The gpio7_mode should be set to “3” (tristate) gpio7_iosf should be set to “0” (normal). Dedicated IO Pins Input Pins ENABLE1/CORE_PWRREQ As long as the ENABLE1 pin is high the DCDC/LDOs operate with the normal register settings. If the ENABLE1 pin goes low the settings will change to the ones stored in regX_voltage_stby . In addition the chip is se t into stand-by mode. regX_select_stby defines the order of the regulators for going into stand_by. All other regulators not defined in sdX_stby_on or ldoX_stdby_on will be put into stand_by simultaneously at the end of the sequence. Pulling ENABLE1 pin high will wake-up the chip. The sequence is reversed to going into stand_by. Delays for the sequence can be set with regX_stby_delay and delay_time_stby . ENABLE1 pin is default disabled after start-up from off state. enable1_stby_en and enable1_inv will enable the input and set the polarity. ENABLE2/CPU_PWRREQ ENABLE2 is a dedicated pin to on/off control of SD0. enable2_enable and enable2_inv will enable the input and set the polarity. THERM Is an external signal which triggers an immediate power down similar to VSUP_low or a chip over-temperature event. The chip will not power-on again before the THERM signal is de-asserted.

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions AC_OK Additional power_on input whic h is used to e.g. detect a charger adapter. With ac_ok_rising_en the detection can be switched between edge and level, while ac_ok_pwr_on will disable/enable the input. ac_ok_pwr can be used to check the status. An interrupt can be generated on rising and falling edges. In addition this input is also us ed to generate the OC_PG output. LID Additional power_on input which is used to e.g. detect the open/close stated of the lid from a clam shell device. With lid_rising_en the detection can be switched between edge and level, while lid_pwr_on will disable/enable the input. lid_pwr can be used to check the status. An interrupt can be generated on rising and falling edges. Output Pins VBAT_ALARM (not de-bounced) Will go high if VSUP falls below ResVoltFall and SupResEn = 0. CLK32K Dedicated pin for providing a 32kHz clock from the RTC oscillator. The pin can be disabled with clk32out_en . XINT Dedicated pin for providing an active low output signal on any enabled (un-masked) interrupt event. For XINT pin an internal pull-up can be enable d to VDD_GPIO_lv ( INT_pullup ). This bit also switches the output driver to open drain. OC_PG Is a dedicated output pin signaling over-current and power good events of SD0 plus additional inputs (see block diagram below).

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions Figure 65: OC_PG Block Diagram OC_PG Block Diagram: Shows the internal structure of the overcurrent-power-good output. =1 & pg_ac_ok_mask OC_PG AC_OK pg_ac_ok_inv ac_ok_pwr =1 & pg_gpio3_mask GPIO3 gpio3_invert gpio3_in GPIO4 GPIO5 pg_vresfall_mask VBAT < ResVoltFall or VSUP < vsup_min pg_ovcurr_sd0_mask ov_curr SD0 =1 & pg_gpio4_mask gpio4_in gpio4_invert =1 & pg_gpio5_mask gpio5_in gpio5_invert pg_pwrgood_sd0_mask sd0_lv sd0_on sd0_vsel Startup FSM & interrupt logic

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Figure 66: OC_PG Timing Diagram OC_PG Timing Diagram: Shows the signal timing of the overcurrent-power-good output. Supervisor The PMIC has a build in over-temperature protection, which could be switched off with the serial interface signal temp_pmc_on (enabled by default; it is not recommended to disable the over-temperature protection). Temperature Supervision The chip has three signals for the serial interface: ov_temp_alarm0, ov_temp_alarm1 and ov_temp_shutdown . The flags ov_temp_alarm0/1 are automatically reset if the over-temperature condition is removed, whereas ov_temp_shutdown has to be reset by th e serial interface with the signal rst_ov_temp_shutdown . If the flag ov_temp_shutdown is set, an automatic reset of the complete chip is initiated. The chip will only start-up when the temperature falls below the T alarm0 level (including hysteresis). The flag ov_temp_shutdown is not affected by this reset cycle allowing the software to detect the reason for this unexpected shutdown: A similar supervision is done for the power-stage dies. The over-temperature alarm flag ( temp_sdX_alarm )is set, when a sub die reaches the alarm level. The over-temperature alarm flag is set anyway and cleared when the temperature falls below the threshold. When reaching th e shutdown level an automatic reset (can be masked) of th e AS3722 is initiated. The sd0_on Vout Tstart = 250usec max. OC_PG 10nsec delay OC_PG>90usec high (typ. 120usec). AC_OK or GPIO3,4,5 if enalbed 100nsec delay done in analog sd0_vsel pg_vmask_time=4/8usec mask 10nsec delay 100nsec delay done in analog sd0_lv or ov_curr

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions corresponding status bit ( temp_sdX_shutdown ) can only be cleared by reading the register. It’s possible to generate an interrupt (mask able) on reaching both the alarm and the shutdown level. Figure 67: Temperature Supervision Characteristics Temperature Supervision Characteristic: Shows the key electrical parameter of the over-temperature supervision. Current Supervision All LDO’s and DCDC step downs have an integrated over-current protection. When a regulator runs into its current limit, the output voltage will drop and trigger a “low voltage” interrupt when hitting the threshold (-5% for SD0-6). Symbol Parameter Conditions Min Typ Max Unit Talarm0 ov_temp_alarm0 rising threshold 79 94 109 ºC Talarm1 ov_temp_alarm1 rising threshold 98 113 128 ºC Tshutdown ov_temp_shutdown rising threshold 125 140 155 ºC Thyst ov_temp_110/140 hysteresis 5º C TSDx_alarm temp_sdX_alarm rising threshold 95 110 1125 ºC TSDx_shutdown temp_sdX_shutdown rising threshold 125 140 155 ºC

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Watchdog The purpose of the watchdog is to detect a deadlock of the software. If the watchdog is active, it must receive a continuous trigger signal within a programma ble time window. If there is no signal anymore for a certain time period from a defined pad or special serial interface bit, it starts either a complete reset cycle or initiates the power off sequence. The watchdog is highly configurable by the following register bits:

• The complete block can be switched on by wtdg_on = 1 and off by wtdg_on = 0.
• The watchdog time window is defined by the register wtdg_timer between 1s and 128s.
• The trigger signal can be ei ther triggered by setting wtdg_sw_sig or using a HW signal on one of the GPIO pins (gpioX_iosf =9).
• If the watchdog expires, the system waits another second before reacting according to wtdg_mode (OTP setting)
• 0: interrupt 8s before the wa tchdog expires, only if the interrupt is not masked
• 1: reset_cycle with re-start
• 2: power_off
• 3: reset_cycle with re-start up to two times, if the watchdog expires a third ti me the systems goes into power_off
• Whether the watchdog caused a reset can be seen in the reset_reason . Figure 68: Watchdog Timing Watchdog Timing: Shows the basic timing relations of the watchdog counter and related signals. n-1n n-2 n n-1 9 8 00watchdog counter counter set to n seconds counter reset by setting bit wtdg_sw_sig wdtg_sw_sig XINT 2 1 interrupt triggered if enalbed watchdog expires action according to wtdg_mode

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions Interrupt Generation The interrupt controller generates an interrupt request for the host controller as soon as one or more of the bits in the Interrupt 1…3 register are set by pulling low pin XINT. All the interrupt sources can be enabled in the In terrupt Mask 1…3 register. The Interrupt 1…3 registers are cleared automatically after the host controller has read them. To prevent the AS3722device from losing an interrupt event, the register that is read is captured before it is transmitted to th e host controller via the serial interface. As soon as the transm ission of the captured value is complete a logical AND operation with the bit wise inverted captured value is applied to the register to clear all interrupt bits that have already been transmitted. Clearing the read interrupt bits takes 2 clock cyc les, a read access to the same register before the clearing process has completed will yield a value of ‘0’ . Note that an interr upt that has been present at the previous read access will be cleared as well in case it occurs again before the clearing process has completed.

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions 10-Bit ADC This general purpose ADC can be used for measuring several voltages and currents to perform functions like battery monitor, temperature supervision, bu tton press detection, etc. Figure 69: ADC Input Sources # Source Range LSB Mode Description 0 SD0_current 1.6V 1.56mV 1:1 output current of SD0 1 SD1_current 1.6V 1.56mV 1:1 output current of SD1 2 SD6_current 1.6V 1.56mV 1:1 output current of SD6 3 DIE temperature 1.6V 1.56mV 1:1 Tj = (0.7698 * ADC10<9:0>) - 274 4 VSUP 5.5V 6.25mV 4:1 check main system supply voltage 5 GPIO1 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 6 GPIO2 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 7 GPIO3 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 8 GPIO4 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 9 GPIO6 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 10 GPIO7 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 11 VBAT 15V 23.44mV 15:1 value valid below 15V only

12 PWM_CLK2/

ADC1 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1

13 PWM_DAT2/

ADC2 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 14 - reserved 15 - reserved 16 TEMP1_SD0 1.56mV Tj = 326.5 - ADC10<9:0> * 0.3734 17 TEMP2_SD0 1.56mV Tj = 326.5 - ADC10<9:0> * 0.3734 18 TEMP3_SD0 1.56mV Tj = 326.5 - ADC10<9:0> * 0.3734 19 TEMP4_SD0 1.56mV Tj = 326.5 - ADC10<9:0> * 0.3734

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions ADC Input Sources: Shows the various inputs with the corresponding resolution which can be measured by the internal ADC. The ADC-10 features 2 control register for measuring 2 different sources. By writing to the control register of channel 0 or channel 1 the selected measurement will be performed and the result placed in the corresponding result register. ADC10 has only one conversion unit, meaning measurements for source 1 and source 2 will be done time multiplexed. ADC channel 1 is capable to pe rform automatic conversion in 0.5s or 1s intervals of the selected source. In addition a free programmable threshold with hysteresis (ADC1_threshold_lo/hi ) can be set to generate interrupts once the threshold is passed. adc1_interrupt_mode defines if an interr upt is generated on every threshold passing or only if the measured value rises above the high threshold or fall below the low threshold. The ADC interrupt can be masked as every other interrupt. By setting adc_buf_on the buffered 1.6V ADC reference is available on GPIO7 during the conversion time. To give the ADC reference output enough time to settle the pre-sample time gets stretched from 32us to 62us. The gpio7_mode should be set to “3” (tristate) gpio7_iosf should be set to “0” (normal). 20 TEMP_SD1 1.56mV Tj = 326.5 - ADC10<9:0> * 0.3734 21 TEMP1_SD6 1.56mV Tj = 326.5 - ADC10<9:0> * 0.3734 22 TEMP2_SD6 1.56mV Tj = 326.5 - ADC10<9:0> * 0.3734 # Source Range LSB Mode Description

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Parameter Figure 70: ADC Characteristics ADC Characteristics: Shows the key electrical parameter of the internal ADC. Symbol Parameter Conditions Min Typ Max Unit Resolution 10 Bit Vin Input Voltage Range for 1:1 mode 0 1.6 V DNL Differential Nonlinearity 1LSB 1.56mV for 1:1 (depending on selected channel) ± 0.3 LSB INL Integral Nonlinearity ± 0.9 LSB Vos Input Offset Voltage 2 LSB Rin Input Impedance 1:1 100 MΩ 4:1 200 kΩ Cin Input Capacitance 9 pF Idd Power Supply Current during conversion only 500 μA Idd Power Down Current 100 nA Transient Parameters (25°C) Tc Conversion Time 40 μs fc Clock Frequency internal CLK frequency/8 f clk_int/ 8 kHz ts Settling time of S&H 1 μs ADC Reference Buffer VOUT Output voltage -1.2% 1.6 +1.2% V IOUT Output current ROUT>6.4kΩ 02 5 0 u A COUT Output capacitor 0 50 pF tSTART Start-up time 10 us

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions Figure 71: ADC Timing Diagram ADC Timing Diagram: Shows timing of the control and data signals of the internal ADC. Real Time Clock The RTC module provides time information to the system. It is implemented as second counter derived from the 32kHz oscillator delivering the necessary accurate time base. The actual time can be read from the second, minute, hour, day month year registers in BCD format. Both 24h and am/pm mode is supported. All counters are set to 0 at a power-on-reset. The host controller can set the counter to any value by setting the RTC registers. To prevent ambiguous time information because some of the registers being incremented before all of the registers have been read or written, a parallel shadow register is implemented. Every time a write/read access via the serial interface occurs the parallel shadow register is updated with the current value of the RTC counter. Any write access to the RTCsecond register will disable the update of the parallel shadow register and set the value of the appropriate byte of the parallel shadow register. Any subsequent write access to the RTCyear register will transfer the current value of the parallel shadow register to the RTCsecond/minute/hour/…/year register and the update of the parallel shadow register is enabled again. Similarly, any read access to the RTCsecond register will freeze the current value of the parallel shadow register and submit the appropriate byte adc0_start_conversion 0 11 ADC clock ADC on ADC start 16us if adc_buf_on = 0 else 96us adc0_result_not_ready adc0_D[9:0] result readyresult not valid 1 12 ADC eoc 0 111 12 16us if adc_buf_on = 0 else 96us adc1_start_conversion adc1_result_not_ready adc1_D[9:0] result readyresult not valid

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions to the host controller via the serial interface. Any subsequent read access to the RTCyear register will enable the update of the parallel register again. This mechanism makes sure that the maximum error of the value that is written to or read from the registers is 1 second. With the rtc_lock bit in OTP , the write access to the RTC registers can be locked and only be eabled by writing a “magic” word to the appropriate address. To start the RTC, rtc_on bit has to be set to 1. The RTC stops automatically at its highest value to prevent overrun. Alarm The RTC module includes an alarm function. When the content of the RTCAlarm registers equals the content of the RTC registers bit rtc_alarm will be set in the interrupt register. Furthermore the RTC module can generate a repeating interrupt every second, every minute, every 2 minutes or every 8 minutes. To avoid ambiguous behavior during write access to the RTCAlarm registers any write access to the RTCAlarmSecond register will disable the alarm function; any subsequent write access to the RTCAlarmyear will enable the alarm function again.

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions I2C Feature List

• High Speed mode capability [max. SCL-frequency is 3.4MHz (2.7MHz for sequential reads)]
• 7+1-bit addressing mode
• 60h x 8-bit data registers (word address 0x00 - 0x60)
• Write formats: Single-Byte-Write, Page-Write
• Read formats: Current-Addr ess-Read, Random-Read, Sequential-Read
• SDA input delay and SCL spik e filtering by integrated RC-components I2C Protocol Figure 74: I2C Symbol Definition I2C Symbol Definition: Shows the symbols used in the following mode descriptions. Symbol Definition RW Note S Start condition after stop R 1 bit Sr Repeated start R 1 bit DW Device address for write R 1000 0000b (80h) DR Device address for read R 1000 0001b (81h) WA Word address R 8 bit A Acknowledge W 1 bit NN o A c k n o w l e d g e R 1 b i t reg_data Register data/write R 8 bit data (n) Register data/read W 8 bit P Stop condition R 1 bit WA++ Increment word address internally R during acknowledge

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Detailed Descriptions- System Functions SPI Parameter Figure 83: SPI Characteristics SPI Characteristic: Shows the key electrical parameter of the SPI interface. PMW DVS Control Interfaces Two dedicated PMW interfaces can be used to perform DVS on SD0 and SD6. The voltage is determined by a base value ( vpwmX_base ) and the increments according to the duty cycle of the pwm signal. The step-size and reset behavior can be programmed individually for both interfaces. A threshold value of 0.6-to 1.84V can be set in the OTP to limit the maximum allowed output voltage for each of the two regulators. Symbol Parameter Conditions Min Typ Max Unit SCLK/SDI/SCSB Pins VIH High-Level Input Voltage 1.4 VSUP_GPIO V VIL Low-Level Input Voltage 0.4 V VHYS Hysteresis 0.2 x VSUP_GP IO V ILEAK Input Leakage Current to VSUP_GPIO and GND_PAD -5 5 μA SDO Pin VOH High-Level Output Voltage at -2.0mA 0.8 x VDD_GPI O_lv V VOL Low-Level Output Voltage at 2.0mA 0.2 x VDD_GPIO_lv V CLOAD Capacitive Load 50 pF

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Register Overview Figure 86: Register Overview 00h SD0Voltage sd0_low_power sd0_vsel<6:0> 01h SD1Voltage sd0_low_power sd1_vsel<6:0> 02h SD2Voltage sd2_frequ sd2_vsel<6:0> 03h SD3Voltage sd3_frequ sd3_vsel<6:0> 04h SD4Voltage sd4_frequ sd4_vsel<6:0> 05h SD5Voltage sd5_frequ sd5_vsel<6:0> 06h SD6Voltage sd6_low_power sd6_vsel<6:0> 08h GPIO0control gpio0_invert gpio0_iosf <6:3> gpio0_mode<2:0> 09h GPIO1control gpio1_invert gpio1_iosf <6:3> gpio1_mode<2:0> 0Ah GPIO2control gpio2_invert gpio2_iosf <6:3> gpio2_mode<2:0> 0Bh GPIO3control gpio3_invert gpio3_iosf <6:3> gpio3_mode<2:0> 0Ch GPIO4control gpio4_invert gpio4_iosf <6:3> gpio4_mode<2:0> 0Dh GPIO5control gpio5_invert gpio5_iosf <6:3> gpio5_mode<2:0> 0Eh GPIO6control gpio6_invert gpio6_iosf <6:3> gpio6_mode<2:0> 0Fh GPIO7control gpio7_invert gpio7_iosf <6:3> gpio7_mode<2:0> 10h LDO0Voltage ldo0_ilimit - ldo0_vsel<4:0> Register Description

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description 11h LDO1Voltage ldo1_ilimit ldo1_vsel<6:0> 12h LDO2Voltage ldo2_ilimit ldo2_vsel<6:0> 13h LDO3Voltage ldo3_mode<7:6> ldo3_vsel<5:0> 14h LDO4Voltage ldo4_ilimit ldo4_vsel<6:0> 15h LDO5Voltage ldo5_ilimit ldo5_vsel<6:0> 16h LDO6Voltage ldo6_ilimit ldo6_vsel<6:0> 17h LDO7Voltage ldo7_ilimit ldo7_vsel<6:0> 19h LDO9Voltage ldo9_ilimit ldo9_vsel<6:0> 1Ah LDO10Voltage ldo10_ilimit ld o10_vsel<6:0> 1Bh LDO11Voltage ldo11_ilimit ld o11_vsel<6:0> 1Dh LDO3_settings - ldo3_vtrack_tr<1:0> 1Eh GPIO_deb1 gpio3_deb<7:6> gpio2_deb<5:4> gpio1_deb<3:2> gpio0_deb<1:0> 1Fh GPIO_deb2 gpio7_deb<7:6> gpio6_deb<5:4> gpio5_deb<3:2> gpio4_deb<1:0> 20h GPIOsignal_out gpio7_out gpio6_out gpio5_o ut gpio4_out gpio3_ out gpio2_out gpio1_out gpio0_out 21h GPIOsignal_in gpio7_in gpio6_in gpio5_in gpio4_in gpio3_i n gpio2_in gpio 1_in gpio0_in 22h Reg_sequ_mod1 - sd6_sequ _on sd5_seq u_on sd4_sequ_ on sd3_se qu_on sd2_sequ_on sd1_sequ_on sd0_sequ_on 23h Reg_sequ_mod2 ldo7_sequ_on ldo6_seq u_on ldo5_se qu_on ldo4_sequ _on ldo3_se qu_on ldo2_sequ_on ldo1_sequ_on ldo0_sequ_on 24h Reg_sequ_mod3 - ldo11_s equ_on ldo10_sequ_on ldo9_sequ_on -

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description 27h SD_phsw_ctrl - sd0_nph_min<5:3> sd6_phsw_ on sd1_phsw_on sd1_phsw_on 28h SD_phsw_status sdmph_clk_div<7:6> - sd6_nph_a uto sd1_np 29h SD0_control sd0_trim_gm<7:6> sd0_forc e_pwm sd0_fast sd0_co mbine_ phase sd0_phases<2:0> 2Ah SD1_control sd1_trim_gm<7:6> sd1_forc e_pwm sd1_fast sd1_co mbine_ phase sd0_low_noise sd1_low_noise sd1_phases 2Bh SDmph_control disable_sd0_pull d - sd6_startslew<5:4> sd1_startslew<3:2> sd0_startslew<1:0> 2Ch SD23_control - sd3_fast sd3_forc e_pwm sd3_low_n oise - sd2_fast sd2_force_pwm sd2_low_noise 2Dh SD4_control - sd4_fast sd4_force_pwm sd4_low_noise 2Eh SD5_control - sd5_fast sd5_force_pwm sd5_low_noise 2Fh SD6_control sd6_trim_gm<7:6> sd6_forc e_pwm sd6_fast sd6_co mbine_ phase sd6_ph2c_on sd6_low_noise sd6_phases 30h SD_dvm - dvm_time_sd6<5:4> dvm_time_sd1<3:2> dvm_time_sd0<1:0> 31h Resetreason reset_reason<7:4> startup_reason<3:0> 32h Battery_voltage_monit or FastResEn SupResEn ResVolt Fall<5:3> ResVoltRise<2:0> 33h Startup_Control - onkey_l press_r eset lid_rising_en ac_ok_rising_en power_off_at_vsuplo w 34h ResetTimer - stby_reset _enable auto_off off_delay<4:3> - res_timer<1:0>

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description 35h ReferenceControl force_softreset - clk_div2 standby_m ode_on clk_int<3:1> low_power_on 36h ResetControl - reset_debounce<4:3> onkey_input power_off force_reset 37h OvertemperatureContr ol - ov_temp_ alarm0 rst_ov_ temp_s hutdow n ov_temp_shutd own ov_temp_alarm1 temp_pmc_on 38h WatchdogControl - wtdg_mode<2:1> wtdg_on 39h Reg_standby_mod1 disable_regpd sd6_stby_ on sd5_stb y_on sd4_stby_ on sd3_stb y_on sd2_stby_on sd1_stby_on sd0_stby_on 3Ah Reg_standby_mod2 ldo7_stby_on ldo6_stby _on ldo5_stb y_on ldo4_stby_ on ldo3_st by_on ldo2_stby_on ldo1_stby_on ldo0_stby_on 3Bh Reg_standby_mod3 - ldo11_s tby_on ldo10_stby_on ldo9_stby_on - 3Ch ENABLEctrl1 enable_ctrl_sd3<7:6> enable_c trl_sd2<5:4> enable_ctrl_sd1<3:2> enable_ctrl_sd0<1:0> 3Dh ENABLEctrl2 - enable_ctrl_sd6<5:4> enable_ctrl_sd5<3:2> enable_ctrl_sd4<1:0> 3Eh ENABLEctrl3 enable_ctrl_ldo3<7:6> enable_ctrl_ldo2<5:4> enable_ctrl_ldo1<3:2> enable_ctrl_ldo0<1:0> 3Fh ENABLEctrl4 enable_ctrl_ldo7<7:6> enable_ctrl_ldo6<5:4> enable_ctrl_ldo5<3:2> enable_ctrl_ldo4<1:0> 40h ENABLEctrl5 enable_ctrl_ldo11<7:6> enable_ctrl_ldo10<5:4 > enable_ctrl_ldo9<3:2> - 41h pwm_control_l pwm_l_time<7:0> 42h pwm_control_h pwm_h_time<7:0> 46h Watchdog_timer - wtdg_timer<6:0> 48h WatchdogSoftwareSig nal pwm_div<7:6> - wtdg_sw_sig

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description 49h IOVoltage - INT_pull up I2C_bus_p ullup - level33 4Ah Battery_voltage_monit or2 - vsup_min<4:2> ncells<1:0> 4Dh SDcontrol - sd6_enabl e sd5_ena ble sd4_enabl e sd3_en able sd2_enable sd1_enable sd0_enable 4Eh LDOcontrol0 ldo7_enable ldo6_ena ble ldo5_en able ldo4_enab le ldo3_e nable ldo2_enable ldo1_enable ldo0_enable 4Fh LDOcontrol1 - ldo11_ enable ldo10_enable ldo9_enable - 50h SD0_protect - sd0_vmax<4:0> 51h SD6_protect - sd6_vmax<4:0> 52h PWM_vcontrol1 vpwm1_step vpwm1_o n vpwm1_vbase<5:0> 53h PWM_vcontrol2 vpwm2_step vpwm2_o n vpwm2_vbase<5:0> 54h PWM_vcontrol3 vpwm1_reset<7:6> vpwm1_value<5:0> 55h PWM_vcontrol4 vpwm2_reset<7:6> vpwm2_value<5:0> 57h BBcharger BBCActive BBCPwrSa ve BBCVolt BBCCur<4:3> BBCResOff BBCMode<1:0> 58h CTRLsequ1 enable3_inv onkey_no debounce enable1 _stby_e n enable1_in v enable 2_inv therm_inv lid_pwr_on ac_ok_pwr_on 59h CTRLsequ2 lid_invert ac_ok_inv ert on_shutdown_delay<5:3> onkey_invert on_shutdown_delay<1:0> 5Ah OVcurrent - sd1_ilimit<6:5> sd0_ilimit <4:3> sd0_ovc_alarm<2:0>

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description 5Bh OVcurrent_deb - sd6_ilimit<4:3> - sd06_ovc_alarm_deb<1:0> 5Dh OC_pg_ctrl pg_vresfall_mask pg_ovcurr _sd0_mas k pg_pwr good_sd 0_mask pg_gpio5_ mask pg_gpi o4_mas k pg_gpio3_mask pg_ac_ok_mask pg_ac_ok_inv 5Eh OC_pg_ctrl2 pg_ovcurr_sd6_ mask pg_pwrgo od_sd6_ mask pg_sd6_ovc_alarm<5:3 >p g _ v m a s k _ t i m e < 2 : 1 > - 5Fh CTRLstatus sd0_pwr_ok enable3 enable2 enable1 ov_curr therm lid ac_ok 60h RTCcontrol am_pm_mode - clk32out _en rtc_irq_mode<4:3> rtc_on rtc_alarm_wakeup_e n rtc_rep_wakeup_en 61h RTCsecond - second1<6:4> second0<3:0> 62h RTCminute - minute1<6:4> minute0<3:0> 63h RTChour pm - hour1<5:4> hour0<3:0> 64h RTCday - day1<5:4> day0<3:0> 65h RTCmonth - month1 month0<3:0> 66h RTCyear - year1<6:4> year0<3:0> 67h RTCAlarmSecond - Alarmsecond1<6:4> Alarmsecond0<3:0> 68h RTCAlarmMinute - Alarmminute1<6:4> Alarmminute0<3:0> 69h RTCAlarmHour Alarmpm - Alarmhour1<5:4> Alarmhour0<3:0> 6Ah RTCAlarmday - Alarmday1<5:4> Alarmday0<3:0> 6Bh RTCAlarmmonth - Alarmmon th1 Alarmmonth0<3:0>

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description 6Ch RTCAlarmyear - Alarmyear1<6:4> Alarmyear0<3:0> 6Dh SRAM SRAM<7:0> 6Fh RTC_Access rtc_write_ena - 73h RegStatus - sd6_lv sd5_lv sd4_lv sd3_lv sd2_lv sd1_lv sd0_lv 74h InterruptMask1 LowBat_int_m ovtmp_in t_m onkey_i nt_m onkey_lpre ss_int_m occur_a larm_s d0_int_ m enable1_int_m acok_int_m lid_int_m 75h InterruptMask2 rtc_rep_int_m sd6_lv_int enable2 _int_m PWM2_ov prot_int_ m PWM1_ ovprot_ int_m sd2345_lv_int_ 76h InterruptMask3 enable3_int_m wtdg_int_ m gpio5_in t_m gpio4_int_ m gpio3_i nt_m gpio2_int_m gpio1_int_m rtc_alarm_int_m 77h InterruptMask4 adc_int_m occur_ala rm_sd6_i nt_m temp_sd 6_alarm _int_m temp_sd1_ alarm_int_ m temp_s d0_alar m_int_ m temp_sd6_shut down_int_m temp_sd1_shutdown _int_m temp_sd0_shutdown _int_m 78h InterruptStatus1 LowBat_int_i ovtmp_in t_i onkey_i nt_i onkey_lpre ss_int_i occur_a larm_s d0_int_ i enable1_int_i acok_int_i lid_int_i 79h InterruptStatus2 rtc_rep_int_i sd6_lv_int enable2 _int_i PWM2_ov prot_int_i PWM1_ ovprot_ int_i 7Ah InterruptStatus3 enable3_int_i wtdg_int_ i gpio5_in t_i gpio4_int_ i gpio3_i nt_i gpio2_int_i gpio1_int_i rtc_alarm_int_i 7Bh InterruptStatus4 adc_int_i occur_ala rm_sd6_i nt_i temp_sd 6_alarm _int_i temp_sd1_ alarm_int_ i temp_s d0_alar m_int_i temp_sd6_shut down_int_i temp_sd1_shutdown _int_i temp_sd0_shutdown _int_i

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description 7Dh Temp_Status - temp_sd6 _alarm temp_sd 1_alarm temp_sd0_ alarm mask_o vtemp temp_sd6_shut down temp_sd1_shutdown temp_sd0_shutdown 80h ADC0_control adc0_start_conv ersion - adc0_gp io_lv adc0_select<4:0> 81h ADC1_control adc1_start_conv ersion adc1_inte rval_scan adc1_gp io_lv adc1_select<4:0> 82h ADC0_MSB_result adc0_result_not_ ready adc0_D[9:3]<6:0> 83h ADC0_LSB_result - adc0_D[2:0]<2:0> 84h ADC1_MSB_result adc1_result_not_ ready adc1_D[9:3]<6:0> 85h ADC1_LSB_result - adc1_D[2:0]<2:0> 86h ADC1_threshold_hi_ MSB - adc1_threshold_hi[9:3]<6:0> 87h ADC1_threshold_hi_ LSB - adc1_threshold_hi[2:0]<2:0> 88h ADC1_threshold_lo_ MSB - adc1_threshold_lo[9:3]<6:0> 89h ADC1_threshold_lo_ LSB - adc1_threshold_lo[2:0]<2:0> 8Ah ADC_configuration - adc_buf_on adc1_interrupt_mod e adc1_interval_time 90h ASIC_ID1 ID1<7:0> 91h ASIC_ID2 - revision<3:0> 9Eh LockRegister - reg_lock<1:0>

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description A7h Fuse7 sd5_slave sd4_slave sd3_slav e sd0_v_minus_200mV -- A8h Fuse8 - sd2_hcurr _tr ldo3_vtrack_tr<5:4> sd5_fas t sd4_fast sd3_fast sd2_fast A9h Fuse9 auto_off em_shutd own_dire ct res_timer<5:4> ResVoltRise<3:1> - AAh Fuse10 unique_id power_off _at_vsupl ow i2c_deva _bit1 rtc_on lid_pwr _on ac_ok_pwr_on del_time sequ_on Abh Fuse11 onkey_lpress_res et onkey_shutdown_del ay<6:5> ac_ok_inv ert onkey_i nvert SupResEn gpio12_in_en lid_invert Ach Fuse12 sdmph_clk_div<7:6> wtdg_mode<5:4> wtdg_o n enable3_inv enable2_inv therm_inv Adh

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Aeh Afh Fuse15 rtc_lock - I2C_bus _pullup vsup_min<4:2> ncells<1:0> B0h Fuse16 Reg3_delay Reg3_sele ct_MSB Reg2_de lay Reg2_sele ct_MSB Reg1_d elay Reg1_select_M SB Reg0_delay Reg0_select_MSB B1h Fuse17 Reg1_select_LSB<7:4> Reg0_select_LSB<3:0> B2h Fuse18 reg0_v<7:0> B3h Fuse19 reg1_v<7:0> B4h Fuse20 Reg3_select_LSB<7:4> Reg2_select_LSB<3:0> B5h Fuse21 reg2_v<7:0> B6h Fuse22 reg3_v<7:0>

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description B7h Fuse23 Reg7_delay Reg7_sele ct_MSB Reg6_del ay Reg6_selec t_MSB Reg5_d elay Reg5_select_MS B Reg4_delay Reg4_select_MSB B8h Fuse24 Reg5_select_LSB<7:4> Reg4_select_LSB<3:0> B9h Fuse25 reg4_v<7:0> Bah Fuse26 reg5_v<7:0> BBh Fuse27 Reg7_select_LSB<7:4> Reg6_select_LSB<3:0> BCh Fuse28 reg6_v<7:0> BDh Fuse29 reg7_v<7:0> Beh Fuse30 Reg11_delay Reg11_sel ect_MSB Reg10_d elay Reg10_sele ct_MSB Reg9_d elay Reg9_select_MS B Reg8_delay Reg8_select_MSB BFh Fuse31 Reg9_select_LSB<7:4> Reg8_select_LSB<3:0>

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description C0h Fuse32 reg8_v<7:0> C1h Fuse33 reg9_v<7:0> C2h Fuse34 Reg11_select_LSB<7:4> Reg10_select_LSB<3:0> C3h Fuse35 reg10_v<7:0> C4h Fuse36 reg11_v<7:0> C5h Fuse37 Reg15_delay Reg15_sel ect_MSB Reg14_d elay Reg14_sele ct_MSB Reg13_ delay Reg13_select_M SB Reg12_delay Reg12_select_MSB C6h Fuse38 Reg13_select_LSB<7:4> Reg12_select_LSB<3:0> C7h Fuse39 reg12_v<7:0> C8h Fuse40 reg13_v<7:0> C9h Fuse41 Reg15_select_LSB<7:4> Reg14_select_LSB<3:0>

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Cah Fuse42_uniqueID0 reg14_v<7:0> CBh Fuse43_uniqueID1 reg15_v<7:0> CCh Fuse44_uniqueID2 ASIC_ID3 Reg17_ delay Reg17_select_ MSB Reg16_delay Reg16_select_MSB CDh Fuse45_uniqueID3 Reg17_select_LSB<7:4> Reg16_select_LSB<3:0> Ceh Fuse46_uniqueID4 reg16_v<7:0> CFh Fuse47_uniqueID5 reg17_v<7:0> E0h Reg0_control - delay_tim e_stby Reg0_de lay_stby Reg0_select_stby<4:0> E1h Reg1_control - Reg1_de lay_stby Reg1_select_stby<4:0> E2h Reg2_control - Reg2_del ay_stby Reg2_select_stby<4:0> E3h Reg3_control - Reg3_del ay_stby Reg3_select_stby<4:0> E4h Reg4_control - Reg4_del ay_stby Reg4_select_stby<4:0>

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Register Overview: Shows all the available registers. E5h Reg5_control - Reg5_del ay_stby Reg5_select_stby<4:0> E6h Reg6_control - Reg6_del ay_stby Reg6_select_stby<4:0> E7h Reg7_control - Reg7_del ay_stby Reg7_select_stby<4:0> E8h Reg8_control - Reg8_del ay_stby Reg8_select_stby<4:0> E9h Reg9_control - Reg9_del ay_stby Reg9_select_stby<4:0> Eah Reg0_Voltage Reg0_voltage_stby <7:0> Ebh Reg1_Voltage Reg1_voltage_stby <7:0> Ech Reg2_Voltage Reg2_ voltage_stby<7:0> Edh Reg3_Voltage Reg3_ voltage_stby<7:0> Eeh Reg4_Voltage Reg4_ voltage_stby<7:0> Efh Reg5_Voltage Reg5_ voltage_stby<7:0> F0h Reg6_Voltage Reg6_ voltage_stby<7:0> F1h Reg7_Voltage Reg7_ voltage_stby<7:0> F2h Reg8_Voltage Reg8_ voltage_stby<7:0> F3h Reg9_Voltage Reg9_ voltage_stby<7:0> F4h SpareRegister1 disable_stby_lid_int

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 95: GPIO0control Addr:08h GPIO0control Bit Bit Name Default Access Bit Description 7g p i o 0 _ i n v e r t 0 R W Invert GPIO input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio0_iosf 0 RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC 2:0 gpio0_mode 3 RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 96: GPIO1control Addr:09h GPIO1control Bit Bit Name Default Access Bit Description 7g p i o 1 _ i n v e r t 0 R W Invert GPIO input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio1_iosf 0 RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC 2:0 gpio1_mode 3 RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 97: GPIO2control Addr:0ah GPIO2control Bit Bit Name Default Access Bit Description 7g p i o 2 _ i n v e r t 0 R W Invert GPIO input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio2_iosf 0 RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC 2:0 gpio2_mode 3 RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 98: GPIO3control Addr:0bh GPIO3control Bit Bit Name Default Access Bit Description 7g p i o 3 _ i n v e r t 0 R W Invert GPIO input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio3_iosf 0 RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC 2:0 gpio3_mode 3 RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 99: GPIO4control Addr:0ch GPIO4control Bit Bit Name Default Access Bit Description 7g p i o 4 _ i n v e r t 0 R W Invert GPIO input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio4_iosf 0 RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC 2:0 gpio4_mode 3 RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 100: GPIO5control Addr:0dh GPIO5control Bit Bit Name Default Access Bit Description 7g p i o 5 _ i n v e r t 0 R W Invert GPIO input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio5_iosf 0 RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC 2:0 gpio5_mode 3 RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 101: GPIO6control Addr:0eh GPIO6control Bit Bit Name Default Access Bit Description 7g p i o 6 _ i n v e r t 0 R W Invert GPIO input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio6_iosf 0 RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC 2:0 gpio6_mode 3 RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 102: GPIO7control Addr:0fh GPIO7control Bit Bit Name Default Access Bit Description 7g p i o 7 _ i n v e r t 0 R W Invert GPIO input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio7_iosf 0 RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC 2:0 gpio7_mode 3 RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 120: Reg_sequ_mod2 4s d 4 _ s e q u _ o n 0 R W _ S S Step down 4 controlled by sequencer for ramping down (reset or power_off ) 3s d 3 _ s e q u _ o n 0 R W _ S S Step down 3 controlled by sequencer for ramping down (reset or power_off ) 2s d 2 _ s e q u _ o n 0 R W _ S S Step down 2 controlled by sequencer for ramping down (reset or power_off ) 1s d 1 _ s e q u _ o n 0 R W _ S S Step down 1 controlled by sequencer for ramping down (reset or power_off ) 0s d 0 _ s e q u _ o n 0 R W _ S S Step down 0 controlled by sequencer for ramping down (reset or power_off ) Addr:23h Reg_sequ_mod2 Bit Bit Name Default Access Bit Description 7 ldo7_sequ_on 0 RW_SS LDO8 controlled by sequencer for ramping down (reset or power_off ) 6 ldo6_sequ_on 0 RW_SS LDO7 controlled by sequencer for ramping down (reset or power_off ) 5 ldo5_sequ_on 0 RW_SS LDO6 controlled by sequencer for ramping down (reset or power_off ) 4 ldo4_sequ_on 0 RW_SS LDO5 controlled by sequencer for ramping down (reset or power_off ) 3 ldo3_sequ_on 0 RW_SS LDO4 controlled by sequencer for ramping down (reset or power_off ) 2 ldo2_sequ_on 0 RW_SS LDO3 controlled by sequencer for ramping down (reset or power_off ) 1 ldo1_sequ_on 0 RW_SS LDO2 controlled by sequencer for ramping down (reset or power_off ) 0 ldo0_sequ_on 0 RW_SS LDO1 controlled by sequencer for ramping down (reset or power_off ) Addr:22h Reg_sequ_mod1 Bit Bit Name Default Access Bit Description

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 123: SD_phsw_status Addr:28h SD_phsw_status Bit Bit Name Default Access Bit Description 7:6 sdmph_clk_div 0 RW_SM Divide clock of sd0,sd1,sd6 by 1,2 or 4 0 : 2.7MHz 1 : 1.35MHz 2 : 0.675MHz 3 : 0.675MHz 4 sd6_nph_auto 0 R Status of the actual number of phases used ,if phase switching enabled 0 : 1 phase 1 : 2 phases 3 sd1_nph_auto 0 R Status of the actual number of phases used ,if phase switching enabled 0 : 1 phase 1 : 2 phases 2:0 sd0_nph_auto 0 R Status of the actual number of phases used ,if phase switching enabled 0 : 1 phase 1 : 2 phases 2 : 3 phases 3 : 4 phases 4 : NA 5 : 6 phases 6 : NA 7 : 8 phases

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 124: SD0_control Addr:29h SD0_control Bit Bit Name Default Access Bit Description 7:6 sd0_trim_gm 0 RW_SM Selects gm setting of OTA 0 : fast setting 1 : slow setting 2 : medium setting 3 : very slow setting 5 sd0_force_pwm 0 RW Selects force pwm mode 0 : normal mode 1 : force pwm, inverted coil current possible to keep the fixed frequency 4s d 0 _ f a s t 0R W Selects a faster regulation mode for SD0 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required 3 sd0_combine_phase 0 RW_SM Selects phase mode (set during startup power_stage test) 0 : normal mode 1 : combine phase 1 and 2 , 3 and 4, 5 and 6, 7 and 8 2:0 sd0_phases 0 RW_SM Selects number of phases for sd0 (set during startup power_stage test, can be changed after that) 0 : 1 phases used 1 : 2 phases used 2 : 3 phases used 3 : 4 phases used 4 : 5 phases used 5 : 6 phases used 6 : 7 phases used 7 : 8 phases used

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 125: SD1_control Addr:2ah SD1_control Bit Bit Name Default Access Bit Description 7:6 sd1_trim_gm 0 RW_SM Selects gm setting of OTA 0 : fast setting 1 : slow setting 2 : medium setting 3 : very slow setting 5 sd1_force_pwm 0 RW Selects force pwm mode 0 : normal mode 1 : force pwm, inverted coil current possible to keep the fixed frequency 4s d 1 _ f a s t 0R W Selects a faster regulation mode for SD1 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required 3 sd1_combine_phase 0 RW_SM Selects phase mode (set during startup power_stage test) 0 : normal mode 1 : combine phase 1 and 2 2 sd0_low_noise 0 RW Enables low noise mode of SD0. If enabled smaller current pulses and output ripple are activated 0 : Normal mode. Minimum current pulses of about 10% the current limit are applied in skip mode 1 : Low noise mode. Only minimum on time applied in skip mode 1 sd1_low_noise 0 RW Enables low noise mode of SD1. If enabled smaller current pulses and output ripple is activated 0 : Normal mode. Minimum current pulses of about 10% the current limit are applied in skip mode 1 : Low noise mode. Only minimum on time applied in skip mode 0 sd1_phases 1 RW_SM Selects number of phases for sd1 (set during startup power_stage test, can be changed after that) 0 : 1 phase used 1 : 2 phases used

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 126: SDmph_control Addr:2bh SDmph_control Bit Bit Name Default Access Bit Description 7 disable_sd0_pulld 0 RW Disable Regulator SD0 pull-down 0 : normal mode (pull-down if SD0 is disabled) 1 : pull-down disabled (only if sd0 controlled by enable1/2/3 in active (ON) state) 5:4 sd6_startslew 0 RW Sets the startup slew rate of SD6 0 : 5mV / us 1 : 10mV / us 2 : 20mV / us 3 : 40mV / us 3:2 sd1_startslew 0 RW Sets the startup slew rate of SD1 0 : 5mV / us 1 : 10mV / us 2 : 20mV / us 3 : 40mV / us 1:0 sd0_startslew 0 RW Sets the startup slew rate of SD0 0 : 5mV / us 1 : 10mV / us 2 : 20mV / us 3 : 40mV / us

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 127: SD23_control Addr:2ch SD23_control Bit Bit Name Default Access Bit Description 6 sd3_fast 0 RW_SS Selects a faster regulation mode for SD3 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required 5 sd3_force_pwm 0 RW Selects force pwm mode 0 : normal mode 1 : force pwm, inverted coil current possible to keep the fixed frequency 4 sd3_low_noise 0 RW Enables low noise mode of SD3. If enabled smaller current pulses and output ripple is activated 0 : Normal mode. Minimum current pulses of about 10% the current limit are applied in skip mode 1 : Low noise mode. Only minimum on time applied in skip mode 2 sd2_fast 0 RW_SS Selects a faster regulation mode for SD2 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required 1 sd2_force_pwm 0 RW Selects force pwm mode 0 : normal mode 1 : force pwm, inverted coil current possible to keep the fixed frequency 0 sd2_low_noise 0 RW Enables low noise mode of SD2. If enabled smaller current pulses and output ripple is activated 0 : Normal mode. Minimum current pulses of about 10% the current limit are applied in skip mode 1 : Low noise mode. Only minimum on time applied in skip mode

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 130: SD6_control Addr:2fh SD6_control Bit Bit Name Default Access Bit Description 7:6 sd6_trim_gm 0 RW_SM Selects gm setting of OTA 0 : fast setting 1 : slow setting 2 : medium setting 3 : very slow setting 5 sd6_force_pwm 0 RW Selects force pwm mode 0 : normal mode 1 : force pwm, inverted coil current possible to keep the fixed frequency 4s d 6 _ f a s t 0 R W Selects a faster regulation mode for SD6 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required 3 sd6_combine_phas e 0R W _ S M Selects phase mode (set during startup subdie test) 0 : normal mode 1 : combine phase 1 and 2 2 sd6_ph2c_on 0 RW_SM Selects high current mode of SD6 (doubled current) (set during startup subdie test) 0 : normal mode (only one supdie connected) 1 : second subdie on pin TEMP2_SD6 detected (short CTRL1 and CTRL2 of each subdie and connect to CTRL1_SD6 and CTRL2_SD6) 1 sd6_low_noise 0 RW Enables low noise mode of SD6. If enabled smaller current pulses and output ripple is activated 0 : Normal mode. Minimum current pulses of about 100f the current limit are applied in skip mode 1 : Low noise mode. Only minimum on time applied in skip mode 0 sd6_phases 1 RW_SM Selects number of phases for SD6 (set during startup subdie test, can be changed after that) 0 : 1 phase used 1 : 2 phases used

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 131: SD_dvm Addr:30h SD_dvm Bit Bit Name Default Access Bit Description 5:4 dvm_time_sd6 0 RW Time steps of DVM voltage change of selected step down If voltage of step Down is changed during operation (sdx_vsel) voltage is de/increased 0 : immediate change (no DVM) 1 : 40mV/us 2 : 10mV/us 3 : 5mV/us 3:2 dvm_time_sd1 0 RW Time steps of DVM voltage change of selected step down If voltage of step Down is changed during operation (sdx_vsel) voltage is de/increased 0 : immediate change (no DVM) 1 : 40mV/us 2 : 10mV/us 3 : 5mV/us 1:0 dvm_time_sd0 0 RW Time steps of DVM voltage change of selected step down If voltage of step Down is changed during operation (sdx_vsel) voltage is de/increased 0 : immediate change (no DVM) 1 : 40mV/us 2 : 10mV/us 3 : 5mV/us

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 132: Resetreason Addr:31h Resetreason Bit Bit Name Default Access Bit Description 7:4 reset_reason 0 RW_SM This flag indicates the exit of active mode reason 0 : VPOR has been reached (battery or supply insertion from scratch) 1 : ResVoltFall reached by VBAT or vsup_min reached by VSUP 2 : Software forced by force_reset (soft or hard) 3 : Software forced by power_off 4 : ONKEY longpress has been detected 5 : XRES_IN pin 6 : THERM pin 7 : overtemperature T140 (die, SD0, SD1, or SD6) 8 : watchdog 9 : VSUP overvoltage reached 10 : Transition to standby mode 3:0 startup_reason 0 RW_SM This flag indicates the startup reason after power off 0 : VPOR has been reached (battery or supply insertion from scratch) 1 : ONKEY has been pulled high in power off mode 2 : AC_OK has been detected in power off mode 3 : LID has been detected in power off mode 4 : RTC wakeup has been detected in power off mode 5 : Interrupt in standby mode has been detected 6 : Reset cycle 7 : Soft reset cycle 8 : ResVoltRise was reached

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 133: Battery_voltage_monitor Addr:32h Battery_voltage_monitor Bit Bit Name Default Access Bit Description 7F a s t R e s E n 0 R W 0 : ResVoltFall debounce time = 4 ms 1 : ResVoltFall debounce time = 4 us 6S u p R e s E n 0 R W _ S S 0 : A reset is generated if VBAT or VSUP falls below 2.5V. If VBAT falls below ResVoltFall only an interrupt is generated (if enabled) and the uProcessor can shut down the system) 1 : A reset is generated if VBAT falls below ResVoltFall or VSUP falls below vsup_min 5:3 ResVoltFall 0 RW_SM This value determines the reset level ResVoltFall for falling VBAT. For stacked battery systems (ncells>0) the level gets multiplied with the number of cells. It is recommended to set this value at least 200mV lower than ResVoltRise 0 : 2.5V * (ncells+1) 1 : 2.7V * (ncells+1) 2 : 2.95V * (ncells+1) 3 : 3.1V * (ncells+1) 4 : 3.2V * (ncells+1) 5 : 3.3V * (ncells+1) 6 : 3.4V * (ncells+1) 7 : 3.6V * (ncells+1) 2:0 ResVoltRise 0 RW_SM This value determines the reset level ResVoltRise for rising VBAT. For stacked battery systems (ncells>0) the level gets multiplied with the number of cells. It is recommended to set this value at least 200mV higher than ResVoltFall 0 : 2.5V * (ncells+1) 1 : 2.7V * (ncells+1) 2 : 2.95V * (ncells+1) 3 : 3.1V * (ncells+1) 4 : 3.2V * (ncells+1) 5 : 3.3V * (ncells+1) 6 : 3.4V * (ncells+1) 7 : 3.6V * (ncells+1)

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 134: Startup_Control Addr:33h Startup_Control Bit Bit Name Default Access Bit Description 3 onkey_lpress_reset 0 RW_SS Selects behavior on onkey_lpress 0 : change to power_off mode on long press 1 : apply reset on long press 2 lid_rising_en 0 RW Select LID detection in power off mode Read write 0 : Exit of Power Off mode, if LID is detected (level detection) 1 : Exit of Power Off mode, if LID active is detected (rising edge detection after possible inversion) 1 ac_ok_rising_en 0 RW Select AC_OK detection in power off mode Read Write 0 : Exit of Power Off mode, if AC_OK is detected (level detection) 1 : Exit of Power Off mode, if AC_OK active is detected (rising edge detection after possible inversion) 0 power_off_at_vsuplow 0 RW_SS Switch on Power_Off mode if low VBAT/VSUP is detected during Active or Standby mode (pin ONKEY=low and bit auto_off=0) 0 : If low VBAT/VSUP is detected, continuously monitor battery voltage and startup if battery voltage is above ResVoltRise 1 : If low VBAT/VSUP is detected, enter Power_Off mode

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 137: ResetControl 3:1 clk_int 0 RW_SM Sets the internal CLK frequency fCLK used for Stepdowns, PWM, ... 0 : 4 MHz (default) 1 : 3.8 MHz 2 : 3.6 MHz 3 : 3.4 MHz 4 : 3.2 MHz 5 : 3.0 MHz 6 : 2.8 MHz 7 : 2.6 MHz All frequencies, timings and delays in this datasheet are based on 4MHz clk_int 0 low_power_on 0 RW_SM Enable low power mode of internal reference. 0 : Standard mode 1 : Low power mode - all specification except noise parameters are still valid. Iq reduced by approx. 45uA Addr:36h ResetControl Bit Bit Name Default Access Bit Description 4:3 reset_debounce 0 RW Sets debounce time for RESET_IN 0 : 0.1 ms 1 : 4 ms 2 : 8 ms 3 : 16 ms 2 onkey_input 0 R_PUSH READ : This flag represents the state of the ONkey pad directly WRITE : Setting to 1 resets the 2/4/8 sec. Onkey reset timer 1p o w e r _ o f f 0 R W _ S M Setting to 1 starts a reset cycle, and puts the PMIC into Power_off state 0 force_reset 0 RW Setting to 1 starts a complete reset cycle Addr:35h ReferenceControl Bit Bit Name Default Access Bit Description

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 146: ENABLEctrl4 1:0 enable_ctrl_ldo0 0 RW Enable control of ldo0. only enabled, if ldo0_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 Addr:3fh ENABLEctrl4 Bit Bit Name Default Access Bit Description 7:6 enable_ctrl_ldo7 0 RW Enable control of ldo7. only enabled, if ldo7_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 5:4 enable_ctrl_ldo6 0 RW Enable control of ldo6. only enabled, if ldo6_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 3:2 enable_ctrl_ldo5 0 RW Enable control of ldo5. only enabled, if ldo5_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 1:0 enable_ctrl_ldo4 0 RW Enable control of ldo4. only enabled, if ldo4_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 Addr:3eh ENABLEctrl3 Bit Bit Name Default Access Bit Description

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 152: IOVoltage Figure 153: Battery_voltage_monitor2 Addr:49h IOVoltage Bit Bit Name Default Access Bit Description 0 level33 0 RW Voltage level of input signals 0 : IO voltage 1.8 V 1 : IO voltage 3.3 V

4 I2C_bus_pullup 0 RW_SS

I2C data and CLK internal pull-ups enabled/disabled 0 : pull-ups disabled 1 : pull-ups enabled 5I N T _ p u l l u p _ d i s 0 R W Interrupt signal pull-up enabled/disabled on pin XINT 0 : pull-up enabled (open drain mode) 1 : pull-up disabled (push/pull mode)f Addr:4ah Battery_voltage_monitor2 Bit Bit Name Default Access Bit Description 1:0 ncells 0 RW_SM Selects number of cells that are connected to VBAT pin 4:2 vsup_min 0 RW_SM Defines minimum value on VSUP for startup/reset 0 : 2.55V 1 : 2.7V 2 : 3.0V 3 : 3.2V 4 : 4.5V 5 : 4.7V 6 : 4.8V

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 163: BBcharger Addr:57h BBcharger Bit Bit Name Default Access Bit Description

7 BBCActive 0 RO

Status of backup battery charger 0 : Charger is not active 1 : Charger charges backup battery

6 BBCPwrSave 1 RW

0 : Normal operation of the backup battery charger 1 : The backup battery charger checks if it is actually charging the battery (bit BBCActive=1) and it is disabled if it is not. Every 10s (every 64s in state Off ) the voltage of the backup battery is checked again to determine if charging is required. This practically reduces the current consumption to 0 if the backup battery is full.

5 BBCVolt 0 RW

This value determines the maximum charging voltage VBBC 0 : VBBC=2.5V 1 : VBBC=3.0V 4:3 BBCCur 0 RW This value determines the charge current IBBC 0 : IBBC=50uA 1 : IBBC=100uA 2 : IBBC=200uA 3 : IBBC=400uA 2B B C R e s O f f 0 R W 0 : Enable output resistor 1 : Bypass output resistor 1:0 BBCMode 0 RW Enable and disable backup battery charger. Activation in PowerOff and standby mode requires 32kHz OSC to be enabled (rtc_on=1). 0 : Backup battery charger is disabled 1 : Backup battery charger is enabled in state Active mode 2 : Backup battery charger is enabled in states Active mode and Standby mode 3 : Backup battery charger is enabled in states PowerOff mode, Active mode and Standby mode

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 164: CTRLsequ1 Addr:58h CTRLsequ1 Bit Bit Name Default Access Bit Description 0 ac_ok_pwr_on 0 RW_SS Enables exit out of PWR OFF mode with pin AC_OK (pin enabled in PWR off mode) 0 : AC_OK disabled 1 : AC_OK enabled 1 lid_pwr_on 0 RW_SS Enables exit out of PWR OFF mode with pin LID (pin enabled in PWR off mode) 0 : LID disabled 1 : LID enabled 2t h e r m _ i n v 0 R W _ S S Sets the polarity of the THERM pin 0 : High active for THERM event 1 : Inverted: Low active for THERM event 3e n a b l e 2 _ i n v 0 R W _ S S Sets the polarity of the ENABLE2 pin 0 : High active for ENALBE2 1 : Inverted: Low active for ENABLE2 4 enable1_inv 0 RW Sets the polarity of the ENABLE1 pin 0 : High active for ENABLE1 1 : Inverted: Low active for ENABLE1 5 enable1_deepsleep 0 RW ENABLE1 signal enable for controlling deepsleep/stand_by 0 : ENABLE1 signal not used for stand_by entry/exit 1 : ENABLE1 signal used for stand_by entry/exit 6 onkey_nodebounce 0 RW Sets the debounce on ONKEY 0 : debounce on 1 : debounce off 7e n a b l e 3 _ i n v 0 R W _ S S Sets the polarity of the ENABLE3 pin 0 : High active for ENABLE3 1 : Inverted: Low active for ENABLE3

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 165: CTRLsequ2 Addr:59h CTRLsequ2 Bit Bit Name Default Access Bit Description 1:0 on_shutdown_delay 0 RW_SM Sets the ONKEY shutdown delay time. After timer expired onkey_lpress_i interrupt status bit is set and one additional second wait is added before shutdown is initiated. If interrupt status register is read out during that second, the delay timer is reset, and no shutdown is done. 0 : disabled 1 : 2 sec 2 : 4 sec 3 : 8 sec 2 onkey_invert 0 RW_SS Sets the polarity of the ONKEY pin 0 : High active for ONKEY 1 : Inverted: Low active for ONKEY 5:3 on_shutdown_delay_cnt 0 R On-reset delay counter in seconds. Starts with 0sec when onkey is pressed. 6 ac_ok_invert 0 RW_SS Sets the polarity of the AC_OK pin 0 : High active for AC_OK 1 : Inverted: Low active for AC_OK 7 lid_invert 0 RW_SS Sets the polarity of the LID pin 0 : High active for LID 1 : Inverted: Low active for LID

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 172: RTCcontrol 5e n a b l e 2 0 R O Status of enable2 signal (enable2 XOR enable2_inv) 6e n a b l e 3 0 R O Status of enable3 signal (enable3 XOR enable3_inv) 7 sd0_pwr_ok 0 RO Status of sd0_pwrgood Addr:60h RTCcontrol Bit Bit Name Default Access Bit Description 7 am_pm_mode 0 RW 12h/24h mode switch 0 : 24hour mode 1 : 12hour am/pm mode 5 clk32out_en 1 RW 0 : CLK32OUT pin disabled 1 : CLK32OUT pin enabled (push/pull to VDD_GPIO_lv) 4:3 rtc_irq_mode 0 RW 0 : generates an interrupt every second 1 : generates an interrupt every minute 2 : generates an interrupt every 2 minutes 3 : generates an interrupt every 8 minutes 2 rtc_on 0 RW_SM Switch on the 32kHz RTC oscillator 0 : 32kHz oscillator disabled 1 : 32kHz oscillator enabled 1 rtc_alarm_wakeup_en 0 RW 0 : Disables RTC alarm wakeup in power off mode 1 : Enable RTC alarm wakeup in power off mode 0 rtc_rep_wakeup_en 0 RW 0 : Disables RTC repeated wakeup in power off mode 1 : Enable RTC repeated wakeup in power off mode Addr:5fh CTRLstatus Bit Bit Name Default Access Bit Description

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 181: RTCAlarmHour Figure 182: RTCAlarmday Figure 183: RTCAlarmmonth Addr:69h RTCAlarmHour Bit Bit Name Default Access Bit Description 3:0 Alarmhour0 0 = Hours digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register 5:4 Alarmhour1 0 = 10-hours digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register

7 Alarmpm 0 =

AM/PM flag (only valid when am_pm_mode is 1, otherwise read returns 0) 0 : AM 1 : PM RTCAlarmyear has to be written to latch the whole alarm register Addr:6ah RTCAlarmday Bit Bit Name Default Access Bit Description 3:0 Alarmday0 Fh = Days digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register 5:4 Alarmday1 3h = 10-days digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register Addr:6bh RTCAlarmmonth Bit Bit Name Default Access Bit Description 3:0 Alarmmonth0 Fh = Months digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register

4 Alarmmonth1 1h =

10-months digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 187: RegStatus Addr:73h RegStatus Bit Bit Name Default Access Bit Description 6s d 6 _ l v 0 R O Bit is set when voltage of step down6 drops below low voltage threshold (-5%) (1ms debounce time default) 5s d 5 _ l v 0 R O Bit is set when voltage of step down5 drops below low voltage threshold (-5%) (1ms debounce time default) 4s d 4 _ l v 0 R O Bit is set when voltage of step down4 drops below low voltage threshold (-5%) (1ms debounce time default) 3s d 3 _ l v 0 R O Bit is set when voltage of step down3 drops below low voltage threshold (-5%) (1ms debounce time default) 2s d 2 _ l v 0 R O Bit is set when voltage of step down2 drops below low voltage threshold (-5%) (1ms debounce time default) 1s d 1 _ l v 0 R O Bit is set when voltage of step down1 drops below low voltage threshold (-5%) (1ms debounce time default) 0s d 0 _ l v 0 R O Bit is set when voltage of step down0 drops below low voltage threshold (-5%) (1ms debounce time default)

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 188: InterruptMask1 Addr:74h InterruptMask1 Bit Bit Name Default Access Bit Description 7L o w B a t _ i n t _ m 1 R W 0 : Interrupt enabled 1 : Interrupt masked (disabled) 6 ovtmp_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 5 onkey_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 4 onkey_lpress_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 3 occur_alarm_sd0_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 2 enable1_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 1 acok_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 0 lid_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled)

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 189: InterruptMask2 Addr:75h InterruptMask2 Bit Bit Name Default Access Bit Description 7 rtc_rep_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 6 sd6_lv_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 5 enable2_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled)

4 PWM2_ovprot_int_m 1 RW 0 : Interrupt enabled

1 : Interrupt masked (disabled)

3 PWM1_ovprot_int_m 1 RW 0 : Interrupt enabled

1 : Interrupt masked (disabled) 2 sd2345_lv_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 1 sd1_lv_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 0 sd0_lv_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled)

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 192: InterruptStatus1 6 occur_alarm_sd6_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 7 adc_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) Addr:78h InterruptStatus1 Bit Bit Name Default Access Bit Description

7 LowBat_int_i 0 SS_RC Bit is set when VSUP drops below vres_fall

6 ovtmp_int_i 0 SS_RC Bit is set when 110deg is exceeded on main or subdies 5 onkey_int_i 0 SS_RC Rising and falling edge 4 onkey_lpress_int_i 0 SS_RC Bit is set at ONkey longpress interrupt (rising edge) Reading out that register resets the ONkey longreset timer 3 occur_alarm_sd0_int_i 0 SS_RC Rising edge only 2 enable1_int_i 0 SS_RC Rising and falling edge 1 acok_int_i 0 SS_RC Rising and falling edge 0 lid_int_i 0 SS_RC Rising and falling edge Addr:77h InterruptMask4 Bit Bit Name Default Access Bit Description

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 193: InterruptStatus2 Figure 194: InterruptStatus3 Addr:79h InterruptStatus2 Bit Bit Name Default Access Bit Description 7 rtc_rep_int_i 0 SS_RC Rising edge only 6 sd6_lv_int_i 0 SS_RC Rising edge only 5 enable2_int_i 0 SS_RC Rising and falling edge

4 PWM2_ovprot_int_i 0 SS_RC

overvoltage protection reached with VPWM2 control

3 PWM1_ovprot_int_i 0 SS_RC

overvoltage protection reached with VPWM1 control 2 sd2345_lv_int_i 0 SS_RC Rising edge only low voltage of sd2,3,4 or 5 1 sd1_lv_int_i 0 SS_RC Rising edge only 0 sd0_lv_int_i 0 SS_RC Rising edge only Addr:7ah InterruptStatus3 Bit Bit Name Default Access Bit Description 7 enable3_int_i 0 SS_RC Rising and falling edge 6 wtdg_int_i 0 SS_RC Watchdog expired 5 gpio5_int_i 0 SS_RC Rising and falling edge 4 gpio4_int_i 0 SS_RC Rising and falling edge 3 gpio3_int_i 0 SS_RC Rising and falling edge 2 gpio2_int_i 0 SS_RC Rising and falling edge 1 gpio1_int_i 0 SS_RC Rising and falling edge 0 rtc_alarm_int_i 0 SS_RC Rising edge only

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 197: ADC0_control Addr:80h ADC0_control Bit Bit Name Default Access Bit Description 7 adc0_start_conversion 0 RW_SC Writing a 1 into this bit starts one ADC conversion. Self cleared at begin of ADC conversion 5a d c 0 _ g p i o _ l v 0 R W 0 : High voltage range of GPIO1,2,6,7, PWM_CLK2, PWM_DAT2 (4:1 divider active) 1 : Low voltage range of GPIO1,2,4,7, PWM_CLK2, PWM_DAT2 (1:1 divider, 1.6V max) 4:0 adc0_select 0 RW Selects an ADC channel 0 : Output Current SD0 1 : Output Current SD1 2 : Output Current SD6 3 : Temperature sensor:DIE temperature [C] = adc_result * 0.7698 - 274 (1:1) 4 : VSUP (4:1) 5 : GPIO1 (4:1 or 1:1 ) 6 : GPIO2 (4:1 or 1:1 ) 7 : GPIO3 (4:1 or 1:1 ) 8 : GPIO4 (4:1 or 1:1 ) 9 : GPIO6 (4:1 or 1:1 ) 10 : GPIO7 (4:1 or 1:1 ) 11 : VBAT (15:1) value valid below 15V only 12 : PWM_CLK2/ADC1 (4:1 or 1:1 ) 13 : PWM_DAT2/ADC2 (4:1 or 1:1 ) 14 : do not use 15 : do not use 16 : TEMP1_SD0: Tj = 326.5 – adc0_D[9:0] * 0.3734 (1:1) 17 : TEMP2_SD0: Tj = 326.5 - adc0_D[9:0] * 0.3734 (1:1) 18 : TEMP3_SD0: Tj = 326.5 - adc0_D[9:0] * 0.3734 (1:1) 19 : TEMP4_SD0: Tj = 326.5 - adc0_D[9:0] * 0.3734 (1:1) 20 : TEMP_SD1: Tj = 326.5 - adc0_D[9:0] * 0.3734 (1:1) 21 : TEMP1_SD6: Tj = 326.5 - adc0_D[9:0] * 0.3734 (1:1) 22 : TEMP2_SD6: Tj = 326.5 - adc0_D[9:0] * 0.3734 (1:1)

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 198: ADC1_control Addr:81h ADC1_control Bit Bit Name Default Access Bit Description 7 adc1_start_conversion 0 RW_SM Writing a 1 into this bit starts one ADC conversion. Self cleared at begin of ADC conversion 6a d c 1 _ i n t e r v a l _ s c a n 0 R W ADC conversion mode 0 : no interval conversion, single shot 1 : interval conversion, convert every 500/1000ms 5a d c 1 _ g p i o _ l v 0 R W 0 : High voltage range of GPIO1,2,6,7, PWM_CLK2, PWM_DAT2 (4:1 divider active) 1 : Low voltage range of GPIO1,2,4,7, PWM_CLK2, PWM_DAT2 (1:1 divider, 1.6V max) 4:0 adc1_select 0 RW Selects an ADC channel 0 : Output Current SD0 1 : Output Current SD1 2 : Output Current SD6 3 : Temperature sensor:DIE temperature [C] = adc_result * 0.7698 - 274 (1:1) 4 : VSUP (4:1) 5 : GPIO1 (4:1 or 1:1 ) 6 : GPIO2 (4:1 or 1:1 ) 7 : GPIO3 (4:1 or 1:1 ) 8 : GPIO4 (4:1 or 1:1 ) 9 : GPIO6 (4:1 or 1:1 ) 10 : GPIO7 (4:1 or 1:1 ) 11 : VBAT (15:1) value valid below 15V only 12 : PWM_CLK2/ADC1 (4:1 or 1:1 ) 13 : PWM_DAT2/ADC1 (4:1 or 1:1 ) 14 : do not use 15 : do not use 16 : TEMP1_SD0: Tj = 326.5 – adc1_D[9:0] * 0.3734 (1:1) 17 : TEMP2_SD0: Tj = 326.5 - adc1_D[9:0] * 0.3734 (1:1) 18 : TEMP3_SD0: Tj = 326.5 - adc1_D[9:0] * 0.3734 (1:1) 19 : TEMP4_SD0: Tj = 326.5 - adc1_D[9:0] * 0.3734 (1:1) 20 : TEMP_SD1: Tj = 326.5 - adc1_D[9:0] * 0.3734 (1:1) 21 : TEMP1_SD6: Tj = 326.5 - adc1_D[9:0] * 0.3734 (1:1) 22 : TEMP2_SD6: Tj = 326.5 - adc1_D[9:0] * 0.3734 (1:1)

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 210: Fuse7 Addr:a7h Fuse7 Bit Bit Name Default Access Bit Description 7s d 5 _ s l a v e 0 R W Enables slave mode of SD4 0 : Normal mode of SD5 1 : SD5 is slave of SD4 6s d 4 _ s l a v e 0 R W Enables slave mode of SD4 0 : Normal mode of SD4 1 : SD4 is slave of SD2 5s d 3 _ s l a v e 0 R W Enables slave mode of SD3 0 : Normal mode of SD3 1 : SD3 is slave of SD2. 4 sd0_v_minus_200mV 0 RW Enables low voltage mode of SD0 0 : Normal mode of SD0 Code starts with 0.61V 1 : Low voltage mode code starts with 0.41V (-0.2V Offset) 3 trim_gpio_pulld 0 RW Enables pulldown mode of GPIO1 and GPIO2 0 : Normal mode 1 : Pull down of GPIO1 and GPIO2 enabled 2:1 ldo10_tr 0 RW 0l d o 9 _ t r _ 1 0 R W

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 211: Fuse8 Addr:a8h Fuse8 Bit Bit Name Default Access Bit Description 6 sd2_hcurr_tr 0 RW Selects high current mode of SD2 5:4 ldo3_vtrack_tr 0 RW Selects offset for tracking mode 0 : no offset 1 : +10mV offset of LDO3 at 1.2V Vout (+0.83%) 2 : +20mV offset of LDO3 at 1.2V Vout (+1.66%) 3 : +30mV offset of LDO3 at 1.2V Vout (+2.5%) 3s d 5 _ f a s t 0 R W Selects a faster regulation mode for SD5 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required 2s d 4 _ f a s t 0 R W Selects a faster regulation mode for SD4 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required 1s d 3 _ f a s t 0 R W Selects a faster regulation mode for SD3 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required 0s d 2 _ f a s t 0 R W Selects a faster regulation mode for SD2 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 212: Fuse9 Addr:a9h Fuse9 Bit Bit Name Default Access Bit Description 7 auto_off 0 RW Defines startup behavior at first battery insertion or reset cycle 0 : Startup of chip if VBAT>ResVoltRise 1 : Enter power off mode (waiting for start-up event e.g. ONKEY) 6e m _ s h u t d o w n _ d i r e c t 0 R W Emergency shutdown 0 : use powerdown sequence 1 : direct (skip powerdown sequence) 5:4 res_timer 0 RW Set Reset Time, after the last regulator has started 0 : RESTIME = 0 ms 1 : RESTIME = 5 ms 2 : RESTIME = 11 ms 3 : RESTIME = 15 ms 3:1 ResVoltRise 0 RW This value determines the reset level ResVoltRise for rising VBAT. ResVoltFall is set to ResVoltRise - 2 steps by default 0 : 2.7V * (ncells+1) 1 : 2.95V * (ncells+1) 2 : 3.1V * (ncells+1) 3 : 3.2V * (ncells+1) 4 : 3.3V * (ncells+1) 5 : 3.4V * (ncells+1) 6 : 3.5V * (ncells+1) 7 : 3.6V * (ncells+1)

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 213: Fuse10 Addr:aah Fuse10 Bit Bit Name Default Access Bit Description 7u n i q u e _ i d 0 R W Enable/Disable unique ID If enabled, Fuse42..47 are used for UID and not for startup 6 power_off_at_vsuplow 0 RW Switch on Power_Off mode if low VBAT/VSUP is detected during Active or Standby mode (pin ONKEY=low and bit auto_off=0) 0 : If low VBAT/VSUP is detected, continuously monitor battery voltage and startup if battery voltage is above ResVoltRise 1 : If low VBAT/VSUP is detected, enter Power_Off mode 5 i2c_deva_bit1 0 RW Set to 0 4r t c _ o n 0 R W Switch on the 32kHz RTC oscillator 0 : 32kHz oscillator disabled 1 : 32kHz oscillator enabled. This will add 200 ms delay after POR to ensure proper operation. 3 lid_pwr_on 0 RW Enables exit out of PWR OFF mode with pin LID (pin enabled in PWR off mode) 0 : LID disabled 1 : LID enabled 2 ac_ok_pwr_on 0 RW Enables exit out of PWR OFF mode with pin AC_OK (pin enabled in PWR off mode) 0 : AC_OK disabled 1 : AC_OK enabled 1d e l _ t i m e 0 R W 0 : 1 ms delay time 1 : 4 ms delay time 0 sequ_on 0 RW Set to "1" to en able the start_up sequence

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 214: Fuse11 Addr:abh Fuse11 Bit Bit Name Default Access Bit Description 7 onkey_lpress_reset 0 RW Selects behavior on onkey_lpress 0 : change to power_off mode on long press 1 : apply reset on long press 6:5 onkey_shutdown_delay 0 RW Selects default state of the bit on_shutdown_delay 4a c _ o k _ i n v e r t 0 R W Sets the polarity of the AC_OK pin 0 : High active for AC_OK 1 : Inverted: Low active for AC_OK 3 onkey_invert 0 RW Sets the polarity of the ONKEY pin 0 : High active for ONKEY 1 : Inverted: Low active for ONKEY 2S u p R e s E n 0 R W 0 : A reset is generated if VBAT or VSUP falls below 2.5V. If VBAT falls below ResVoltFall only an interrupt is generated (if enabled) and the uProcessor can shut down the system) 1 : A reset is generated if VBAT falls below ResVoltFall or VSUP falls below vsup_min 1 gpio12_in_en 0 RW Don't use 0l i d _ i n v e r t 0 R W Sets the polarity of the LID pin 0 : High active for LID 1 : Inverted: Low active for LID

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 217: Fuse14 Addr:aeh Fuse14 Bit Bit Name Default Access Bit Description 7:3 sd6_vmax_1 0 RW Overvoltage protection for SD6 Output voltages are limited to vmax 0 : protection disabled 1 : 1 V 2 : 1.02 V 3 : 1.04 V .. : .. 25 : 1.48 V 26 : 1.50 V 2:0 sd0_vmax_1 0 RW Overvoltage protection for SD0 Output voltages are limited to vmax 0 : protection disabled 1 : 1 V 2 : 1.02 V 3 : 1.04 V .. : .. 25 : 1.48 V 26 : 1.50 V

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Register Description Figure 220: Fuse17 Figure 221: Fuse44_uniqueID2 Addr:b1h Fuse17 Bit Bit Name Default Access Bit Description 3:0 Reg0_select_LSB 0 RW Selects Regulator address for startup sequence(Slot0) Address 00..1f selectable (use 1Ch for unused timeslot) 00h : SD0 01h : SD1 .. : .. 06h : SD6 07h : n/a 08h : GPIO0 .. : .. 0Fh : GPIO7 10h : LDO0 .. : .. 1Bh : LDO11 1Ch : unused time slot 1Dh : LD03_settings 1Eh : GPIO_deb1 1Fh : GPIO_deb2 7:4 Reg1_select_LSB 0 RW Addr:cch Fuse44_uniqueID2 Bit Bit Name Default Access Bit Description

0 Reg16_select_MSB 0 RW

1R e g 1 6 _ d e l a y 0 R W

2 Reg17_select_MSB 0 RW

3R e g 1 7 _ d e l a y 0 R W 7:4 ASIC_ID3 0 RW Additional ASIC ID 0 : for die rev. 1v0,1v1,1v2 1 : for die rev. 1v21 (OC_PG function fixed)

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 222: Reg0_control Figure 223: Reg1_control Addr:e0h Reg0_control Bit Bit Name Default Access Bit Description 4:0 Reg0_select_stby 1Fh RW Selects regulator address for mapping; if Reg0_select_stby>=1Fh then timeslot is unused 00h : SD0 01h : SD1 .. : .. 06h : SD6 07h : n/a 08h : GPIO0 .. : .. 0Fh : GPIO7 10h : LDO0 .. : .. 1Bh : LDO11 1Ch : n/a 1Dh : LD03_settings 1Eh : GPIO_deb1 1Fh : timeslot unused 5R e g 0 _ d e l a y _ s t b y 0 R W Selects delay for standby entry after reg0_select is executed; selects delay for standby exit before reg0_select is executed 6 delay_time_stby 0 RW Selects delay time for standby entry/exit 0 : 1msec delay 1 : 4msec delay Addr:e1h Reg1_control Bit Bit Name Default Access Bit Description 4:0 Reg1_select_stby 1Fh RW Selects regulator for mapping; if Reg1_select_stby>=1Fh then timeslot is unused

5 Reg1_delay_stby 0 RW

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 226: SpareRegister1 Addr:f4h SpareRegister1 Bit Bit Name Default Access Bit Description 7 disable_stby_lid_int 0 RW_SM Selection, if LID interrupt is used to exit standby mode directly 0 : Exit stanby mode with LID interrupt 1 : Do not exit stanby mode with LID interrupt, if enable1_deepsleep=1 6 disable_stby_acok_int 0 RW_SM Selection, if ACOK interrupt is used to exit standby mode directly 0 : Exit stanby mode with AC_OK interrupt 1 : Do not exit stanby mode with AC_OK interrupt, if enable1_deepsleep=1 5 sparereg1 0 RW_SM 4:0 osc32k_trim 0 RW_SM Select internal load capacitor on XIN32K and XOUT32k 0h : 12 pF 1h : 12.5 pF 2h : 13 pF 3h : 13.5 pF 4h : 14 pF 5h : 14.5 pF 6h : 15 pF 7h : 15.5 pF .. : .. pF Eh : 19 pF Fh : 19.5 pF 10h : 4 pF 11h : 4.5 pF .. : .. pF 1E : 12 pF 1F : 12.5 pF

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Application Information Application Schematics Figure 227: Application Schematic 1/3 Application Schematic 1/3: Shows a basic application schematic for the internal DCDC/LDOs and system functions

Application Information

AS3722 Evalboard BGAA3 1.2 18.11.2013 0402 C21 0402 C27 0402 C25 0402 C13 0402 C31 0402 C32 0402 C33 0402 C34 0402 C35 0402 C36 0402 C37 0402 C40 0402 C39 0402 C41 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 L1 0.47u L2 0.47u L3 1u L4 1u 0603 C12 2u2 0603 C24 2u2 0603 C26 2u2 0805 C10 22u 0805 C22 22u 0805 C28 22u LDO11 LDO10 LDO9 LDO7 LDO6 LDO5 LDO4 LDO3 LDO2 LDO1 LDO0 FB5 FB4 FB3 FB2 VSUP VSUP VSUP VSUP 0603 R17 0R(nm) FB5 FB4 FB3 FB2 LX5 LX4 LX3 LX2 SD4: master SD5: slave FB5 must be connected to GND (short C28) TEMP2_SD6 TEMP1_SD6 CTRL2_SD6 CTRL1_SD6 FB_SD6_N FB_SD6_P TEMP3_SD0 CTRL8_SD0 CTRL7_SD0 FB_SD0_N FB_SD0_P TEMP2_SD0 TEMP1_SD0 CTRL6_SD0 CTRL5_SD0 CTRL4_SD0 CTRL3_SD0 CTRL2_SD0 CTRL1_SD0 TEMP_SD1 CTRL2_SD1 CTRL1_SD1 FB_SD1_N FB_SD1_P 0402 ONKEY ENABLE1 ENABLE2 THERM XRES_IN XRES_OUT AC_OK LID XINT OC_PG VSUP RBIAS V2_5 CREF CLK32K XIN32K XOUT32K VBAT_BKUP XRES_OUT XINT CLK32K XIN32K XOUT32K 0603 VSUP 0603 SCLK SDA_SDI SDA_SDI SCLK BU1VBAT BU2GND GND GND VSUP SDO TEMP2_SD6 TEMP1_SD6 CTRL2_SD6 CTRL1_SD6 FB_SD6_N FB_SD6_P TEMP4_SD0 TEMP3_SD0 TEMP2_SD0 TEMP1_SD0 CTRL8_SD0 CTRL7_SD0 CTRL6_SD0 CTRL5_SD0 CTRL4_SD0 CTRL3_SD0 CTRL2_SD0 CTRL1_SD0 FB_SD0_N FB_SD0_P TEMP_SD1 CTRL2_SD1 CTRL1_SD1 FB_SD1_N FB_SD1_P LDO10 LDO9 LDO7 LDO6 LDO5 LDO4 LDO3 LDO2 LDO1 LDO0 0603 1M(nm) 0603 0603 0603 0603 100k VIN_LDO0 VIN_LDO1_6 VIN_LDO9_10 VIN_LDO2_5_7 J15 J14 J13 0805 C11 22u C15 22u 0805 C23 (nm) 0805 C29 (nm) FB2 VIN_LDO0 VIN_LDO1_6 VIN_LDO9_10 VIN_LDO2_5_7 FB3 VIN_LDO2_5_7 FB4 VIN_LDO1_6 VIN_LDO9_10 0402 C14 J11 FB3 GPIO0 J120603 R16 270 1206 100u 1058375 HSMW-C191 0603 VSUP XRES_OUT1 1690149 SI1304BDL-T1-E3. XIN32K XOUT32K VBAT_BKUP VBAT_BKUP 0603 R11 0603 R12 0603 R13 0603 R14 0603 R15 SDO TEMP4_SD0 0402 100p 0402 100p 0402 100p 0402 100p 0402 100p 0402 100p HVSUP HVSUP HVSUPHV pin EN5V EN5V V2_5 401-1426-1-ND KMR211GLFS 401-1426-1-ND KMR211GLFS 1058375 HSMW-C191 PWM_DAT2 PWM_DAT1 PWM_CLK2 PWM_CLK1 VDD_GPIO_LV GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 SCSB 0805 C16 (nm) 0603 C17 2u2 0402 C38 0402 R10 220k ONKEY ENABLE1 ENABLE2 THERM AC_OK LID OC_PG RBIAS V2_5 CREF PWM_DAT2 PWM_DAT1 PWM_CLK2 PWM_CLK1 SCSB VDD_GPIO_LV XRES_IN PAD 1 BU7 VSUP PAD 1 BU8 GND VIN_LDO3_4 FB_SD1 VIN_LDO11 VIN_LDO3_4 VIN_LDO11 L4 must not mounted 1658510 C76 100uF VSUP VSUP 0603 R60 0603 R61 0603 R62 VIN_LDO3_4 VIN_LDO11 VIN_LDO3_4 VIN_LDO11 VSUP R17 must be mounted 0402 100n 0402 C18 0402 C19 0402 C20 SD2 SD3 SD4 SD5 VIN_LDO3_LV VIN_LDO3_LV FB_SD1 LDO11 VIN_LDO3_LV VIN_LDO0VIN_LDO0 HVSUP 0402 C101 0603 R87 0R(nm) J53 VIN_LDO3_SWVIN_LDO3_SW J10 BU11VSUP VSUP BU12GND VIN_LDO0B14 LDO1B9 LDO2A9 LDO3B7 LDO4A2 LDO5A10 LDO6A7 LDO7A11 VIN_LDO3_LVB6 VIN_LDO1_6A8 LIDD7 THERMD8 ENABLE2E11 AC_OKL8 CLK32KD1 ENABLE1F8 V2_5H2 CREFJ4 VBAT_BKUPH4 XINTC1 RBIASJ2 VSSA A1 ONKEYB10 SCL_SCLKG4 SDA_SDIF4 XRES_INJ8 VSUP_GPIOL9 GPIO1G6 GPIO2D5 GPIO3E4 GPIO4B3 LX_SD2 N5 FB_SD6_P F11 TEMP1_SD6 L14 VSUP_ANAH1 FB_SD2 K1 CTRL1_SD6 C13 PWM_CLK1D9 CTRL2_SD6 C14 VSUP_SD2 N6 AS3722 VIN_LDO9_10A6 VIN_LDO3_4A3 VIN_LDO2_5_7A12 VIN_LDO3_SWA4 VIN_LDO11B1 LDO0A13 LDO9A5 LDO10B8 LDO11B5 FB_SD6_N G11 TEMP4_SD0 K11 TEMP3_SD0 K13 TEMP2_SD0 J13 TEMP1_SD0 J14 CTRL8_SD0 H14 CTRL6_SD0 G14CTRL7_SD0 H13 CTRL5_SD0 G13 CTRL4_SD0 F14 CTRL3_SD0 F13 CTRL2_SD0 E14 CTRL1_SD0 E13 FB_SD0_P H11FB_SD0_N J11 FB_SD1_P G9 TEMP_SD1 K14 CTRL1_SD1 D13CTRL2_SD1 D14 FB_SD1_N H9 VSUP_SD2 P6 LX_SD2 N7 LX_SD2 P5 VSS_SD2 N4 VSS_SD2 N8 VSS_SD2 P4 LX_SD3 M1 FB_SD3 K2 VSUP_SD3 L1 VSUP_SD3 L2 LX_SD3 N1 LX_SD3 M2 VSS_SD3 N3 VSS_SD3 P2 VSS_SD3 P3 LX_SD4 N14 FB_SD4 L10 VSUP_SD4 N12 VSUP_SD4 P12 LX_SD4 P13 VSS_SD4 M13 VSS_SD4 M14 LX_SD5 N10 FB_SD5 J1 VSUP_SD5 N11 VSUP_SD5 P11 LX_SD5 P10 VSS_SD5 N9 VSS_SD5 P9 VDD_GPIO_LVF2 VSS_GPIOF1 GPIO0D6 GPIO5C2 GPIO6B4 GPIO7D2 ENABLE3_SDOE2 SCSBH6 XRES_OUTL5 XIN32KG1 XOUT32KG2 GNDSENSEK4 OC_PGE1 PWM_CLK2B11 PWM_DAT1D10 PWM_DAT2B12 DCDC6 System Control PWM I2C/SPI GPIO LDO0 - LDO11 DCDC0 DCDC1 DCDC2 DCDC3 DCDC4 DCDC5 References TEMP2_SD6 L13 VSSA A14 VSSA F7 VSSAJ7 VSSA P1 VSSA P14 LX_SD2 P7 VSS_SD2 P8 EN5VL6 VBATL7 Multi-Phase DCDC controller PMIC AS3722 VSUP VSUP 0603 R89 1M(nm) 0603 R90 1M(nm) 0603 R91 1M (nm) J54 ONKEY 0603 R92 1M(nm) VSUP AC_OK LID VSUP 0603 R93 0603 R94 1M(nm) 0603 R95 0603 R96 VSUP VDD_GPIO_LV

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Application Information Figure 228: Application Schematic 2/3 12345678 D C B A Size Date Project Title Revision Sh t fOi i t k AS3722 Evalboard BGAA3 1.2 18.11.2013 CTRL1_U0a CTRL2_U0a CTRL1_U0b CTRL2_U0b CTRL1_U0c CTRL2_U0c CTRL1_U0d CTRL2_U0d TEMP_U0a TEMP_U0b TEMP_U0c TEMP_U0d SD0 (4A - 32A) TEMP4_SD0 TEMP3_SD0 TEMP2_SD0 TEMP1_SD0 CTRL8_SD0 CTRL7_SD0 CTRL6_SD0 CTRL5_SD0 CTRL4_SD0 CTRL3_SD0 CTRL2_SD0 CTRL1_SD0 1206 C42 47u 1206 C45 47u 1210 C44 22u1210 C43 22u 1210 C47 22u 1210 C48 22u 1210 C51 22u 1210 C52 22u 1210 C55 22u 1210 C56 22u LX0a1 LX0a2 LX0b1 LX0b2 LX0c1 LX0c2 LX0d1 LX0d2 0603 R20 J19 J20 J21 CTRL1_SD0 CTRL2_SD0 TEMP1_SD0 CTRL3_SD0 CTRL4_SD0 TEMP2_SD0 CTRL5_SD0 CTRL6_SD0 TEMP3_SD0 CTRL7_SD0 CTRL8_SD0 TEMP4_SD0 0603 R22 0603 R24 0603 R21 0R(nm) 0603 R26 0603 R28 0603 R29 0603 R27 0R(nm) 0603 R31 0603 R33 0603 R34 0603 R36 0603 R38 0603 R39 0603 R32 0R(nm) 0603 R37 0R(nm) 0603 R35 0R(nm) 0603 R30 0R(nm) 0603 R25 0R(nm) 0603 R19 0R(nm) L5 = L6 = 0.47uH L5 = 0.47uH L6 not connected R19 not connected R19 needed SD0a normal mode: SD0a combined mode: L5 = L6 = 0.47uH L5 = 0.47uH L6 not connected R19 not connected R19 needed SD0a normal mode: SD0a combined mode: L7 = L8 = 0.47uH L7 = 0.47uH L8 not connected R25 not connected R25 needed SD0b normal mode: SD0b combined mode: L9 = L10 = 0.47uH L9 = 0.47uH L10 not connected R30 not connected R30 needed SD0c normal mode: SD0c combined mode: L11 = L12 = 0.47uH L11 = 0.47uH L12 not connected R35 not connected R35 needed SD0d normal mode: SD0d combined mode: L7 = L8 = 0.47uH L7 = 0.47uH L8 not connected R25 not connected R25 needed SD0b normal mode: SD0b combined mode:LL L9 = L10 = 0.47uH L9 = 0.47uH L10 not connected R30 not connected R30 needed SD0c normal mode: SD0c combined mode: L11 = L12 = 0.47uH L11 = 0.47uH L12 not connected R35 not connected R35 needed SD0d normal mode: SD0d combined mode:LL set J19 to "on" if SD0b is used! set J20 to "on" if SD0c is used! set J21 to "on" if SD0d is used! FB_SD0_P FB_SD0 FB_SD0_P FB_SD0_NFB_SD0_N J17 0603 R18 0603 R23 J18 PAD 1 BU6GND PAD 1 BU5SD0 0603 R63 20k L5 0.68u on on on off off off SD0 L6 0.68u L7 0.68u L8 0.68u L9 0.68u L10 0.68u L11 0.68u L12 0.68u FB_SD0 J16 FB_SD0 FB_SD0 FB_SD0 FB_SD0 FB_SD0 FB_SD0 FB_SD0 C30 100n C77 100n C78 100n C79 100n C80 100n C81 100n C82 100n C83 100n Boost1_0d Boost2_0d Boost1_0c Boost2_0c Boost1_0b Boost2_0b Boost1_0a Boost2_0a HVSUP HVSUP HVSUP HVSUP 0402 C90 0402 C91 0402 C92 0402 C93 0603 R66 0R(nm) 0603 R67 0R(nm) 0603 R68 0R(nm) 0603 R69 0R(nm) 0603 R73 0603 R74 0603 R75 0603 R76 0603 R77 0603 R78 0603 R79 0603 R80 1206 C46 47u 1206 C49 47u 1206 C50 47u 1206 C53 47u 1206 C54 47u 1206 C57 47u VSUP VSUP VSUP VSUP PVSS1 B4 LX1 B3HVSUP1B2 CTRL2E1 PVSS2 D4 LX2 D3HVSUP2D2 TEMPD1 PVSS1 A4 LX1 A3HVSUP1A2 CTRL1B1 PVSS1 C4 LX1 C3HVSUP1C2 BOOST1A1 HVSUP2E2 HVSUP2F2 LX2 E3 LX2 F3 5VSUPC1 BOOST2F1 PVSS2 E4 PVSS2 F4 AS3728 8A Power Stage SD0a AS3728 PVSS1 B4 LX1 B3HVSUP1B2 CTRL2E1 PVSS2 D4 LX2 D3HVSUP2D2 TEMPD1 PVSS1 A4 LX1 A3HVSUP1A2 CTRL1B1 PVSS1 C4 LX1 C3HVSUP1C2 BOOST1A1 HVSUP2E2 HVSUP2F2 LX2 E3 LX2 F3 5VSUPC1 BOOST2F1 PVSS2 E4 PVSS2 F4 AS3728 8A Power Stage SD0b AS3728 PVSS1 B4 LX1 B3HVSUP1B2 CTRL2E1 PVSS2 D4 LX2 D3HVSUP2D2 TEMPD1 PVSS1 A4 LX1 A3HVSUP1A2 CTRL1B1 PVSS1 C4 LX1 C3HVSUP1C2 BOOST1A1 HVSUP2E2 HVSUP2F2 LX2 E3 LX2 F3 5VSUPC1 BOOST2F1 PVSS2 E4 PVSS2 F4 AS3728 8A Power Stage SD0c AS3728 PVSS1 B4 LX1 B3HVSUP1B2 CTRL2E1 PVSS2 D4 LX2 D3HVSUP2D2 TEMPD1 PVSS1 A4 LX1 A3HVSUP1A2 CTRL1B1 PVSS1 C4 LX1 C3HVSUP1C2 BOOST1A1 HVSUP2E2 HVSUP2F2 LX2 E3 LX2 F3 5VSUPC1 BOOST2F1 PVSS2 E4 PVSS2 F4 AS3728 8A Power Stage SD0d AS3728 1206 C102 47u(nm) 1206 C103 47u 1206 C104 47u(nm) 1206 C105 47u 1206 C106 47u(nm) 1206 C107 47u 1206 C108 47u(nm) 1206 C109 47u 1210 C111 22u1210 C110 22u 1210 C112 22u 1210 C113 22u 1210 C114 22u 1210 C115 22u 1210 C116 22u 1210 C117 22u

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Application Information Figure 229: Application Schematic 3/3 12345678 D C B A Size Date Project Title Revision Sheet ofOriginator mkc AS3722 Evalboard BGAA3 1.2 18.11.2013 HVSUP FB_SD1_P SD1 (4A - 8A) TEMP_SD1 CTRL2_SD1 CTRL1_SD1 LX1(28)-1 LX1(28)-2 CTRL1_U1 CTRL2_U1 TEMP_U1 CTRL1_SD1 CTRL2_SD1 TEMP_SD1 FB_SD1_N J25 FB_SD1_N FB_SD1_P L13 = L14 = 0.47uH L13 = 0.47uH L14 not connected R41 not connected R41 needed SD1 normal mode: SD1 combined mode: L13 = L14 = 0.47uH L13 = 0.47uH L14 not connected R41 not connected R41 needed SD1 normal mode: SD1 combined mode: J28 VSUP J24 1 J26 CTRL1_SD1 TEMP_SD1 CTRL2_SD1 PAD 1 BU4 GND PAD 1 BU3 SD1 FB_SD6_P SD6 (4A - 16A) TEMP1_SD6 CTRL2_SD6 CTRL1_SD6 SD6 LX6a1 LX6a2 CTRL1_U6a CTRL2_U6a TEMP_U6a CTRL1_SD6 CTRL2_SD6 TEMP1_SD6 FB_SD6_N J30 FB_SD6_N FB_SD6_PFB_SD6 LX6b TEMP2_SD6 CTRL_U6b TEMP_U6b TEMP2_SD6 J32 SD6a alone: R49, R51, R53 needed R50 needed if CTRL combined SD6a & SD6b:R49, R50, R53, R54, R55 needed R51 not connected SD6a alone: R49, R51, R53 needed R50 needed if CTRL combined SD6a & SD6b:R49, R50, R53, R54, R55 needed R51 not connected d L15 = L16 = 0.47uH L15 = 0.47uH L16 not connected R48 not connected R48 needed SD6a normal mode: SD6a combined mode: L15 = L16 = 0.47uH L15 = 0.47uH L16 not connected R48 not connected R48 needed SD6a normal mode: SD6a combined mode: set J32 to "on" if SD6b is used! PAD 1 BU9 GND PAD 1 BU10 SD6 0603 R48 0603 R41 0R(nm) 0603 R43 0R(nm) 0603 R54 0603 R42 0603 R44 0603 R46 0603 R49 0603 R51 0R(nm) 0603 R53 0603 R55 on off 0603 R40 0603 R45 0603 R47 0603 R52 0603 R64 82k R65 39k 0603 R50 SD1 L13 0.68u L14 0.68u L15 0.68u L16 0.68u L17 0.68u FB_SD1 FB_SD1 J27 J23 FB_SD6 FB_SD6 FB_SD6 J31 J29 FB_SD1 C84 100n C85 100n C86 100n C87 100n C88 100n C89 100n Boost1_6b Boost2_6b Boost1_6a Boost2_6a Boost1_1 Boost2_1 HVSUP HVSUP 0402 C94 0402 C95 0402 C96 0603 R70 0R(nm) 0603 R71 0R(nm) 0603 R72 0R(nm) 0603 R81 0603 R82 0603 R83 0603 R84 0603 R85 0603 R86 VSUP VSUP VSUP PVSS B4 LX1 B3VSUPB2 CTRL2D1 PVSS D4 LX2 D3VSUPD2 TEMPB1 PVSS A4 LX1 A3VSUPA2 CTRL1A1 PVSS C4 LX2 C3VSUPC2 AGNDC1 AS3729 SD1b AS3729_WLP16 (nm) VSUP CTRL1_U1 CTRL2_U1 TEMP_U1 LX1(29)-1 LX1(29)-2 L18 0.47u(nm) L19 0.47u(nm) FB_SD1 FB_SD1 1210 C59 22u 1210 C60 22u 1210 C63 22u 1210 C64 22u 0603 C97 10u(nm) 0603 C98 10u(nm) 1210 C66 22u 1210 C67 22u 1206 C58 47u 1206 C61 47u 1206 C99 47u(nm) 1206 C100 47u(nm) 1206 C62 47u 1206 C65 47u 1206 C68 47u J52 HVSUP 0603 R88 0R(nm) FB_SD1 PVSS1 B4 LX1 B3HVSUP1B2 CTRL2E1 PVSS2 D4 LX2 D3HVSUP2D2 TEMPD1 PVSS1 A4 LX1 A3HVSUP1A2 CTRL1B1 PVSS1 C4 LX1 C3HVSUP1C2 BOOST1A1 HVSUP2E2 HVSUP2F2 LX2 E3 LX2 F3 5VSUPC1 BOOST2F1 PVSS2 E4 PVSS2 F4 AS3728 8A Power Stage SD1a AS3728 PVSS1 B4 LX1 B3HVSUP1B2 CTRL2E1 PVSS2 D4 LX2 D3HVSUP2D2 TEMPD1 PVSS1 A4 LX1 A3HVSUP1A2 CTRL1B1 PVSS1 C4 LX1 C3HVSUP1C2 BOOST1A1 HVSUP2E2 HVSUP2F2 LX2 E3 LX2 F3 5VSUPC1 BOOST2F1 PVSS2 E4 PVSS2 F4 AS3728 8A Power Stage SD6a AS3728 PVSS1 B4 LX1 B3HVSUP1B2 CTRL2E1 PVSS2 D4 LX2 D3HVSUP2D2 TEMPD1 PVSS1 A4 LX1 A3HVSUP1A2 CTRL1B1 PVSS1 C4 LX1 C3HVSUP1C2 BOOST1A1 HVSUP2E2 HVSUP2F2 LX2 E3 LX2 F3 5VSUPC1 BOOST2F1 PVSS2 E4 PVSS2 F4 AS3728 8A Power Stage SD6b AS3728 1210 C118 22u 1210 C119 22u 1210 C120 22u 1210 C121 22u 1210 C122 22u 1210 C123 22u 1206 C125 47u(nm) 1206 C124 47u 1206 C127 47u 1206 C126 47u(nm) 1206 C128 47u 1206 C129 47u 1206 C130 47u(nm) L20 0.68u

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Application Information PCB Routing Recommendations RBIAS A critical line on the PMIC is RBIAS. This is a high ohmic node and may pick up noise from nearby clock lines rather easily. Please keep the trace as short as possible and do not route any clock line near to it. Internal DCDC Attention should be paid to the routing of the VSUP , LX and GND traces of the DCDC converter.

• Keep the VSUP traces to the input capacitor as short as possible. Do not use vias for this connection.
• Make a common ground area fo r the input cap, output cap and PVSS terminal of the DCDC . Connect this ground area with vias to the system ground plane.
• Use short wide traces for LX no de. If you need to set vias, use it on the LX trace and not on the capacitor connections. Power Stage Connections To avoid cross talk to other lines a minimum spacing of minimum 3W should be kept. For a proper DCDC operation it’s recommended to avoid routing other clock traces being routed in parallel (also on other layers) to the control lines. Figure 230: PCB Control Line Routing PCB Control Line Routing: Shows an example PCB routing for the control lines of the multiphase controllers. CTRL1&2, are not interfering wi th each other as they are running at 180° phase shift. They can be routed with a minimum spacing. The TEMP lines should be used as “guard traces” to other control line pairs (e.g. CTRL3&4 or CTRL 5&6 or CTRL 7&8) as well as to other sensitive or clock traces on the PCB. A minimum spacing of >1.5W should be used as spacing bet ween TEMP and CTRL traces. CTRL1 GND H İr W •3W > 1W CTRL2 W> 1.5W TEMP1 W> 1.5W CTRL3 W> 1W CTRL4 W

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Application Information To minimize the cross talk of these clock lines, the width of the traces (W) should be the minimum acceptable width for manufacturing (e.g. 4mil).The di fferential feedback lines are less critical, nevertheless to en sure a good coupling between the differential lines and a low coupling to other traces and ground planes its recommended to have: S<W, S<H, X≥2W and Figure 231: PCB Differential Feedback Routing PCB Differential Feedback Routing: Shows an example PCB routing for the differential feedback lines of the multiphase controllers. FB_N W FB_P S W X GND H İr

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Package Drawings & Markings Figure 232: Package Drawing (CTBGA) Note(s) and/or Footnote(s): 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. 3. Primary datum C and seating plane are defined by the spherical crowns of the contact balls. 4. Dimensions ‘b’ is measured at the maximu m ball diameter, parallel to primary datum C. Package Drawings & Markings Ref Min Typ Max D1 6.50 aaa - 0.10 - bbb - 0.10 - ddd - 0.08 - eee - 0.15 - fff - 0.05 - N 124 Green RoHS Ref Min Typ Max A- - 1 . 2 0 A1 0.15 - - A2 - - 1.00 b 0.25 0.30 0.35 e0 . 5 0 B S C D8 . 0 0 E8 . 0 0 E1 6.50

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Package Drawings & Markings Figure 233: Package Drawing (WL-CSP) Note(s) and/or Footnote(s): 1. Pin 1=A1 2. ccc Coplanarity 3. All dimensions are in μm

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Package Drawings & Markings Figure 234: Package Marking Figure 235: Package Code Package Code: Shows the coding of the package marking. Figure 236: Start-Up Revision Code Start-Up Revision Code: Shows the coding of the different startup sequences. Package Marking: Shows the package marking for different product versions. YY WW I ZZ @ Year Manufacturing week Plant identifier Free choice Sublot identifier (CTBGA only) xx Sequence ES Engineering samples, no sequence prog rammed or sequence programmed on request

00 Standard programming (no sequence programmed)

xx Other customer specified sequence programmed during production test YYWWIZZ AS3722 @ T1V2-xx

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Ordering & Contact Information Figure 237:

Ordering Information

Ordering Information: Shows the ordering information for the different product versions Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbaderstrasse 30

8141 Unterpremstaetten

Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code Marking OTP programming Delivery Form Package AS3722-BCTR-ES T1V2-ES sequence programmable on request Tray 124-pin CTBGA 0.5mm pitch AS3722-BCTT-00 T1V2-00 standard programming, no sequence Tape & Reel 124-pin CTBGA 0.5mm pitch AS3722-BCTT-xx T1V2-xx other customer specified programming Tape & Reel 124-pin CTBGA 0.5mm pitch AS3722-BWLW-ES T1V2-ES sequence programmable on request Waffle Pack 108-pin WL-CSP 0.4mm pitch AS3722-BWLT-00 T1V2-00 standard programming, no sequence Tape & Reel 108-pin WL-CSP 0.4mm pitch AS3722-BWLT-xx T1V2-xx other customer specified programming Tape & Reel 108-pin WL-CSP 0.4mm pitch Ordering & Contact Information

Document Feedback [v1-01] 2015-Sep-07 AS3722 − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specif ied lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are unde rway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to prov ide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appe aring in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding th e information set forth herein. ams AG reserves the right to ch ange specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any th ird party shall arise or flow out of ams AG rendering of technical or other services. Copyrights & Disclaimer

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Revision Information Note(s) and/or Footnote(s): 1. Page and figure numbers for the previous version may diff er from page and figure numbers in the current revision. 2. Correction of typographical er rors is not explicitly mentioned. Changes from 1-00 (2014-Jul-11) to current revision 1-01 (2015-Sep-07) Page Removed Confidential Updated Figure 6 7 Updated Figure 7 14 Updated Figure 31 38 Updated Figure 33 39 Updated text above Figure 46 46 Updated Figure 49 49 Updated Normal Startup 50 Updated Figure 50 51 Updated Figure 51 52 Updated Figure 52 53 Updated Figure 56 58 Updated OC_PG_SD0 Output 66 Updated Figure 106 114 Updated Figure 164 148 Revision Information

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Content Guide

1 General Description

1 Key Benefits & Features

2 Applications

3 Block Diagram

5 Pin Assignment

7 Pin Description

19 Typical Operating Characteristics

20 Detailed Descriptions-

Power Management Functions

20 DCDC Step-Down Converter

20 Description

21 Mode Settings

21 Low Ripple, Low Noise Operation

24 Power Save Operation (A utomatically Controlled)

24 Fast Regulation Mode

24 Selectable Frequency Operation

24 100% PMOS ON Mode for Low Dropout Regulation

24 Step-Down Converter Configuration Modes

27 Parameter

30 DCDC Step-Down Controller

30 Description

34 Mode Settings

34 Low Ripple, Low Noise Operation

35 High Efficiency Operation (Default Setting)

35 Low Power Operation (sdX_low_power=1)

35 Power Save Operation (A utomatically Controlled)

35 Force PWM Mode Operation

36 Fast Regulation Mode

36 100% PMOS ON Mode for Low Dropout Regulation

36 DVS (Dynamic Voltage Setting)

36 DVM (Dynamic Voltage Management)

36 Automatic Phase Shedding

36 Parameter

41 LDO Regulators

41 Description

43 Parameter

45 Low Power LDO V2_5 Regulator

45 Description

45 Parameter

46 Backup Battery Charger

46 Description

47 Parameter

48 Detailed Descriptions-

48 Start-Up

50 Normal Start-Up

52 Start-Up Reasons

52 Start-Up From Multiple Batteries

[v1-01] 2015-Sep-07 Document Feedback AS3722 − Content Guide

53 Reset

53 Description

54 Reset Reasons

54 Voltage Detection

55 Power Off

55 Software Forced Reset

55 External Triggered Reset

55 Over-Temperature Reset

55 Watchdog Reset

56 Long ONKEY Press

58 Parameter

58 Stand-By

58 Description

60 Stand-By Sequence

63 Internal References

63 Description

63 Low Power Mode

63 Parameter

64 Digital IO Supply Concept

64 Description

64 GPIO Pins

65 IO Functions

65 Normal IO Operation

65 Interrupt Output

65 VSUP_VBAT_Low Output (not de-bounced)

65 GPIO Interrupt Input

66 PWM Input

66 Voltage_sdtby + Restart Input

66 OC_PG_SD0 Output

66 PWRGOOD Output

66 Q32k Output

66 Watchdog Input

66 Soft-Reset Input

66 PWM Output

67 Vsup_vbat_low Output (de-bounced)

67 OC_PG_SD6 Output

67 ADC_reference Output

67 Dedicated IO Pins

67 Input Pins

67 ENABLE1/CORE_PWRREQ

67 ENABLE2/CPU_PWRREQ

67 THERM

68 AC_OK

68 LID

68 Output Pins

68 VBAT_ALARM (not de-bounced)

68 CLK32K

68 XINT

68 OC_PG

70 Supervisor

70 Temperature Supervision

71 Current Supervision

72 Watchdog

Document Feedback [v1-01] 2015-Sep-07 AS3722 − Content Guide

72 Description

73 Interrupt Generation

73 Description

74 Description

76 Parameter

77 Real Time Clock

77 Description

78 Alarm

79 Serial Control Interfaces

79 I2C-SPI Mode Selection

80 I2C Feature List

80 I2C Protocol

81 I2C Write Access

81 I2C Read Access

83 I2C Parameter

84 SPI Protocol

85 SPI Parameter

85 PMW DVS Control Interfaces

85 Description

86 Parameter

87 Register Description

87 Register Overview

101 Detailed Register Description

186 PCB Routing Recommendations

186 RBIAS

186 Internal DCDC

186 Power Stage Connections

192 RoHS Compliant & ams Green Statement

193 Copyrights & Disclaimer

194 Document Status