AS3715

AS3715 AMSOSRAM | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 159

Technical content

[v1-03] 2015-Aug-10 Document Feedback AS3715 Dual or Single Power Path PMIC The AS3715 is a compact System PMU supporting two Li-Ion batteries and up to 14 power rails. The device offers advanced power management functions. All necessary ICs and peripherals in a battery powered mobile device are supplied by the AS3715. It features 3 DCDC buck converters, one DCDC buck controller, a 5V HDMI booster, a HV backlight boost controller with 3 current sinks as well as 8 LDOs (2 low noise). The different regulated supply voltages are programmable via the serial control interface. 3-4MHz DCDC operation with 0.47uH coils is reducing cost and PCB space. AS3715 contains a linear or switch mode Li-Ion battery charger with constant current and constant voltage operation. The maximum charging current is 1.5A . An internal battery switch and an optional external swit ch are separating the battery during charging or whenever an external power supply is present. In addition a second external battery path can be controlled. With these switches it is also possible to operate with no or deeply discharged batteries. A dual USB input current limiter can be used to control the current taken form the USB supplies or charger inputs. Additional features are a 30V OV protection and JEITA compliant battery temperature supervisio n with selectable NTC beta values. The single supply voltage may vary from 2.7V to 5.5V. Ordering Information and Content Guide appear at end of datasheet. Key Benefits and Features The key benefits and features of AS3715, Dual or Single Power Path PMIC are listed below. Figure 1: Added Value of Using AS3715 Benefits Features

• Compact design due to small coils for IO and memory voltage generation
• DCDC step down regulators (3-4MHz)
• Output (0.6V-3.3V; 2x1A, 1x2A)
• High current generation with external power stage to minimize PMIC power dissipation
• DCDC step down controller
• DVM (0.6V-1.5V; 1x6A)
• Multiple independent voltage rails for general purpose IO supplies
• 8 universal LDOs
• 6x universal IO range(0.8-3.3V; 0.3A)
• 2x analog (1.2-3.3V; 0.25A) General Description

Document Feedback [v1-03] 2015-Aug-10 AS3715 − General Description

Applications

The device is suitable for digital still cameras, outdoor action cameras, digital movie cameras, general Li-Ion battery powered mobile devices.

• Backlight boost controller for multiple display configurations or fixed voltage supplies
• Current mode boost controller with two current sinks.
• Constant voltage operation and over-voltage protection
• 3 programmable current sinks (max. 40mA)
• Possible external PWM dimming input (DLS, CABC)
• Self-contained Li-Ion battery charger with dual battery and USB path control
• 1.5A max charging current
• Dual battery control (opt.)
• Dual charger input with current limiters (opt.)
• Soft-, Trickle-, Constant Current and Constant Voltage operation (3.5V to 4.44V)
• Linear and switch mode charging
• Charger timeout and JEITA temperature supervision
• NTC beta selection
• Save supervision in HW which works also without a processor
• Supervisor with interrupt generation and selectable warning levels
• Automatic battery monitoring
• Automatic temperature monitoring
• Power supply supervision for DCDC
• Flexible multi-purpose IOs for general control tasks
• General Purpose IOs
• A D C i n p u t
• W a k e - u p / s t a n d - b y i n p u t
• PWM input/output
• Low battery and power good status
• Enables the processor to check the actual system state in detail • ADC with internal and external sources
• Flexible and fast adaptation to different processors/applications
• OTP programmable Boot and Power-down sequence
• Power saving control according to the processor needs
• Stand-by function with programmable sequence and voltages
• Self-contained start-up and control dual battery and dual USB operation. Safety shutdown feature.
• Control Interface
• I²C control lines with watchdog
• ONKEY with 4/8s emergency shut-down
• P O R w i t h R E S E T I / O
• Dedicated package for PCB size optimization • Package
• 81-ball WL-CSP 0.4mm pitch Benefits Features

[v1-03] 2015-Aug-10 Document Feedback AS3715 − General Description Block Diagram The functional blocks of this device for reference are shown below: Figure 2: Block Diagram for AS3715 Block Diagram: Shows the main function blocks of the AS3715. 30V OVP op tion al

8 GPIOs + 4 Enable

(Sup ply & Temp) I2C Boot ROM (OTP) Watchdog Stand-by POR AS3715 Control & Reference

3 SINKs

HV, 40mA each DCDC1 1.5 – 2A 0.6 – 3.35V LDO4 UIO 1/g159 0.8-3.3V 300mA .g/3.g–(.g50.g – .g 0.g22.g/1 LDO5 UIO 1/g159 0.8-3.3V 300mA .g/3.g–(.g50.g / .g 0.g22.g/1 LDO6 UIO 1/g159 0.8-3.3V 300mA .g/3.g–(.g50.g 5 .g 0.g22.g/1 LDO7 UIO 1/g159 0.8-3.3V 300mA LDO8 UIO 1/g159 0.8-3.3V 300mA .g 0.g22.g/1 .g/3.g–(.g50.g 6 .g 0.g22.g/1 .g/3.g–(.g50.g 3 DCDC2 0.7 – 1A 0.6 – 3.35V .g 0.g22.g/– .g 0.g1(.g22.g/1 DCDC3 0.7 – 1A 0.6 – 3.35V .g 0.g22.g/– .g 0.g1(.g22.g/1 LDO1 ANA 1/g159 1.2-3.3V 250mA .g/3.g–(.g50.g 0 .g 0.g22.g/1 LDO2 ANA 1/g159 1.2-3.3V 250mA .g/3.g–(.g50.g 1 .g 0.g22.g/1 LDO3 UIO 1/g159 0.8-3.3V 300mA .g/3.g–(.g50.g .g 0.g22.g/1 5V CP 55mA 1MHz .g–2.g–6.g51.g/( .g–2.g–6.g51.g51 .g53.g /.g66.g1( .g 0.g22.g/1 BOOST (controller) voltage & current mode 0.5/1MHz 1.5A Li-Ion Charger linear or switched mode dual battery control enh anced temp control NT C ß-correction .g5/.g 1 .g5(.g50.g/1.g/1 .g53.g56.g5/.g–3 30V Over-Voltage Protection 0.6 – 1.5V

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Pin Assignments Figure 3: Pin Assignment Pin Assignment: Shows the top view pin assignment of the AS3715 1 2 3 4 5 6 7 8 9 A VSS_SU SENSEN_SU LDO6 LDO5 LDO4 CHGIN1 VSUP_CHG CHGIN2 CHGOUT B FB_SD4_N GATE_SU VIN_LDO456 GPIO8 EN2 CHGIN1 VSUP_CHG CHGIN2 CHGOUT C CTRL1_SD4 TEMP_SD4 VSUP_SU FB_SD4_P FB_SU EN1 IBATSW XOFF VSUP_SD3 D CAPN VSS_CP VEBAT CTRL2_SD4 SENSEP_SU EN4 EBATSW FB_SD3 LX_SD3 E V5_0 CAPP VSUP_CP VIBAT BATT EMP VUSB EN3 FB_SD2 VSS_SD3 F V2_5 LDO3 CREF GPIO7 GPIO6 SDA VSS_ANA VSSA VSS_SD2 G LDO2 VIN_LDO123 GPIO5 GPIO2 GPIO 1 CURR3 FB_SD1 VSUP_SD2 LX_SD2 H LDO1 GPIO3 SCL ONKEY VIN_LDO78 CURR2 LX_SD1 VSUP_SD1 VSUP_SD1 J GPIO4 XRES VSUP_GPIO LDO7 LDO8 CURR1 LX_SD1 VSS_SD1 VSS_SD1 Pin Assignments

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Pin Assignments Figure 4: Pin Description Pin # Pin Name I/O Description Max. Voltage If not used F6 SDA DI SPI digital input in SPI mode; Data IO in I²C mode. VSUP Open H3 SCL DI SPI clock input in SPI mode; SCK input in I²C mode. VSUP Open H4 ONKEY DI Input pin to startup with pull-down 5.5V Define level J2 XRES DIO IO pin for reset during active state VSUP Define level F1 V2_5 AO Output voltage of low power LDO V2_5 3.6V Mandatory F3 CREF AIO Bypass capacitor for the internal voltage reference; connect 100nF 1.8V Mandatory J3 VSUP_GPIO S Supply pin for GPIOs (connect to other VSUP pins) 5.5V Mandatory F7 VSS_ANA AIO Analog sense GND input (connect to VSSA on PCB) -M a n d a t o r y G5 GPIO1 DIO General purpose input/output pin VSUP Open G4 GPIO2 DIO General purpose input/output pin VSUP Open H2 GPIO3 DIO General purpose input/output pin VSUP Open J1 GPIO4 DIO General purpose input/output pin VSUP Open G3 GPIO5 DIO General purpose input/output pin VSUP Open F5 GPIO6 DIO General purpose input/output pin VSUP Open F4 GPIO7 DIO General purpose input/output pin VSUP Open B4 GPIO8 DIO General purpose input/output pin VSUP Open C6 EN1 DI Input pin to startup with pull-down 5.5V Open B5 EN2 DI Input pin to startup with pull-down 5.5V Open E7 EN3 DI Input pin to startup with pull-down 5.5V Open D6 EN4 DI Input pin to startup with pull-down 5.5V Open G2 VIN_LDO123 S Supply pad for LDOs 5.5V Mandatory B3 VIN_LDO456 S Supply pad for LDOs 5.5V Mandatory H5 VIN_LDO78 S Supply pad for LDOs 5.5V Mandatory

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Pin Assignments H1 LDO1 AO Output voltage of ana LDO - PMOS_1 3.3V Open G1 LDO2 AO Output voltage of ana LDO - PMOS_1 3.3V Open F2 LDO3 AO Output voltage of LDO - PMOS_1 3.3V Open A5 LDO4 AO Output voltage of LDO - PMOS_1 3.3V Open A4 LDO5 AO Output voltage of LDO - PMOS_1 3.3V Open A3 LDO6 AO Output voltage of LDO - PMOS_1 3.3V Open J4 LDO7 AO Output voltage of LDO - PMOS_1 3.3V Open J5 LDO8 AO Output voltage of LDO - PMOS_1 3.3V Open H9 VSUP_SD1 S System supply voltage input of SD1 (connect to other VSUP pins) 5.5V Mandatory H8 VSUP_SD1 S System supply voltage input of SD1 (connect to other VSUP pins) 5.5V Mandatory J7 LX_SD1 AIO LX node of Stepdown1 VSUP Open H7 LX_SD1 AIO LX node of Stepdown1 VSUP Open G7 FB_SD1 AI Analog Feedback pin of SD1 3.6V Open J9 VSS_SD1 AIO Power GND pin of Stepdown1 - Mandatory J8 VSS_SD1 AIO Power GND pin of Stepdown1 - Mandatory G8 VSUP_SD2 S System supply voltage input of SD2 (connect to other VSUP pins) 5.5V Mandatory G9 LX_SD2 AIO LX node of Stepdown2 VSUP Open E8 FB_SD2 AI Analog Feedback pin of SD2 3.6V Open F9 VSS_SD2 AIO Power GND pin of Stepdown2 - Mandatory C9 VSUP_SD3 S System supply voltage input of SD3 (connect to other VSUP pins) 5.5V Mandatory D9 LX_SD3 AIO LX node of Stepdown3 VSUP Open D8 FB_SD3 AI Analog Feedback pin of SD3 3.6V Open E9 VSS_SD3 AIO Power GND pin of Stepdown3 - Mandatory C4 FB_SD4_P AIO Positive Feedback of SD4 3.6V Open B1 FB_SD4_N AIO Negative Feedback of SD4 3.6V Open Pin # Pin Name I/O Description Max. Voltage If not used

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Pin Assignments C1 CTRL1_SD4 AIO Bidirectional control pin of SD4, phase 1 VSUP Open D4 CTRL2_SD4 AIO Bidirectional control pin of SD4, phase 2 VSUP Open C2 TEMP_SD4 AIO Temperature control pin of power stage for SD4 VSUP Open E3 VSUP_CP S System supply voltage input of CP (connect to other VSUP pins) 5.5V Mandatory E2 CAPP AIO Flying cap of charge pump VSUP Open D1 CAPN AIO Flying cap of charge pump VSUP Open E1 V5_0 AIO Output voltage of charge pump - Open D2 VSS_CP AIO Power GND pin of 5V charge pump - Mandatory C3 VSUP_SU S System supply voltage input of SU (connect to other VSUP pins) 5.5V Mandatory D5 SENSEP_SU AI SU positive sense resistor input VSUP Open A2 SENSEN_SU AI SU negative sense resistor input VSUP Open C5 FB_SU AI Analog Feedback pin of SU 3.6V Open B2 GATE_SU AO SU ext. NMOS gate driver output VSUP Open A1 VSS_SU AIO Power GND pin of SU - Mandatory J6 CURR1 AIO Current sink 1 terminal 30V Open H6 CURR2 AIO Current sink 2 terminal 30V Open G6 CURR3 AIO Current sink 3 terminal 30V Open D7 EBATSW AO External battery switch gate driver VSUP Open C7 IBATSW AO Internal battery switch gate driver VSUP Open C8 XOFF AO External OV NMOS gate driver 15V Open A6 CHGIN1 S Charger adapter input (protected) 5.5V Open B6 CHGIN1 S Charger adapter input (protected) 5.5V Open A8 CHGIN2 S 2 nd Charger adapter input 5.5V Open B8 CHGIN2 S 2nd Charger adapter input 5.5V Open A7 VSUP_CHG S IO Current limiter output, Charger input VSUP Open B7 VSUP_CHG S IO Current limiter output, Charger input VSUP Open Pin # Pin Name I/O Description Max. Voltage If not used

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Pin Assignments Pin Description: This table shows the pin description for the CSP package including information of the I/O type, protection and handling if the function block is not used. A9 CHG_OUT AO Charger output (liner, switched) 5.5V Open B9 CHG_OUT AO Charger output (liner, switched) 5.5V Open E6 VUSB S Charger adapter input (unprotected) 30V Open E4 VIBAT S Internal Li-Ion battery terminal 5.5V Open D3 VEBAT S External Li-Ion battery terminal 5.5V Open E5 BATTEMP AIO Li-Ion battery charger NTC input 3.6V Open F8 VSSA AIO Analog GND input - Mandatory Pin # Pin Name I/O Description Max. Voltage If not used

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings Symbol Parameter Min Max Units Comments Electrical Parameters Supply Voltage to Ground 30V pins -0.5 32 V Applicable for pins VUSB, CURR1/2/3 Supply Voltage to Ground 15V pins -0.5 17 V Applicable for pins XOFF Supply Voltage to Ground 5V pins -0.5 7.0 V Applicable for pins VSUP_SDx, VSUP_GPIO, VSUP_ANA, VIN_LDOx, LDOx, GPIOx, LX_SDx, GATE_SU, SENSEP/N XRES, SCL, SDA, ONKEY, ENx, VIBAT, VEBAT, E/IBATSW, CTRLx_SD4, CHGIN1/2 Supply Voltage to Ground 3V pins -0.5 5.0 V Applicable for pins V2_5, CREF, FB_SDx, FB_SU, TEMP_SD4, BATTEMP Voltage Difference between Ground Terminals -0.3 0.3 V Applicable for pins VSSx, VSSA I SCR Input Current (latch-up immunity) -100 100 mA Norm: JEDEC JESD78 Continuous Power Dissipation (TA = 70°C) PT Continuous power dissipation 1.2 W PT (1) for WL-CSP81 package (RTHJA ~ 45K/W) Electrostatic Discharge ESDHBM Electrostatic Discharge Human Body Model ±1.5 kV Norm: JEDEC JESD22-A114F Absolute Maximum Ratings

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Absolute Maximum Ratings Note(s) and/or Footnote(s): 1. Depending on actual PCB layout and PCB used. 2. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensiti vity Classification for Nonhermetic Solid State Surface Mount Devices” . Temperature Ranges and Storage Conditions TA Operating Temperature -40 85 °C TJ Junction Temperature 125 °C TSTRG Storage Temperature Range -55 125 °C RHNC Relative Humidity non-condensing 58 5 % MSL Moisture Sensitivity Level 1 Represents an unlimited floor life time Symbol Parameter Min Max Units Comments

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Electrical Characteristics All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 6:

Electrical Characteristics

unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VUSB Charger HV input 0 5 30 V CHGINx Charger input 0 5 5.5 V VIBAT, VEBAT Battery Voltage 2.5 3.6 5.5 V VSUPx Supply Voltage 2.5 3.6 5.5 V VINLDO123 Supply Voltage for LDO1, 2 & 3 2.7 3.6 5.5 V VINLDO456 Supply Voltage for LDO4, 5 & 6 1.7 3.6 5.5 V VINLDO78 Supply Voltage for LDO7 & 8 1.7 3.6 5.5 V V2_5 Voltage on Pin V2_5 2.4 2.5 2.6 V Ilow_power Low Power current @ VSUPx = 4.2V 220 μA Ipower_off Power-off current All regulators OFF, V2_5 ON, supplied via VIBAT only 13 μA

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Typical Operating Characteristics This page is intentionally left blank.Typical Operating Characteristics

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – Power Management Functions DCDC Step-Down Converter

Description

The step-down converter is a high efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS switches efficiency up to 95% can be achieved. The fast switching frequency allows using small inductors, without increasing the current ripple. The unique feedback and regulation circuit guarantees op timum load and line regulation over the whole output voltage range, up to an output current of 2A (SD1), and 1A for (SD2, SD3), with an output capacitor of only 8μF - 12μF. The implemented current limitation protects the DCDC and the coil du ring overload condition. Figure 7: Step-Down DC/DC Converter Block Diagram DCDC Step-Down Converter Block Diagram: Shows the internal structure of the DCDC bucks. Detailed Description – Power Management Functions Lo gic +- + Σ IMIN ILIMIT 250/600mA 1.2/2.5A ISENS EP ISENS EN Zero Comparator PWM Comparator Overvoltage Comparator Ref + 8% Ref - 5% Slope Com pensation Softstar t Ref = 0.6VSk ip sdX_low_noise clk sdX_lv sdX_vsel FB_SDx VSS_SDx LX_SD x VOUT VSUP_SDx CVS UP _SD x LSD x COU T_S Dx

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions Figure 12: DC/DC Buck Dis-Continuous Mode & High Efficiency 2/2 DC/DC Buck Dis-Continuous Mode: Shows the DC/DC switching waveforms of SD3 at about 10mA with the low_noise bit deactivated. It’s possible to switch between these two modes during operation. Power Save Operation (Automatically Controlled): As soon as the output voltage stays above the desired target value for a certain time, some internal blocks will be powered down leaving the output floating to lower the power consumption. Normal operation starts as soon as the output drops below the target value for a similar amount of time. To minimize the accuracy error some internal circuits are kept powered to assure a minimized output voltage ripple. Two addition guard bands, based on comparators, are set at ±5% of the target value to react quickly on large over/under-shoots by immediately turning on the output drivers without the normal ti me delays. This ensures a minimized ripple also in very extreme load conditions. DVM (Dynamic Voltage Management) To minimize the over-/undersho ot during a change of the output voltage, the DVM can be enabled. With DVM the output voltage will ramp up/down with a selectable slope after the new value was written to the registers. Without DVM the slew rate of the output voltage is only determined by external components like the coil and load capacitor as well as the load current. DVM can be selected for all step-down converters, but only for one at a time. (see dvm_time and sd_dvm_select description)

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – Power Management Functions Fast Regulation Mode This mode can be used to react faster on sudden load changes and thus minimize the over-/unde rshoot of the output voltage. This mode needs a bigger output capacitor to guarantee the stability of the regulator. The mode is enabled by setting sdX_fast =1. Selectable Frequency Operation Especially for very low load conditions, e.g. during a sleep mode of a processor, the switching frequency can be reduced to achieve a higher efficiency. The frequency for SD1 can be set to 3 or 4MHz. SD2 and SD3 have a 2, 3 or 4MHz mode. This mode is selected by setting sdX_freq and sdX_fsel to the appropriate values. 100% PMOS ON Mode for Low Dropout Regulation For low input to output voltage difference the DCDC converter can use 100% duty cycle for the PMOS transistor, which is then in LDO mode. Step-Down Converter Configuration Modes The step down dc/dc converters have two configuration modes to deliver different output currents for the applications. The operating mode is selected by setting the bit sd2_slave , sd3_slave (the default is set by the Boot-OTP) Parameter Figure 13: DC/DC Buck Converter Parameter Symbol Parameter Conditions Min Typ Max Unit VIN Input voltage Pin VSUP_SDx 2.7 5.5 V VOUT Regulated output voltage 0.6125 3.35 V VOUT_tol Output voltage tolerance min. ±30mV -3 3 % ILOAD_SD23 Load current SD2, 3 VSD2, 3 <1.8V 0 1 A VSD2, 3 >1.8V 0 0.7 A ILOAD_SD1 Load current SD1 VSD1 <1.8V 0 2 A VSD1 >1.8V 0 1.2 A ILIMIT Current limit SD2, 3 1.2 A SD1 2.5 A RPSW P-Switch ON resistance incl. bonds, substrate, etc SD2, SD3; VSUP_SDx=3.0V 250 500 mΩ

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions DC/DC Buck Converter Parameter: Shows the key electrical parameter of the internal DC/DC buck converters. Figure 14: DC/DC Buck Converter External Components DC/DC Buck Converter External Components: Shows the external component parameter of the internal DC/DC buck converters. SD1, VSUP_SDx=3.0V 120 200 mΩ RNSW N-Switch ON resistance incl. bonds, substrate, etc SD2, SD3; VSUP_SDx=3.0V 160 500 mΩ SD1; VSUP_SDx=3.0V 63 200 mΩ fSW Switching frequency sdX_frequ=1; sdX_fsel=1; fclk_int =4MHz 4M H z sdX_frequ=0; sdX_fsel=1; fclk_int =4MHz 3M H z sdX_frequ=0; sdX_fsel=0; fclk_int =4MHz (SD2/3 only) 2M H z ηeff Efficiency see figures below % IVDD Current consumption Operating current without load 60 μA RDISCHG Pull-down resistance SD1 disabled 100 Ω SD2 or SD3 disabled 200 Ω Symbol Parameter Conditions Min Typ Max Unit COUT_SD2;3 Output capacitor Ceramic X5R or X7R 8 μF Output capacitor, sd2_fast=1 or sd3_fast=1 Ceramic X5R or X7R 18 μF C OUT_SD1 Output capacitor Ceramic X5R or X7R 12 μF Output capacitor, sd1_fast=1 Ceramic X5R or X7R 27 μF CVSUP_SD1;2;3 Input capacitor Ceramic X5R or X7R 2.2 μF LSD1-SD3 Inductor 4/3MHz operation 0.5 1 μH 4/3MHz; VOUT≤1.8V 0.3 0.47 μH Symbol Parameter Conditions Min Typ Max Unit

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – Power Management Functions Mode Settings Low Ripple, Low Noise Operation Bit settings: sdX_low_noise =1 In this mode there is no minimu m coil current necessary before switching OFF the PMOS. As long as the load current is superior to the ripple current the device operates in continuous mode. When the load current gets lower, the discontinuous mode is triggered. As result, the auto-z ero comparator stops the NMOS conduction to avoid load discharge and the duty cycle is reduced down to tmin_on to keep the regulation loop stable. This results in a very low ri pple and noise, but decreased efficiency, at light loads, especially at low input to output voltage differences. Only in the case the load current gets so small that less than the minimum ON-time of the PMOS would be needed to keep the loop in regulation the regulator will enter low power mode operation. The crossover poin t is about ~1% of the DCDC current limit. High Efficiency Operation (Default Setting) Bit settings: sdX_low_noise =0 In this mode there is a minimu m coil current necessary before switching OFF the PMOS. As a result there are less pulses necessary at low output loads, and therefore the efficiency at low output load is increased. As drawback this mode increases the ripple at lower output currents. The crossover point to low power mode is already reached at reasonable high output currents (~10% of the DCDC current limit). It’s possible to switch between these two modes during operation. Low Power Operation (sdX_low_power=1) In this mode the controller is only running on a single phase (phase 1). Only one output stage of the external power stage is used to reduce the power consumption for e.g. a stand-by mode operation. Power Save Operation (Automatically Controlled) As soon as the output voltage stays above the desired target value for a certain time, some internal blocks will be powered down leaving the output floating to lower the power consumption. Normal operation starts as soon as the output drops below the target value for a similar amount of time. To minimize the accuracy error some internal circuits are kept powered to assure a minimized output voltage ripple.

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions Two addition guard bands, based on comparators, are set at ±5% of the target value to react quickly on large over/under-shoots by immediately turning on the output drivers without the normal ti me delays. This ensures a minimized ripple also in very extreme load conditions. Force PWM Mode Operation Even in the case the load current gets so small that less than the minimum ON-time of the PMOS would be needed to keep the loop in regulation the regulator will still stay on the fixed switching frequency without en tering low power mode. To guarantee a stable output voltage also negative coil currents are possible. This mode guarantees the lowest possible ripple and a fixed frequency over all load conditions for powering noise sensitive RF circuits, but is compromising on the efficiency. The mode is enabled by setting sdX_force_pwm =1. Fast Regulation Mode This mode can be used to react faster on sudden load changes and thus minimize the over-/unde rshoot of the output voltage. This mode needs a bigger output capacitor to guarantee the stability of the regulator. The mode is enabled by setting sdX_fast =1. 100% PMOS ON Mode for Low Dropout Regulation For low input to output voltage difference the DCDC converter can use 100% duty cycle for the PMOS transistor, which is then in LDO mode. DVM (Dynamic Voltage Management) To minimize the over-/undersho ot during a change of the output voltage, the DVM can be enabled. With DVM the output voltage will ramp up/down with a selectable slope after the new value was written to the registers. Without DVM the slew rate of the output voltage is only determined by external components like the coil and load capacitor as well as the load current. DVM can be selected for all step-down controllers, but only for one at a time. (see dvm_time and sd_dvm_select description).

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – Power Management Functions Analog LDO Regulators LDO1 and LDO2 are designed to supply sensitive analog circuits like LNA’s, Transceivers, VCO’s an d other critical RF components of cellular radios. Another application is the supply of audio devices or as a reference for AD and DA converters. The design is optimized to deliver the best compromise between quiescent current and regulator performance for battery powered devices. Stability is guaranteed with ce ramic output capacitors of 1μF ±20% (X5R) or 2.2μF +100/-50% (Z5U). The low ESR of these caps ensures low output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the power transistor has to operate in linear mode. Power supply rejection is high enough to suppress the PA-ripple on the battery in TDMA systems at the output. The low noise performance allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of the power device enables the device to deliver up to IOUT current even at nearly discharged batteries without any decrease of performance. The default guaranteed operating current during start-up is 150mA, but can be set to 250mA with ldoX_ilimit = 1. To save power in low-power states where the full performance is not needed the bias current can be reduce by setting reg_low_bias_mode = 1. Figure 27: Analog IO LDO Block Diagram Analog IO LDO Block Diagram: Shows the internal structure of the analog PMOS linear regulators. .g/3.g–(.g50.g(1 .g53.g25.g3 .g3–

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions Parameter Figure 28: Analog LDO Parameter LDO Parameter: Shows the key electrical parameter of the linear regulators. Note(s) and/or Footnote(s): 1. Guaranteed by design and verified by laboratory ev aluation and characterization; not production tested. Symbol Parameter Conditions Min Typ Max Unit VOUT_LDO1;2 Output voltage Iout<150mA; 10mV steps 1.2 3.3 V VOUT_tol Output voltage tolerance min. ±40mV -3 3 % IOUT_L Output current (1) ldoX_ilimit = 0 (150mA) 0 150 mA ILIMIT_L Current limit (1) 300 mA IOUT_H Output current (1) ldoX_ilimit = 1 (250mA) 0 250 mA ILIMIT_H Current limit (1) 500 mA RON ON resistance LDO1-2 0.6 Ω PSRR Power supply rejection ratio f=1kHz 70 dB f=100kHz 40 eN Output noise BW=10Hz to 100kHz; Vout=1.8V; Iout=1mA; Cout= 2.2uF 22 μVrms BW=10Hz to 100kHz; Vout=3.3V; Iout=1mA; Cout= 2.2uF 38 μVrms I OFF Shut down current 100 nA IVDD Supply current without load 50 μA without load, reg_low_bias_mode = 1 30 μA tSTART Startup time low current used during start-up 200 μs VLineReg Line regulation Static -1 1 mV Transient; Slope: tr=15μs; delta 1V -10 10 mV VLoadReg Load regulation Static -1 1 mV Transient; Slope: tr=15μs; 1mA->300mA -10 10 mV RDISCHG Pull-Down resistance Re gulator disabled 770 Ω

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions Parameter Figure 31: LDO Parameter LDO Parameter: Shows the key electrical parameter of the linear regulators. Note(s) and/or Footnote(s): 1. Guaranteed by design and verified by laboratory ev aluation and characterization; not production tested. Symbol Parameter Conditions Min Typ Max Unit VOUT_LDO3-6 Output voltage Iout<150mA; 25mV steps 0.825 3.3 V VOUT_LDO7-8 Output voltage Iout<150mA; 25mV steps 0.825 3.275 V VOUT_tol Output voltage tolerance min. ±40mV -3 3 % IOUT_L Output current (1) ldoX_ilimit = 0 (150mA) 0 150 mA ILIMIT_L Current limit (1) 300 mA IOUT_H Output current (1) ldoX_ilimit = 1 (300mA) 0 300 mA ILIMIT_H Current limit (1) 500 mA RON ON resistance LDO3-8 0.6 1 Ω PSRR Power supply rejection ratio f=1kHz 60 dB f=100kHz 30 eN Output noise BW=10Hz to 100kHz; Vout=0.85V; Iout=1mA; Cout= 2.2uF 48 μVrms BW=10Hz to 100kHz; Vout=3.3V; Iout=1mA; Cout= 2.2uF 181 μVrms I OFF Shut down current 100 nA IVDD Supply current without load 30 43 μA tSTART Startup time low current used during start-up 500 μs VLineReg Line regulation Static 0.07 %/V Transient; Slope: tr=15μs; delta 1V 20 mV VLoadReg Load regulation Static 0.014 %/mA Transient; Slope: tr=15μs; 1mA->300mA 30 mV RDISCHG Pull-Down resistance Regulator disabled 730 Ω

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions Figure 34: Low Power LDO External Components Low Power LDO External Components: Shows the external component parameter of the low power V2_5 linear regulator. DCDC Step-up Converter The DC/DC Step Up converter is a high efficiency current mode PWM regulator, which provides an output voltage dependent on the maximum VDS voltage of the external transistor, and maximum load current selectable by the external shunt resistor. For Example:

• 5V, 0.5-1A @ 1Mhz
• 25V, 50mA @ 1MHz
• 40V, 20mA @ 500kHz A constant switching frequency results in a low noise on supply and output voltage. Three feedback regulation modes are supported:
• Current feedback (all three current sinks can be selected)
• Current feedback with auto matic feedback selection
• Voltage feedback Symbol Parameter Conditions Min Typ Max Unit CV2_5 Output capacitor Ceramic X5R or X7R 0.7 μF

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – Power Management Functions Figure 35: DCDC Step-Up Converter DCDC Step-Up Converter Block Diagram: Shows the internal structure of the DCDC boost controller including external components. ov_curr ov_voltage Gate Driver V PWM Logic HV Current Sinks Each 0.156-39.8mA Automatic feedback select (CURR 1,2,3) Optional; only required if CURR3 can exceed 30V clk1 MHz 500 kHz stepup12_clkinv stpup2_on vov_current pulse_skip overshoot overshoot comp err ota stepup2_fb 1.25 V 0.8 V 1.25 V 0.5 V 1.4 V VSUP currX_ctrl = '10' CURR1 CURR2 CURR3 LEDs as required by the application FB_SU stepup2_fbprot GATE_SU SENSEN_SU SENSEP_SU RSU2 0.15Ÿ +/- 5% LSU2 10μH; SD12-100 Coiltronics DSU2 PMEG2010 QSU2 Si1304 CSU2_IN 2.2μF CSU2_OUT2 2.2μF/25V C1=1.5nFC2=15nF R2=100kŸ R1=1MŸ current sense setpup2_v step2_prot VSUPPLY ramp

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions Feedback Selection For the step up the following feedback selections are possible (selected by setpup2_fb ): (see Figure 35 ) Current Feedback CURR1, CURR2 and CURR3 can be selected by setpup2_fb as a current feedback pin. The step-up converter is regulated such that the required current at the feedback path can be supported. In this mode the output voltage will be limited by limiting the voltage on the selected feedback pin to 1.25V (select the external resistor network and stepup2_v to adjust this limitation voltage). stepup2_prot_dis has to be set to 0, otherwise the protection is disabled. Always choose the path with the higher voltage drop as feedback to guarantee adequate supply for the other, unregulated path. Current Feedback with Auto matic Feedback Selection Same as above, but when currX_ctrl = 10b for the used current sinks, the chip automatically selects the highest string (CURR1, CURR2 or CURR3) as feedback input. Voltage Feedback The step-up converter output voltage is regulated by regulating the selected feedback pin voltage to 1.25V. Calculating Resistors for Voltage Feedback or Over-Voltage Protection Bit stepup_res should be set to 1 in voltage feedback mode using two resistors. The output voltage is regulated to a constant value, given by: If R2 is not used, the output voltage is: V SU: Step up regulator output voltage R1 Feedback resistor R1 R2 Feedback resistor R2 IFB: Tuning current on FB_SU pin: stepup2_v (0..31μA (1μA steps)) (EQ1) VSU R1 R2+ (EQ2) VSU 1.25 I FB R1×+=

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – Power Management Functions Figure 36: SU Output Voltage or Protection Voltage IFB (stepup2_v) VSU VSU µA R1 = 1MΩ, R2 not used R1 = 500kΩ, R2 = 64kΩ 0- 1 1 1- 1 1 . 5 2- 1 2 3- 1 2 . 5 4- 1 3 56 . 2 5 1 3 . 5 67 . 2 5 1 4 78 . 2 5 1 4 . 5 89 . 2 5 1 5 9 10.25 15.5 10 11.25 16 11 12.25 16.5 12 13.25 17 13 14.25 17.5 14 15.25 18 15 16.25 18.5 16 17.25 19 17 18.25 19.5 18 19.25 20 19 20.25 20.5 20 21.25 21 21 22.25 21.5 …… … 30 31.25 26 31 32.25 26.5 SU Output Voltage or Protection Voltage: Shows examples of possible output or protection voltages of the DCDC SU depending on external resistors and FB_SU current settings.

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions Parameter Figure 37: DC/DC SU Parameter DC/DC SU Parameter: Shows the key electrical parameter of the DCDC boost converter. Symbol Parameter Conditions Min Typ Max Unit IVDD Quiescent Current Pulse skipping mode 140 μA VFB Feedback voltage for external resistor divider For constant voltage control 1.20 1.25 1.30 V VCURR Feedback voltage for current sink regulation CURR1, CURR2, CURR3 0.6 V IDCDC_FB Additional tuning current at FB_SU Adjustable by software in 1μA steps 03 1 μ A Accuracy of feedback current @ full scale -7 7 % Vrsense_ max Current limit voltage at Rsense E.g.: 0.65A for 0.15Ω sense resistor 100 mV RSW Switch resistance ON-resistance of external switching transistor 1Ω Iload Load current At 25V output voltage 0 50 mA fIN Switching frequency Internal CLK frequency/4, default 1MHz fclk_int/4 MHz tMIN_ON Minimum ON time 130 ns MDC Maximum duty cycle @ 1MHz 91 %

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – Power Management Functions Figure 38: DC/DC SU External Components DC/DC SU External Components: Shows the external component parameter of the DCDC boost converter. Symbol Parameter Conditions Min Typ Max Unit Cout Output capacitor Ceramic, ±20% 2.2 μF LSU Inductor Use inductors with small Cparasitic (<100pF) to get high efficiency; Vout >8V 10 μH Use inductors with small Cparasitic (<100pF) to get high efficiency; Vout <8V 4.7 μH QSU Transistor VGS(TH) threshold voltage 1.3 1.5 V VDS max drain to source voltage Vout_max +20% V RDS(ON) drain - source ON resistance 0.35 Ω QGS total gate charge @ VGS=4.5V 35 n C C1 / C2 Feedback capacitor ratio Ratio should be smaller than the feedback resistor ratio (inverted) to avoid overshoots during start-up R 2 / R1 μF

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions Current Sinks CURR1, 2 and 3 are high voltage (30V) current sinks, e.g. for series of white LEDs or general purpose usage to drive buzzer, vibrator, signal LEDs, etc. Current sinks CURR1, 2 and 3 can be controlled individually. The step-up DCDC converter (SU) may supply them with voltages up to 30V. For an automatic feedback selection the used current sinks can be assigned to the SU booster. If not used as a current sink, CURR3 can be used to output several status signals. In this mode the CURR3 output acts like an open-drain output and needs an external pull-up resistor for generating logic high levels. Parameter Figure 39: Current Sink Parameter Current Sink Parameter: Shows the key electrical parameter of the HV current sinks. Symbol Parameter Conditions Min Typ Max Unit ICURR1,2,3 CURR1,2 & 3 current For V(CURRx) > 0.5V resolution = 0.156mA 03 9 . 8 m A ICURR_protect Current sink protection Current Protection current if stpup_on=1 and currx_current=00h 2μ A Δ Absolute Accuracy All Current sinks -8 8 % VCURR1,2,3 Voltage compliance During normal operation 0.5 30 V

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions Charger The AS3715 device serves as a standalone battery charge controller supporting rechargeable Lithium Ion (LiIon) and Lithium Polymer batteries. Re quiring only a few external components, a full-featured battery charger with a high degree of flexibility can easily be real ized. The main features of the controller are:

• Charge adapter detection
• PowerPath management & internal voltage regulator (V2_5), for dead battery startup
• Low current (soft) charging
• Low current (trickle) charging
• Constant current charging
• Constant voltage charging
• 30V Overvoltage protection for CHGIN1(optional)
• Battery presence indication
• Operation without battery
• Separate input current limitation for CHGIN1/2
• Input voltage drop regulation
• Programmable linear or switched mode operation
• Single power-path mode for reduced ON-resistance
• Bypass mode for high input current application (up to 6A)

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – Power Management Functions Figure 42: Charger Application Block Diag ram, Switch Mode Charger Switch Mode Charger Block Diagram: Shows the connections and external components for the charger operating in switch mode. 30V OVP optional 1.5A Li-Ion Charger linear or switched mode dual battery control enhanced temp control NTC ß -correction VSUP_CHG EBATSW IBATSW VEBAT CHGOUT BATTEMP Power Path & LimiterCHGIN 1 4.7uF XOFF VUSB 30V Over-Voltage Protection CHGIN 2 4.7uF VIBAT 1uH

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions Figure 43: Charger Application Block Diagram, Linear Mode Charger Linear Mode Charger Block Diagram: Shows the connections and external components for the charger operating in linear mode. 30V OVP optional 1.5A Li-Ion Charger linear or switched mode dual battery control enhanced temp control NTC ß -correction VSUP_CHG EBATSW IBATSW VEBAT CHGOUT BATTEMP Power Path & LimiterCHGIN 1 4.7uF XOFF VUSB 30V Over-Voltage Protection CHGIN 2 4.7uF VIBAT

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – Power Management Functions Figure 44: Charger Application Block Diagram, Linear Mode Single Power-Path and Battery Linear Mode Charger Block Diagram: Shows the connections and external components for the charger operating in linear mode with a single power-path and only one battery. 30V OVP optional 1.5A Li-Ion Charger linear or switched mode dual battery control enhanced temp control NTC ß -correction VSUP_CHG EBATSW IBATSW VEBAT CHGOUT BATTEMP Power Path & LimiterCHGIN 1 4.7uF XOFF VUSB 30V Over-Voltage Protection CHGIN 2 VIBAT

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions Charging Cycle Description Charger Adapter Detection The charger uses an integrated detection circuit to determine if an external charger adapter has been applied to the VUSB pin. If the adapter voltage exceeds the battery voltage at pin VBAT by VCHDET the ChDet bit in the ChargerStatus register will be set. The detection circuit will reset the charge controller (bit ChDet is cleared) as soon as the voltage at the VUSB pin drops to only V CHMIN above the battery voltage. In case the AS3715 device is reset the charge controller will also be reset, even if a charge adapter is applied to the VUSB pin. Soft Charging Soft charge mode is started when an external charger adapter has been detected, the bat_charging_enable is set and the battery voltage at pin VBAT is below the VSOFT threshold. Low Current (Trickle) Charging Trickle charge mode is started when an external charge adapter has been detected bat_charging_enable is set and the battery voltage at pin VBAT is below the V TRICKLE threshold and above VSOFT threshold; bits ChDet and Trickle will be set in the ChargerStatus register. In this mo de the charge current will be limited to TrickleCurrent (set in the ChargerCurrent register) to prevent undue stress in case of deeply discharged batteries. Once V TRICKLE has been exceeded, the charger will change over to constant current charging ( Trickle is cleared). Constant Current Charging Constant current charging is initiated when bat_charging_enable is set and the battery voltage at pin VBAT is above the V TRICKLE and below V CHOFF. The CCM bit is set when the charger has started, and the charge current will be limited to ConstantCurrent by the battery charge controller. When the battery approaches full charge, its voltage will reach the charge termination threshold V CHOFF. VCHOFF depends on the ChVoltEOC bits settings. Top-off charge will be started ( CVM will be set). Constant Voltage Charging Constant voltage charge mo de is initiated and the CVM bit will be set when the V CHOFF threshold has been reached. The charge current is monitored during constant voltage charging. It will be decreasing from its initial value during constant current charging and eventually drop below the value set by TrickleCurrent . If the measured charge current is less than or equal to TrickleCurrent , the charging cycle is terminated and EOC is set.

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – Power Management Functions Figure 45: Charger States Charger States Diagram: Shows a full charging cycle with the corresponding states. Stop Charging Conditions There are multiple safety features implemented that trigger a stop_charging condition: These are the following:

• Battery temperature too high/low. If ntc_on=1 and voltage at pin NTC is below/above VBATTEMP threshold.
• Timeout timer expired (If ch_timeout >0 and charging time has been exceeded. (Can be reset by unplugging the charger, setting bat_charging_enable =0 or writing charging_tmax =0)
• VUSB over-voltage detected
• Die temp>140deg (ov_temp_140 set)
• All reset reasons External Charger at pin VUSB

5.5 V max

1. 5 V Battery Voltage (VBAT ) Charging Current Regulator Voltages XRES after enabling the charger serial communication possible t (not to scale ) 60 mA – 240 mA 350 mA – 1500 mA 2.9V -3.3% or - 5.6% Trickle Current Constant Current Constant Voltage EOC Resume ICHGOFF 1.8V Soft Charge 22 mA

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions Battery Presence Indication After EOC state is reached a timer for NOBAT detection is started. If there is no battery present, the VBAT voltage will drop to V RESUME . Depending on the load on VBAT and the capacitor on VBAT this might take some mi lliseconds to 1 second. If the RESUME mode is enabled (bit auto_resume =1), the charger will restart charging (ConstantCurrent charging) after 100msec delay. The 100msec dead time is necessary to get a battery oscillation frequency below 10Hz, if there is no battery present. If the NOBAT detection timer is below 2 seconds after reaching EOC state, and this happens 2 times in serial, the Nobat bit in ChargerStatus register is set. If a battery is inserted the bit will be reset after the timer exceeds the 2 seconds. Charger Overvoltage Protection This blocks checks if the ch arger voltage VUSB is above VCHOVH. If the VUSB voltage is above VCHOVH , the pin XOFF is pulled to GND immediately, to protect the pin VCHG_IN, and the charger is set into OFF state. If the VUSB voltage is below VCHOVH the XOFF pin is charged up to VXOFF_REG with an integrated charge pump. If the pin exceeds VXOFF_MIN the bit is set and the charger is started. NTC Supervision This charger block also features a supply for an external NTC resistor to measure the battery temperature while charging. If the temperature is too high the charger will stop operation. If needed an interrupt can be generated based on this event. When the battery temperature drops the voltage on BATTEMP pin will rise above VBATTEMP_OFF and the charger will start charging again. This is forming a temperature hysteresis of about 3 to 5°C to avoid an oscillation of the charger. The type of NTC ( ntc_10k :10k or 100k) can be selected via register settings. The battery temperature supervision via the NTC can be switched OFF ( ntc_on = 0). The supply for the NTC will be on when the ntc_on bit is set, no matter if a charger is detected or not. NTC ß-Correction To keep the voltage drop over the whole temperature range inside of the ADC input range a parallel resistor to the NTC is needed.

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions Txlim_upper = Txmin + Tx_adj * 7mV Also the hysteresis of the ON and OFF levels can be programmed (4bits with 16 7mV steps). Txlim_lower = Txlim_upper + ( Tx_hyst + 3) * 7mV Charger MIN/MAX Temp Supervision The simpler supervision mode is supervising T1 (0°C) and T4 (60°C) Figure 48: MIN/MAX Temp Supervision MIN/MAX Temp Supervision Diagram: Shows the voltage and current settings for the MIN/MAX temperature supervision. (EQ3) (EQ4) T1upper TEMPERATURE [°C] CHARGE CURRENT CHARGE VOLTAGE Maximum Charge Current: 1C Typical Charge Voltage: Veoc(typ) 3 . 5 V<V e o c ( t y p )<4 . 4 4 V 750mA < Icc_normal(typ) < 1500mA 60mA < Itrickle(typ) < 240mA COLD TYPICAL HOT Charger is OFF Charger is OFF 350mA < Icc_low(typ) < 750mA T1lower T4upper T4lower

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – Power Management Functions Charger JEITA Temp Supervision The more complex JEITA temperat ure supervision is monitoring T1 (0°C), T2 (10°C), T3 (45°C) and T4 (60°C) and adjusting charging current and voltage to it. Figure 49: JEITA Temp Supervision JEITA Temp Supervision Diagram: Shows the voltage and current settings for the JEITA temperature supervision. Dual Battery Switching The charger is only charging the battery connected to CHGOUT/VIBAT, but can handle two batteries and controls the external battery switches accordingly. When moving to power_off mode only the internal battery switch is kept closed. T1upper TEMPERATURE [°C] CHARGE CURRENT CHARGE VOLTAGE 0.5C Typical Charge Voltage: Veoc(typ) 3.5V < Veoc(warm) < 4.34V 750mA < Icc_normal(typ) < 1500mA 60mA < Itrickle(typ) < 240mA COLD TYPICAL HOT Charger is OFF Charger is OFF 350mA < Icc_low(typ) < 750mA T1lower T4upper T4lower 350mA < Icc_low(cool) < 750mA 60mA < Itrickle(cool) < 120mA COOL T2upper T2lower Maximum Charging Current 1C WARM T3upper T3lower Veoc(warm)=Veoc(typ)-100mV 3.5V < Veoc(typ) < 4.44V 350mA < Icc_normal(cool) < 750mA

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – Power Management Functions Figure 50: Dual Battery Switching (Flowchart) Dual Battery Switching Diagram: Shows the state diagram for controlling two batteries to the PMIC.

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – Power Management Functions Dual Power Path Two charger inputs can be used to hook up two different charger supplies. CHGIN1 has an optional protection function with an external NMOS using VUSB1 as sensing input. Figure 51: Dual Power Path Diagram Dual Power Path Diagram: Shows the internal structure of the dual power path input. PWRSELECT CHGIN 1 CHGIN 2 VSUP _CHG CURRLIM 1 XOFF VUSB1 External OVP optional CURRLIM 2 VUSB2 LDO PWRSELECT MAX (CHGIN1,CHGIN2,VSUP _CHG ) VBAT VUSB2 CHDET_USB 2 VBAT VUSB1 CHDET_USB1 -3.95V VBAT 3. 95V MAX(CHGIN1,CHGIN2,VSUP _CHG)

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – Power Management Functions Charger Parameter: Shows the key electrical parameter of the charger and power paths. ICC CC current limit Programmable in 50mA steps 350.. 1500 mA Linear charging mode -10 10 % IUSB_limit USB input current limit @ 470mA -7% 470 6% mA VRESUME Resume voltage limit to start charger VBAT falling threshold relative to ChVoltEOC (depending on ChVoltResume) -3.3 or -5.6 VSUP_min VSUP level for charging current regulation (reduction), to avoid voltage drop on VSUP Trickle current (or constant current in linear mode) will be regulated down, if VSUP drops below this level -6% 3.9 3% V 4.2 4.5 4.7 I REV_OFF Reverse current shut down VSUP_CHG = 5V, VUSB open 5 μA VDiode Ideal Diode start voltage 50 mV RON_BATSW Battery Switch ON-resistance 0.20 Ω Temp Supervision IBATTEMP NTC Bias Current 100kΩ NTC 10kΩ NTC -15% 15 150 15% μA XOFF Overvoltage Protection VCHOVH VUSB Overvoltage Detection monitor voltage on VUSB, disable charging beyond this voltage (200mV hysteresis) 6.2 3% V -3% 6.0 V XOFF_min Minimum XOFF voltage for charger startup 7.5 V VXOFF_REG Regulation voltage for XOFF pin 10 V IXOFF External pull down current on XOFF pin Connect XOFF pin to MOSFET gates only 100 nA Symbol Parameter Conditions Min Typ Max Unit

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – System Functions Start-Up Figure 56: Start-Up Flow Chart Start-Up Flow Chart: Shows the main state transitions during start-up. Detailed Description – System Functions power_of f=1 OR (VS UP<ResV oltFall && power_of f_at_vsuplow) OR (onkey_lpress_reset=0 && ONKEY lpress) OFF delay wait off_delay/g69 Reset all Registers Switch off Regulators reset registers and reload fuse s 0xA0 to 0xAB /g122 RUN startup sequence regulator startup sequnece GPIO programming during sequence startup delay programmable set sdX_sequ_on=1 or ldoX_sequ_on=1 if regulator selected during startup RESET Timer regulator startup executed waiting time to re lease X RE S p in 10..150ms ACTIVE state XRES=1 GPIOx=1 if GPIOx_iosf=6 or standby_mode _on=1 OFF delay wait off_delay /g69 Sequence Down force off all regulators not in the sequence; sequence down inverse to start-up sequence; STAND-BY state V2_5 stays active, all regulators with regX_stby_on=1 enabled any interrupt applied or ONKEY=1 or ENx=1 po wer_of f=1 or f orce_reset=1 or (XRES is low if stdby_reset_disable=1) or (VS UP<ResV oltFall && SupResEn=1) or Die temp>140°C or SD4 overtemp /g69 /g69 /g122 /g122 remove „stand-by force off“ of all regulators Die temp>140°C/g122 power_of f=1 or f orce_reset=1 o r XR ES is low o r ONKEY lpress /g69 OFF delay wait off_delay /g122 die temp >110°C /g69 /g122 /g69 any state Start-Up Battery or Charger insertion 1. V2_5 power up 2. Readout ROM fuse auto_of f=1 POWER OFF state V2_5 power up Quiescent current < 10uA Pin ONKE Y debounce time=20msec /g122 ONKEY=RISI NG OR ENx=RISI NG OR (chdet=1 && chg_pwr_of f_en=0) OR (chdet_rise && chg_pwr_of f_en=1) /g69 /g122 VSUP debounce state Measuring VSUP Quiesent current ~200uA /g69 5ms && VSUP>ResVoltRise auto_of f=1 or power_of f_at_vsuplow=1 N /g69 ONKEY=1 or Char ge detect =1 /g122 /g69 VSUP<ResVoltFall for more than 500ms /g122 /g69 /g122 /g122 SD4 overtemp or Die temp >140°C or (VS UP<ResVoltFall && SupResE n=1) /g69

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – System Functions Normal Startup The following gives a brief description on a start-up from scratch (battery insertion). More details can be found in the start-up flow charts.

• Powering up V2_5 (wait till it’s above V POR)
• The external capacitor on CREF is charged to 1.8V.
• Check if VSUP is above ResVoltRise
• Configuration of Charger (DCDC or linear) and SDx slave modes is read from Boot-OTP
• Startup State machine reads out the internal Boot-OTP. The start-up sequence of Step -Down Converter, LDO’s and GPIOs are controlled by the Boot-OTP.
• Reset-Timer is set by the Boot-OTP
• The reset is released when the Reset Timer expires (external pin XRES) Figure 57: Regulator Power-Up Sequence Regulator Power-Up Sequence: Shows timing relationships of the regulators and corresponding control signals during power-up. Reg1_select VSUP VSUP > ResVoltRise set in OTP 4ms debounce Reg2_select 0, 1, 4 or 12ms delay depending on Reg2_gpio_sel and del _time Reg11_select 0, 1, 4 or 12ms delay depending on Reg1_gpio_sel and del _time 10..150ms set by res_timer in OTP XRES 0, 1, 4 or 12ms delay depending on Reg11_gpio_sel and del _time. . .

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – System Functions Start-Up Reasons A Start-up can be activated from 4 different sources:

• VPOR has been reached (VUSB/VSUP/VBAT rising from scratch)
• ONKEY or ENx has been pul led high in power_off mode
• Reset cycle
• ResVoltRise was reached Parameter Figure 58: ONKEY/ENx-Input Start-Up Conditions ONKEY-Input Start-Up Conditions: Shows the electrical parameter for the ONKEY input initiating the start-up. Reset

XRES is a low active bi-directional pin. An external pull-up to the periphery supply has to be added. During each reset cycle the following states are controlled by the AS3715:

• Power-down sequence of the regulators
• Pin XRES is forced to GND
• All registers are set to their default values after power-ON, except the reset control- and status-registers.
• Normal startup with progra mmable power-ON sequence and regulator voltages (see Start-Up )
• Reset is active until the programmable reset timer expires (set by register bits res_timer<2:0> ) Symbol Parameter Conditions Min Typ Max Unit VUSBON Voltage in VUSB for system to start 4.2 5.0 30 V VON_IL ONKEY/ENx Low Level input voltage –0.3 0.4 V VON_IH ONKEY/ENx High Level input 1.4 VVSUP_ GPIO V ION_PD ONKEY/ENx Pull down current 5 12 20 μA

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – System Functions Reset Reasons Reset can be activated from 8 different sources:

• VPOR has been reached (VSUP/ VBAT rising from scratch)
• VSUP low, ResVoltFall (2.5V) has been reached
• Software forced reset by force_reset
• ONKEY or ENx long press has been detected
• External triggered through the pin XRES
• Over-temperature T140 (die)
• Over-temperature T140 SD4 (sub die)
• Watchdog Voltage Detection: There are two types of voltage dependent resets: V POR and VRESRISE . VPOR monitors the voltage on V2_5 and V RESRISE monitors the voltage on VSUP . The linear regulator for V2_5 is always ON and uses the voltage VUSB/VBAT/VSUP as its source. The pin XRES is only released if V2_5 is above V POR, VSUP is above ResVoltRise . VRESFALL is only accepted if the re set condition is longer than VRESMASK . This guard time is used to avoid a complete reset of the system in case of short drops of VBAT. Figure 59: VSUP Supervision VSUP Supervision: Describes the behavior of the PMIC when VSUP drops below ResVoltFall depending on OTP bit settings. SupResEn power_off_at_vsuplow auto_off Behavior if VSUP<ResVoltFall 0 x x LowBat interrupt is generated 10 0 Reset cycle is initiated, PMIC will move to “VSUP debonce” state and start-up if VSUP>ResVoltRise 10 1 Reset cycle is initiated, PMIC will move to “VSUP debonce” state and try to start-up if VSUP>ResVoltRise, if not it will go to the “Power OFF” state 11 x Reset cycle is initiated, PMIC will move to “Power OFF” state

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – System Functions Power OFF To put the chip into ultralow power mode, write ‘1’ into power_off . The chip stays in power OFF mode until it gets a wakeup signal from either the ON pin or from a charger insert. For more details see the start-up flowchart ( Figure 56 ). The bit power_off is automatically cleared by this reset cycle. During power_off state all circuits are shut-off except the Low Power LDO (V2_5). Thus the current consumption of AS3715 is reduced to about 13μA (if only supplied via VIBAT). The digital part is supplied by V2_5, all other circuits are turned OFF in this mode, including references and oscillator. Except the reset control registers all other registers are set to their default value after power-ON. Below table show the behavior of the PMIC in terms of USB pre-regulator and battery switch operation supplying VSUP when putting the PMIC into power_off state by setting power_off =1 Figure 60: Pre-Regulator and Battery Switch Operation Pre-Regulator and Battery Switch Operation: Shows the VSUP behavior under different supply conditions and settings when setting power_off=1. Software Forced Reset Writing ‘1’ into the register bit force_reset immediately starts a reset cycle. The bit force_reset is automatically cleared by this reset. External Triggered Reset If the pin XRES is pulled from high to low by an external source (e.g. microprocessor or button) a reset cycle is started as well. Over-temperature Reset The reset cycle can be started by over-temperature conditions. (see Supervisor ) # Battery USB Present chg_pwr_off_en States of VSUP_CHG 1 don’t care YES =1 PMIC enter power_off mode. Pre-regulator powered down, VSUP_CHG not powered 2 don’t care YES =0 PMIC enter power_off mode and power ON again. VSUP_CHG powered by the pre-regulator 3a IBAT attached NO don't care PMIC enter power_off mode. VSUP_CHG connected to VIBAT via the internal battery switch 3b EBAT attached NO don’t care PMIC enter power_off mode. VSUP_CHG not powered

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – System Functions Watchdog Reset If the watchdog is armed (register bit wtdg_on = 1 and wtdg_res_on = 1) and the timer expires it causes a reset. (see Watchdog ). Long ONKEY/ENx Press When applying a high level on the ONKEY or ENx input pins for 4s/8s (depending on on_reset_delay ) a reset or power_off (depending on onkey_lpress_reset) is initiated. This is thought as a safety feature when the SW hangs up and no watchdog is used. Figure 61: ONKEY/ENx Long Press Behavior ONKEY/ENx Long Press Behavior: Shows the selectable options for behaving on a long press. Reset and Power-OFF Sequence The regulator power-down sequence is inverted to the power-up sequence programmed in the OTP . It can be slightly modified by setting or clearing the sdX_sequ_on and ldoX_sequ_on bits. The bit is set automatically for all the regulators defined in the OTP start-up sequence.

• Regulators which have the corresponding sequ_on bit cleared will be shut down before the power-down sequence starts.
• Regulators which have the bit set and are in the power-up sequence of the OTP will shut down in an inverted order.
• Regulators which have the bit set and are not part of the power-up sequence will shut down after the sequence has been completed. onkey_lpress_reset on_reset_delay Long Press Behavior 0 0 power_off after 8s long press delay 0 1 power_off after 4s long press delay 1 0 reset_cycle after 8s long press delay 1 1 long press feature disabled

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – System Functions Figure 62: Regulator Power-Down Sequence Regulator Power-Down Sequence: Shows timing relationships of the regulators and corresponding control signals during power-down. all regulators not in the sequence VSUP VSUP < ResVoltFall or ONKEY lpress or power_off = 1 or force_reset = 1 or XRES = low or die temp >140°C or 4ms debounce for VSUP only Reg11_select 0, 1, 4 or 12ms delay depending on Reg11_gpio_sel and del _time off _delay = 0, 8, 16 or 32ms . . . Reg10_select 0, 1, 4 or 12 ms delay depending on Reg10_gpio_sel and del _time 0, 1, 4 or 12ms delay depending on Reg2_gpio _sel and del_timeReg2_select Reg1_select XRES

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – System Functions Stand-By Stand-By allows shutting down a part or the complete system. Stand-By can be terminated by every possible interrupt or GPIO of the PMU. The interrupt has to be enabled and GPIO has to be configured before going to stand-by. Figure 65: Stand-By Stand-By: Shows different options to enter and leave the stand-by state. State Description Enter via GPIO To enter stand-by mode the following settings have to be done:

• Enable just these IRQ sources which should lead to leave stand-by mode.
• Make sure that IRQ is inactive (IRQ flags get cleared by register reading)
• Set the GPIO to input (gpioX_mode = 0)
• Set the GPIO for stand-by control (gpioX_iosf = 6)
• Set regX_select and regX_voltage if another voltage is needed during stand-by for up to 3 regulators
• Define which regulators should be kept powered during stand-by (sdX_stby_on and ldoX_stby_on)
• Activate the selected GPIO (set to HIGH) Enter via SW To enter stand-by mode the following settings have to be done:
• Enable just these IRQ sources which should lead to leave stand-by mode.
• Make sure that IRQ is inactive (IRQ flags get cleared by register reading)
• Set regX_select_stby and regX_voltage_stby if another voltage is needing during stand-by for up to 7 regulators
• Define which regulators should be kept powered during stand-by (sdX_stby_on and ldoX_stby_on)
• Set the delay for going into stand-by after the SW command (off_delay)
• set standby_mode to 1 Stand-By V2_5 chip supply is kept ON All other regulators are switched OFF dependent on the bits sdX_stby_on and ldoX_stby_on XRES_OUT goes active (can be disabled with standby_reset_disable in the boot OTP) and pwr_good goes inactive Leave The chip will come out of stand-by with
• IRQ activation (use the GPIO restart interrupt (gpio_restart_int) to leave with the same GPIO you entered stand-by)
• ONKEY/ENx = High Start-Up sequence is provided defined by the boot OTP

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – System Functions GPIO Pins The device contains 8 GPIO pins. Each of the pins can be configured as digital input, digital input (with pull-up or pull-down), ADC input (tri-state only for GPIO3,4,7 & 8), push-pull output (selectable lowe r or higher GPIO supply), or open drain output (with or wit hout pull-up). When configured as output the output source can be a register bit, or the PWM generator. The polarity of the input and output signals can be inverted with the corresponding gpioX_invert bit, all further descriptions refer to normal (non-inverted) mode. GPIO7 & 8 have no special IO functionality, they just provide gpioX_in/out function. Figure 68: GPIO Functions GPIO Functions: Gives an overview which functions are available on which GPIOs. Function GPIO 1 2 3 4 5 6 7 8 Accessible via OTP during start-up x x x x Accessible during stand-by entry/leave x x x x Regulator ON/OFF control configurable in OTP x Regulator ON/OFF control configurable after start-up x x x I O s p e c i a l f u n c t i o n s a v a i l a b l e xxxxxx ADC input function x x x x

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – System Functions Figure 69: GPIO Block Diagram GPIO Block Diagram: Shows the internal structure of the IO pads. IO Functions Normal IO Operation If set to input, the logic level of the signal present at the GPIOx pin can be read from gpioX_in . If the output mode is chosen, gpioX_out specifies the logic level of the GPIOx pin. This mode is also used for the ON/OFF control of the DCDC and LDOs. The selection which regu lator is controlled by which GPIO, is done with the gpio_ctrl_sdX or gpio_ctrl_ldoX bits. The gpioX_mode should be set to input. Interrupt Output GPIOx pin logic state is derived from the interrupt signal INT. Whenever an interrupt is present, the GPIOx pin is pulled high. The gpioX_mode should be set to output. VSUP_low Output GPIOx pin will go high if VSUP falls below ResVoltFall and SupResEn = 0. The gpioX_mode should be set to output. GPIO Interrupt Input A falling or rising edge will set the gpio_int bit. The gpioX_mode should be set to input. .g( .g– .g 0 .g( .g( .g(

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – System Functions Current Sink PWM Input The GPIO is used as PMW input for the current sink to control the current. 100% PWM mode will set the current to the value set by currX_current . The PWM control has to be enabled by currX_ctrl =11b for each current sink to be controlled. The gpioX_mode should be set to input. Vselect Input As long as the GPIOx pin is low the DCDC/LDOs operate with the normal register settings. If the GPIOx pin goes high the settings will change to the ones stored in regX_voltage . The gpioX_mode should be set to input. The regulator affected by this mode is selected by regX_select. While GPIO3 to GPIO6 always control all regulators selected by regX_select, GPIO1 and GPIO2 may be used to control two regulators separately: Figure 70: GPIO Vselect Modes GPIO Vselect Mode: Shows the different GPIO voltage control modes for regulators. Stand-By and Vselect Input This mode is very similar to th e Vselect mode described in the previous paragraph. In addition to switch between 2 register settings of 3 regulators, the chip is set to stand-by mode when the GPIOx pin goes high and wakes up again when the pin is pulled low. The gpioX_mode should be set to input. Only one GPIO is needed to control the stand-by function and voltage setting of all 3 selectable regulators. It’s not recommended to set this mode ( gpioX_iosf=6 ) for more than one GPIO at the same time. It’s not possible to control the regulators by different GPIOs. PWRGOOD Output This signal will go high at the end of the start-up sequence. This can be used as a second reset si gnal to the processor to e.g. start oscillators. The gpioX_mode should be set to output. gpio1_iosf gpio2_iosf Vselect Mode ≠ 5 ≠ 5 No voltage select by GPIO for regulator ≠ 5 5 GPIO2 controls regulator selected by reg1_select, reg2_select and reg3_select 5≠ 5 GPIO1 controls regulator selected by reg1_select, reg2_select and reg3_select

55 GPIO1 controls regulator selected by reg1_select

GPIO2 controls regulator selected by reg2_select & reg3_select

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – System Functions Q32k Output When selected the GPIOx will provide the internal 32kHz oscillator frequency. The gpioX_mode should be set to output. Watchdog Input When pulling the GPIO high the watchdog will be triggered to avoid a reset cycle initiated by the watchdog. The gpioX_mode should be set to input. SU1 OC Output This output signal can be used to control an external disconnect transistor if SU1 detects an over current condition. The gpioX_mode should be set to output. Charger Active Output When selected, the GPIOx will go high if the charger is active. The gpioX_mode should be set to output. EOC Output When selected, the GPIOx will go high if the charger has reached the EOC state. The gpioX_mode should be set to output. 100/900mA Charger Input With this function the charger input current limiter can be set to 100 or 900mA (low power or high power USB limit). The gpioX_mode should be set to input. 900mA/2.5A Charger Input With this function the charger input current limiter can be set to 900mA or 2.5A (high power USB limit or full current enabled). The gpioX_mode should be set to input. Charging Enable Input When pulling the GPIO to high the charger is be ing enabled and vice versa. This is to enable the charger without I²C communication. The gpioX_mode should be set to input. PWM Output The GPIO block includes an internal programmable PWM generator (can be connected to any of the GPIO outputs). Its timing is defined by pwm_h_time , pwm_l_time and pwm_div . The gpioX_mode should be set to output.

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – System Functions Parameter Figure 71: GPIO Pin Characteristics GPIO Pin Characteristics: Shows the key electrical parameter of the GPIO pins. VSUP=2.7 to 5.5V; Tamb = -20 to 70°C; unless otherwise mentioned. Supervisor All LDO’s, the DCDC step ups and DCDC step downs have an integrated over-current protection. An over-temperature protection of the chip is also integrated which can be switched ON with the serial interface signal temp_pmc_on (enabled by default; it is not recommended to disable the over-temperature protection). Temperature Supervision (Main Die) The chip has two signals for the serial interface: ov_temp_110 and ov_temp_140 . The flag ov_temp_110 is automatically reset if the over-temperature condition is removed, whereas ov_temp_140 has to be reset by the serial interface with the signal rst_ov_temp_140 . If the flag ov_temp_140 is set, an automatic reset of the complete chip is initiated. The chip will only start-up when the temperature falls below the T 110 level (including hysteresis). The flag ov_temp_140 is not affected by this reset cycle allowing the software to detect the reason for this unexpected shutdown. Symbol Parameter Conditions Min Typ Max Unit VOL Low level output voltage IOL=1mA; digital output –0.3 0.4 V VOH High level output voltage IOH=–1mA; digital push-pull output 0.8 VSUP_G PIO VSUP_G PIO V VIL Low level input voltage Digital input –0.3 0.4 V VIH High level input voltage Digital input 1.4 VSUP_G PIO V ILEAKAGE Leakage current High impedance 10 μA Rpull-up Pull-up resistance If enabled; VSUP_GPIO=3.6V 300 kΩ Rpull-down Pull-down resistance If enabled; VSUP_GPIO=3.6V 300 kΩ

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – System Functions Figure 72: Temperature Supervision Characteristics Temperature Supervision Characteristic: Shows the key electrical parameter of the over-temperature supervision. Temperature Supervision SD4 (Sub Die) A similar supervision is installed for the power stage controlled by SD4. temp_sd4_alarm and temp_sd4_shutdown are indicating a >110°C or >140°C temperature condition of the sub die. For both events an interrupt can be triggered. With mask_ovtemp =0 reaching 140°C is initiating a reset cycle. If mask_ovtemp =1 only an interrupt is generated (if enabled) Watchdog The purpose of the watchdog is to detect a deadlock of the software. If the watchdog is active, it must receive a continuous trigger signal within a programma ble time window. If there is no signal anymore for a certain time period from a defined pad or special serial interface bit, it starts either a complete reset cycle or initiates the power OFF sequence. The watchdog is highly configurable by the following register bits:

• The complete block can be switched ON by wtdg_on = 1 and OFF by wtdg_on = 0.
• The watchdog time window is defined by the register wtdg_timer between 1s and 128s.
• The trigger signal can be ei ther triggered by setting wtdg_sw_sig or using a HW signal on one of the GPIO pins (gpioX_iosf =9).
• If the watchdog expires, the system can start automatically a reset cycle if wtdg_reset_on = 1 and wtdg_pweroff = 0, or perform a power down if wtdg_reset_on = 1 and wtdg_pweroff = 1.
• If wtdg_reset_on = 0 and wtdg_pweroff = 0 only an interrupt is generated (if the interrupt is enabled)
• Whether the watchdog caused a reset can be seen in the reset_reason . Symbol Parameter Conditions Min Typ Max Unit T110 ov_temp_110 rising threshold 95 110 125 ºC T140 ov_temp_140 rising threshold 125 140 155 ºC Thyst ov_temp_110 and ov_temp_140 hysteresis 5º C

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Detailed Description – System Functions Interrupt Generation The interrupt controller generates an interrupt request for the host controller as soon as one or more of the bits in the Interrupt 1 to 3 register are set by pulling high pin INT (INT has to be selected as GPIO output function). The output polarity can be changed to active low (XINT) by using the gpioX_invert bit of the selected GPIO. All the interrupt sources can be enabled in the Interrupt Mask 1 to 3 register. The Interrupt 1 to 3 registers are cleared automatically after the host controller has read them. To prevent the AS3715 device from losing an interrupt event, the register that is re ad is captured before it is transmitted to the host controller via the serial interface. As soon as the transmission of the captured value is complete a logical AND operation with the bit wise inverted captured value is applied to the register to clear all interrupt bits that have already been transmitted. Clearing the read interrupt bits takes 2 clock cycles, a read access to the same register before the clearing process has completed will yield a value of ‘0’ . Note that an interrupt that has been present at the previous read access will be cleared as well in case it occurs again before the clearing process has completed.

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – System Functions 10-Bit ADC This general purpose ADC can be used for measuring several voltages and currents to perform functions like battery monitor, temperature supervision, bu tton press detection, etc. Figure 73: ADC Input Sources ADC Input Sources: Shows the various inputs with the corresponding resolution which can be measured by the internal ADC. # Source Range LSB Mode Description 0 BATTEMP 1.8V 1.76mV 1:1 Check battery charging temperature 1 DIE temperature 1.8V 1.76mV 1:1 Tj = (0.866 * ADC10<9:0>) - 274 2 CHGIN2 5.5V 7.03mV 4:1 3 CURR1 1.0V 1.76mV 1:1 4 CURR2 1.0V 1.76mV 1:1 5 CURR3 1.0V 1.76mV 1:1 6 VUSB1 15V 26.4mV 15:1 Check USB charger HV input 7 CHGIN1 5.5V 7.03mV 4:1 Check USB charger LV input 8 VIBAT 5.5V 7.03mV 4:1 Check Li-Ion battery voltage 9 VSUP 5.5V 7.03mV 4:1 Check main system supply voltage A VEBAT 5.5V 7.03mV 4:1 Check 2nd Li-Ion battery voltage B GPIO3 1.8V / 5.5V 1.76 / 7.03mV 1:1 / 4:1 C GPIO4 1.8V / 5.5V 1.76 / 7.03mV 1:1 / 4:1 D GPIO7 1.8V / 5.5V 1.76 / 7.03mV 1:1 / 4:1 E GPIO8 1.8V / 5.5V 1.76 / 7.03mV 1:1 / 4:1 FR e s e r v e d

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Detailed Description – System Functions Serial Control Interfaces I²C Feature List

• Fast mode capability (max . SCL-frequency is 400kHz)
• 7+1-bit addressing mode
• 60h x 8-bit data registers (word address 0x00 - 0x60)
• Write formats: Single-Byte-Write, Page-Write
• Read formats: Current-Addr ess-Read, Random-Read, Sequential-Read
• SDA input delay and SCL spike filtering by integrated RC-components I²C Protocol Figure 76: I²C Symbol Definition I²C Symbol Definition: Shows the symbols used in the following mode descriptions. Symbol Definition RW Note S Start condition after stop R 1 bit Sr Repeated start R 1 bit DW Device address for write R 1000 0000b (80h) DR Device address for read R 1000 0001b (81h) WA Word address R 8 bit A Acknowledge W 1 bit N No Acknowledge R 1 bit reg_data Register data/write R 8 bit data (n) Register data/read W 8 bit P Stop condition R 1 bit WA++ Increment word address internally R During acknowledge

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Register Overview Figure 83: Register Overview 00h SD1Voltage sd1_frequ sd1_vsel<6:0> 01h SD2Voltage sd2_frequ sd2_vsel<6:0> 02h SD3Voltage sd3_frequ sd3_vsel<6:0> 03h SD4Voltage sd4_low_power sd4_vsel<6:0> 04h LDO1Voltage ldo1_on ldo1_ilimit - ldo1_vsel<4:0> 05h LDO2Voltage ldo2_on ldo2_ilimit - ldo2_vsel<4:0> 06h LDO3Voltage ldo3_ilimit ldo3_vsel<6:0> 07h LDO4Voltage ldo4_ilimit ldo4_vsel<6:0> 08h LDO5Voltage ldo5_ilimit ldo5_vsel<6:0> 09h LDO6Voltage ldo6_ilimit ldo6_vsel<6:0> 0ah LDO7Voltage ldo7_ilimit ldo7_vsel<6:0> 0bh LDO8Voltage ldo8_ilimit ldo8_vsel<6:0> 0ch GPIO1control gpio1_invert gpio1_iosf<6:3> gpio1_mode<2:0> 0dh GPIO2control gpio2_invert gpio2_iosf<6:3> gpio2_mode<2:0> 0eh GPIO3control gpio3_invert gpio3_iosf<6:3> gpio3_mode<2:0> 0fh GPIO4control gpio4_invert gpio4_iosf<6:3> gpio4_mode<2:0> Register Description

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description 10h SDcontrol - sd4_force_pwm sd1_force_ pwm sd4_enable sd3_enable sd2_enable sd1_enable 11h LDOcontrol - ldo8_enable ldo7_enable ldo6_enable ldo5_enable ldo4_enable ldo3_enable 20h GPIOsignal_out gpio8_out gpio7_out gpio6_out gpio5_out gpio4_out gpio3_out gpio2_out gpio1_out 21h GPIOsignal_in gpio8_in gpio7_in gpio6_in gpio5_in gpio4_in gpio3_in gpio2_in gpio1_in 22h Reg1_Voltage Reg1_voltage<7:0> 23h Reg2_Voltage Reg2_voltage<7:0> 24h Reg_control Reg_select2<7:4> Reg_select1<3:0> 25h GPIOctrl_sd gpio_ctrl_sd4<7:6> gpio_ctrl_sd3<5:4> gpio_ctrl_sd2<3:2> gpio_ctrl_sd1<1:0> 26h GPIOctrl_ldo1 gpio_ctrl_ldo4<7:6> gpio_ctrl_ldo3<5:4> gpio_ctrl_ldo2<3:2> gpio_ctrl_ldo1<1:0> 27h GPIOctrl_ldo2 gpio_ctrl_ldo8<7:6> gpio_ctrl_ldo7<5:4> gpio_ctrl_ldo6<3:2> gpio_ctrl_ldo5<1:0> 2bh Reg3_Voltage Reg3_voltage<7:0> 2ch Reg_control3 - Reg_select3<3:0> 2dh SD4_control1 sd4_ilimit<7:6> sd4_trim_gm<5:4> sd4_lv_deb<3:2> sd4_combine_ phase sd4_phases 2eh SD4_control2 temp_sd4_ shutdown temp_sd4_alarm sdmph_clk_div<5:4> sd4_startslew<3:2> sd4_nph_auto sd4_phsw_ on 30h SD_control1 sd4_low_noise sd3_low_noise sd2_low_noise sd1_low_noise sd4_fast sd3_fast sd2_fast sd1_fast 31h SD_control2 dvm_time_sd4<7:6> dvm_time_sd1<5:4> sd3_slave sd3_fsel sd2_fsel sd2_slave 32h Battery_voltage_m onitor FastResEn SupResEn ResVoltFall<5:3> ResVoltRise<2:0> 33h Startup_Control - onkey_lpress_ reset chg_pwr_off_en power_off_ at_vsuplow

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description 34h ResetTimer - stby_reset_disable auto_off off_delay<4:3> - res_timer<1:0> 35h ReferenceControl on_reset_delay reg_low_bias_mode clk_div2 standby_mode on 36h ResetControl mask_ovtemp reset_reason<6:3> on_input power_off force_reset 37h OvertemperatureCo ntrol rst_ov_temp_ 140 ov_temp_140 ov_temp_110 temp_pmc_ on 38h WatchdogControl - wtdg_res_on wtdg_on 39h Reg_standby_mod1 disable_regpd - sd4_stby_on sd3_stby_on sd2_stby_on sd1_stby_on 3ah Reg_standby_mod2 ldo8_stby_on ldo7_stby_on ldo6_stby_on ldo5_stby_on ldo4_stby_on ldo3_stby_on ldo2_stby_on ldo1_stby_ on 3bh Reg_sequ_mod1 - sd4_sequ_on sd3_sequ_on sd2_sequ_on sd1_sequ_ on 3ch Reg_sequ_mod2 ldo8_sequ_on ldo7_sequ_on ldo6_sequ_on ldo5_sequ_on ldo4_sequ_on ldo3_sequ_on ldo2_sequ_on ldo1_sequ_ on 40h curr_control curr3_ctrl<7:4> curr2_ctrl<3:2> curr1_ctrl<1:0> 41h pwm_control_l pwm_l_time<7:0> 42h pwm_control_h pwm_h_time<7:0> 43h curr1_value curr1_current<7:0> 44h curr2_value curr2_current<7:0> 45h curr3_value curr3_current<7:0> 46h Watchdog_min_tim er wtdg_min_timer<7:0> 47h Watchdog_max_tim er wtdg_max_timer<7:0>

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description 48h WatchdogSoftwareS ignal pwm_div<7:6> - wtdg_sw_ sig 51h Stepup_control2 stepup2_v<7:3> stepup2_res stepup2_freq stepup2_on 53h Stepup_control4 - stepup2_pwm_l owf stepup2_prot_ dis stepup2_fb<1:0> 54h Stepup_control5 - stepup2_pwm_ mode stepup2_clkinv 55h CPcontrol - cp_freq cp_on 56h ADC_BATTEMP adc_battemp<7:0> 60h GPIO5control gpio5_invert gpio5_iosf<6:3> gpio5_mode<2:0> 61h GPIO6control gpio6_invert gpio6_iosf<6:3> gpio6_mode<2:0> 63h GPIO8_7control gpio8_mode<7:5> gpio8_invert gpio7_mode<3:1> gpio7_invert 67h ENsignal_in - en4_in en3_in en2_in en1_in 69h SRAM SRAM<7:0> 70h ADC_control start_conversion adc_presample adc_slow gpio_lv adc_select<3:0> 71h ADC_MSB_result result_not_ready D9_3<6:0> 72h ADC_LSB_result - D2_0<2:0> 73h RegStatus curr3_lv curr2_lv curr1_lv - sd4_lv sd3_lv sd2_lv sd1_lv 74h InterruptMask1 LowBat_int_m ovtmp_int_m onkey_int_m chdet_int_m eoc_int_m resume_int_m nobat_int_m trickle_int_ m 75h InterruptMask2 ebat_int_m temp_sd4_shutdown_ int_m temp_sd4_alarm_ m 76h InterruptMask3 chdet2_int_m en4_int_m en3_int_m en2_int_m en1_int_m gpio_restart_ int_m gpio_int_m -

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description 77h InterruptStatus1 LowBat_int_i ovtmp_int_i onkey_int_i chdet_int_i eoc_int_i resume_int_i nobat_int_i trickle_int_i 78h InterruptStatus2 ebat_int_i temp_sd4_shutdown_ int_i temp_sd4_alarm_ 79h InterruptStatus3 chdet2_int_i en4_int_i en3_int_i en2_int_i en1_int_i gpio_restart_ int_i gpio_int_i - 7fh ChargerControl0 - usb12_ feedthrough usb2_current<3:0> 80h ChargerControl1 cc_eoc_hcurr Auto_Resume bat_charging_ enable usb_current<4:1> usb_chgEn 81h ChargerVoltageCont rol vsup_min<7:6> ChVoltEOC<5:0> 82h ChargerCurrentCont rol eoc_current cc_lowlimit ConstantCurrent<5:2> TrickleCurrent<1:0> 83h Chargerconfig usb_combined usb2_on ChVoltResume temp_sel<4:3> vsup_voltage<2:0> 84h Chargerconfig2 - ebat_enable jeita_on zero_temp_on ntc_10k ntc_on 85h Chargersupervision Charging_1Hz_clk ovprot_dis dcdc_chmode charging_tmax ch_timeout<3:0> 86h ChargerStatus1 Nobat Battemp_hi EOC CVM Trickle Resume CCM ChDet 87h ChargerStatus2 usb_prt_ready_ deb temp_cond<6:4> batsw2_on batsw2_mode batsw_on batsw_ mode 88h T1_adjust - T1_adj<5:0> 89h T2_adjust - T2_adj<4:0> 8ah T3_adjust - T3_adj<4:0> 8bh T4_adjust - T4_adj<5:0> 8ch T2_T1_hyst T2_hyst<7:4> T1_hyst<3:0>

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description 8dh T4_T3_hyst T4_hyst<7:4> T3_hyst<3:0> 8eh LockRegister - charger_lock reg_lock<1:0> 90h ASIC_ID1 ID1<7:0> 91h ASIC_ID2 - revision<3:0> a7h Fuse7 del_time unique_id sequ_on - - a8h Fuse8 sd3_slave sd3_fsel sd2_fsel sd2_slave sd4_fast sd3_fast sd2_fast sd1_fast a9h Fuse9 auto_off chg_pwr_off_en res_timer<5:4> ResVoltRise<3:1> i2c_deva_ bit1 aah Fuse10 usb2_current<7:4> usb_current<3:0> abh Fuse11 power_off_at_ vsuplow ovprot_dis on_reset_delay onkey_lpress_ reset dcdc_chmode SupResEn gpio12_in_en dis_bypass ach Fuse12 Reg4_gpio_sel<7:6> Reg3_gpio_sel<5:4> Reg2_gpio_sel<3:2> Reg1_gpio_sel<1:0> adh Fuse13 Reg2_select<7:4> Reg1_select<3:0> aeh Fuse14 reg1_V<7:0>

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description afh Fuse15 reg2_V<7:0> b0h Fuse16 Reg4_select<7:4> Reg3_select<3:0> b1h Fuse17 reg3_V<7:0> b2h Fuse18 reg4_V<7:0> b3h Fuse19 Reg8_gpio_sel<7:6> Reg7_gpio_sel<5:4> Reg6_gpio_sel<3:2> Reg5_gpio_sel<1:0> b4h Fuse20 Reg6_select<7:4> Reg5_select<3:0> b5h Fuse21 reg5_V<7:0> b6h Fuse22 reg6_V<7:0> b7h Fuse23 Reg8_select<7:4> Reg7_select<3:0> b8h Fuse24 reg7_V<7:0>

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Register Overview: Shows all the available registers. b9h Fuse25 reg8_V<7:0> bah Fuse26_uniqueID0 - Reg11_gpio_sel<5:4> Reg10_gpio_sel<3:2> Reg9_gpio_sel<1:0> bbh Fuse27_uniqueID1 Reg10_select<7:4> Reg9_select<3:0> bch Fuse28_uniqueID2 reg9_V<7:0> bdh Fuse29_uniqueID3 reg10_V<7:0> beh Fuse30 _uniqueID4 ibattemp10k Reg11_select<3:0> bfh Fuse31_uniqueID5 reg11_V<7:0>

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 97: GPIO2control 2:0 gpio1_mode b011 RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pullup 5 : Input with pulldown 6 : Output/Input open drain (NMOS) with pullup, 7 : ADC input with pulldown Addr:0dh GPIO2control Bit Bit Name Default Access Bit Description 7g p i o 2 _ i n v e r t 0 R W Invert GPIO input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio2_iosf b0000 RW Select the GPIO special function 0 : Normal I/O operation 1 : Interrupt output 2 : VSUP_low output 3 : GPIO interrupt input 4 : Current sink PWM input 5 : Vselect input, (apply on RegSelect1 and RegSelect2 and RegSelect3, if GPIO1_iosf=5 then apply on RegSelect2 and RegSelect3 only) 6 : standby + Vselect + GPIO restart interrupt input 7 : pwr_good output 8 : 32 kHz output (derived from oscillator) 9 : Watchdog input 10 : Charger active output 11 : EOC output 12 : 100/841mA charger input 13 : 841mA/2.5A charger input 14 : PWM output 15 : Charging_enable input 2:0 gpio2_mode b011 RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pullup 5 : Input with pulldown 6 : Output/Input open drain (NMOS) with pullup, 7 : ADC input with pulldown Addr:0ch GPIO1control Bit Bit Name Default Access Bit Description

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 98: GPIO3control Addr:0eh GPIO3control Bit Bit Name Default Access Bit Description 7g p i o 3 _ i n v e r t 0 R W Invert GPIO input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio3_iosf b0000 RW Select the GPIO special function 0 : Normal I/O operation 1 : Interrupt output 2 : VSUP_low output 3 : GPIO interrupt input 4 : Current sink PWM input 5 : Vselect input, (apply on RegSelect1 and RegSelect2 and RegSelect3) 6 : standby + Vselect + GPIO restart interrupt input 7 : pwr_good output 8 : 32 kHz output (derived from oscillator) 9 : Watchdog input 10 : Charger active output 11 : EOC output 12 : 100/841mA charger input 13 : 841mA/2.5A charger input 14 : PWM output 15 : Charging_enable input 2:0 gpio3_mode b011 RW Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pullup 5 : Input with pulldown 6 : Output/Input open drain (NMOS) with pullup, 7 : ADC input with pulldown

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 99: GPIO4control Addr:0fh GPIO4control Bit Bit Name Default Access Bit Description 7g p i o 4 _ i n v e r t 0 R W Invert GPIO input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio4_iosf b0000 RW Select the GPIO special function 0 : Normal I/O operation 1 : Interrupt output 2 : VSUP_low output 3 : GPIO interrupt input 4 : Current sink PWM input 5 : Vselect input, (apply on RegSelect1 and RegSelect2 and RegSelect3) 6 : standby + Vselect + GPIO restart interrupt input 7 : pwr_good output 8 : 32 kHz output (derived from oscillator) 9 : Watchdog input 10 : Charger active output 11 : EOC output 12 : 100/84841 charger input 13 : 841mA/2.5A charger input 14 : PWM output 15 : Charging_enable input 2:0 gpio4_mode b011 RW Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pullup 5 : Input with pulldown 6 : Output/Input open drain (NMOS) with pullup, 7 : ADC input with pulldown

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 102: GPIOsignal_out Addr:20h GPIOsignal_out Bit Bit Name Default Access Bit Description 7 gpio8_out 0 RW This bit determines the output signal of the GPIO8 pin when selected as output source 6 gpio7_out 0 RW This bit determines the output signal of the GPIO7 pin when selected as output source 5 gpio6_out 0 RW This bit determines the output signal of the GPIO6 pin when selected as output source 4 gpio5_out 0 RW This bit determines the output signal of the GPIO5 pin when selected as output source 3 gpio4_out 0 RW This bit determines the output signal of the GPIO4 pin when selected as output source 2 gpio3_out 0 RW This bit determines the output signal of the GPIO3 pin when selected as output source 1 gpio2_out 0 RW This bit determines the output signal of the GPIO2 pin when selected as output source 0 gpio1_out 0 RW This bit determines the output signal of the GPIO1 pin when selected as output source

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 107: GPIOctrl_sd Addr:25h GPIOctrl_sd Bit Bit Name Default Access Bit Description 7:6 gpio_ctrl_sd4 b00 RW_SM Enable GPIO control of DCDC SD4. GPIO ctrl only enabled, if sd4_vsel>0 0 : No GPIO control 1 : Controlled by GPIO1 2 : Controlled by GPIO2 3 : Controlled by GPIO3 5:4 gpio_ctrl_sd3 b00 RW_SM Enable GPIO control of DCDC SD3. GPIO ctrl only enabled, if sd3_vsel>0 0 : No GPIO control 1 : Controlled by GPIO1 2 : Controlled by GPIO2 3 : Controlled by GPIO3 3:2 gpio_ctrl_sd2 b00 RW_SM Enable GPIO control of DCDC SD2. GPIO ctrl only enabled, if sd2_vsel>0 0 : No GPIO control 1 : Controlled by GPIO1 2 : Controlled by GPIO2 3 : Controlled by GPIO3 1:0 gpio_ctrl_sd1 b00 RW_SM Enable GPIO control of DCDC SD1. GPIO ctrl only enabled, if sd1_vsel>0 0 : No GPIO control 1 : Controlled by GPIO1 2 : Controlled by GPIO2 3 : Controlled by GPIO3

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 108: GPIOctrl_ldo1 Addr:26h GPIOctrl_ldo1 Bit Bit Name Default Access Bit Description 7:6 gpio_ctrl_ldo4 b00 RW_SM Enable GPIO control of LDO4. 0 : No GPIO control 1 : Controlled by GPIO1 2 : Controlled by GPIO2 3 : Controlled by GPIO3 5:4 gpio_ctrl_ldo3 b00 RW_SM Enable GPIO control of LDO3. 0 : No GPIO control 1 : Controlled by GPIO1 2 : Controlled by GPIO2 3 : Controlled by GPIO3 3:2 gpio_ctrl_ldo2 b00 RW_SM Enable GPIO control of LDO2. GPIO ctrl only enabled, if LDO2_on=1 0 : No GPIO control 1 : Controlled by GPIO1 2 : Controlled by GPIO2 3 : Controlled by GPIO3 1:0 gpio_ctrl_ldo1 b00 RW_SM Enable GPIO control of LDO1. GPIO ctrl only enabled, if LDO1_on=1 0 : No GPIO control 1 : Controlled by GPIO1 2 : Controlled by GPIO2 3 : Controlled by GPIO3

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 113: SD4_control2 Addr:2Eh SD4_control2 Bit Bit Name Default Access Bit Description 7 temp_sd4_shutdown 0 R Indicates over temperature >140deg in subdie. Reset initated if mask_ovtemp=0 6 temp_sd4_alarm 0 R Indicates over temperature >110deg in subdie 5:4 sdmph_clk_div 0 RW_SM Divide clock of SD4 by 1, 2 or 4 0 : 2.7MHz 1 : 1.35MHz 2 : 0.675MHz 3 : 0.675MHz 3:2 sd4_startslew 0 RW Sets the startup slew rate of SD4 0 : 2.5mV / us 1 : 5mV / us 2 : 10mV / us 3 : 20mV / us 1 sd4_nph_auto 0 R Status of the actual number of phases used ,if phase switching enabled 0 : 1 phase 1 : 2 phases 0 sd4_phsw_on 0 RW Switch ON automatic phase switching for sd4

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 114: SD_control1 Addr:30h SD_control1 Bit Bit Name Default Access Bit Description 7 sd4_low_noise 0 RW Enables low noise mode of SD4. If enabled smaller current pulses and output ripple is activated 0 : Normal mode. Minimum current pulses of >100mA applied in skip mode 1 : Low noise mode. Only minimum ON time applied in skip mode 6 sd3_low_noise 0 RW Enables low noise mode of SD3. If enabled smaller current pulses and output ripple is activated 0 : Normal mode. Minimum current pulses of >100mA applied in skip mode 1 : Low noise mode. Only minimum ON time applied in skip mode 5 sd2_low_noise 0 RW Enables low noise mode of SD2. If enabled smaller current pulses and output ripple is activated 0 : Normal mode. Minimum current pulses of >100mA applied in skip mode 1 : Low noise mode. Only minimum ON time applied in skip mode 4 sd1_low_noise 0 RW Enables low noise mode of SD1. If enabled smaller current pulses and output ripple is activated 0 : Normal mode. Minimum current pulses of >100mA applied in skip mode 1 : Low noise mode. Only minimum ON time applied in skip mode 3 sd4_fast 0 RW_SM Selects a faster regulation mode for SD4 suitable for larger load changes. 0 : Normal mode, Cext=10uF 1 : Fast mode, Cext=22uF required 2 sd3_fast 0 RW_SM Selects a faster regulation mode for SD3 suitable for larger load changes. 0 : Normal mode, Cext=10uF 1 : Fast mode, Cext=22uF required 1 sd2_fast 0 RW_SM Selects a faster regulation mode for SD2 suitable for larger load changes. 0 : Normal mode, Cext=10uF 1 : Fast mode, Cext=22uF required 0 sd1_fast 0 RW_SM Selects a faster regulation mode for SD1 suitable for larger load changes. 0 : Normal mode, Cext=10uF 1 : Fast mode, Cext=22uF required

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 115: SD_control2 Addr:31h SD_control2 Bit Bit Name Default Access Bit Description 7:6 dvm_time_sd4 b00 RW Time steps of DVM voltage change of SD4 If voltage of step Down is changed during operation (sdx_vsel) voltage is de/increased by single steps 10mV 0 : 0 usec, immediate change (no DVM) 1 : 1 usec time delay between steps 2 : 2 usec time delay between steps 3 : 8 usec time delay between steps 5:4 dvm_time_sd1 b00 RW Time steps of DVM voltage change of SD1 If voltage of step Down is changed during operation (sdx_vsel) voltage is de/increased by single steps 12.5/25/50mV 0 : 0 usec, immediate change (no DVM) 1 : 4 usec time delay between steps 2 : 8 usec time delay between steps 3 : 16 usec time delay between steps 3s d 3 _ s l a v e 0 R W _ S M Enables slave mode of SD3 0 : Normal mode of SD3 1 : SD3 is slave of SD2. 2 sd3_fsel 0 RW_SM Selects between high and low frequency range 0 : 2 or 3MHz frequency (selctable by sd3_frequ) 1 : 3 or 4MHz frequency (selctable by sd3_frequ) 1 sd2_fsel 0 RW_SM Selects between high and low frequency range 0 : 2 or 3MHz frequency (selctable by sd2_frequ) 1 : 3 or 4MHz frequency (selctable by sd2_frequ) 0s d 2 _ s l a v e 0 R W _ S M Enables slave mode of SD2 0 : Normal mode of SD2 1 : SD2 is slave of SD1

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 116: Battery_voltage_monitor Note(s) and/or Footnote(s): 1. If VSUP falls below ResVoltFall only an interrupt is generated (if enabled) and the uProcessor can shut down the system Addr:32h Battery_voltage_monitor Bit Bit Name Default Access Bit Description 7F a s t R e s E n 0 R W 0 : Vresetfall debounce time = 3msec 1 : Vresetfall debounce time = 4usec (tbd) 6 SupResEn 0 RW_SM 0 : A reset is generated if VSUP falls below 2.7V. (1) 1 : A reset is generated if VSUP falls below ResVoltFall 5:3 ResVoltFall b000 RW_SM This value determines the reset level ResVoltFall for falling VBAT. It is recommended to set this value at least 200mV lower than ResVoltRise 0 : 2.7V 1 : 2.9V 2 : 3.1V 3 : 3.2V 4 : 3.3V 5 : 3.4V 6 : 3.5V 7 : 3.6V 2:0 ResVoltRise b000 RO This value determines the reset level ResVoltRise for rising VBAT. It is recommended to set this value at least 200mV higher than ResVoltFall 0 : 2.7V 1 : 2.9V 2 : 3.1V 3 : 3.2V 4 : 3.3V 5 : 3.4V 6 : 3.5V 7 : 3.6V

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 117: Startup_Control Addr:33h Startup_Control Bit Bit Name Default Access Bit Description 2 onkey_lpress_reset 0 RW_SM Selects behavior for ONKEY/ENx long press 0 : Change to power_off mode 1 : Reset cycle started if on_reset_delay=0; ONKEY/ENx long press is disabled if on_reset_delay=1 1 chg_pwr_off_en 0 RO Select charger detection in power OFF mode Read only (OTP setting) 0 : Exit of Power OFF mode, if charger is detected (level detection) 1 : Exit of Power OFF mode, if charger is attached or detached 0 power_off_at_vsuplow 0 RW_SM Switch ON Power OFF mode if low VSUP is detected during active or standby mode (Pin ON= low and bit auto_off=0) 0 : If low battery is detected, continuously monitor battery voltage and startup if battery voltage is above ResVoltrise 1 : If low battery is detected, enter power OFF mode

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 118: ResetTimer Addr:34h ResetTimer Bit Bit Name Default Access Bit Description 6 stby_reset_disable 0 RW Disable Reset output signal (PIN XRES) in standby mode 0 : Normal mode, reset is active in standby mode 1 : No reset in standby mode and during exit of standby mode 5a u t o _ o f f 0 R O Defines startup behavior at first battery insertion 0 : Startup of chip if VBAT>ResVoltRise 1 : Enter power OFF mode (Startup with ON key or charger insertion) 4:3 off_delay b01 RW Set Delay between I²C command, GPIO or Reset signal for power_off, standby mode or reset and execution of that command 0 : No delay 1 : 8 msec 2 : 16 msec 3 : 32 msec 1:0 res_timer b00 RW_SM Set RESTime, after the last regulator has started 0 : RESTIME=10ms 1 : RESTIME=50ms 2 : RESTIME=100ms 3 : RESTIME=150ms

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 119: ReferenceControl Note(s) and/or Footnote(s): 1. All frequencies, timings and delays in this datasheet are based on 4MHz clk_int. Addr:35h ReferenceControl Bit Bit Name Default Access Bit Description 7 on_reset_delay 0 RW_SM Sets the ONKEY/ENx long press delay time 0 : 8 sec 1 : 4 sec if onkey_lpress_reset=0; ONKEY/ENx long press is disabled if onkey_lpress_reset=1 6 reg_low_bias_mode 0 RW_SM 5 clk_div2 0 RW_SM Divide internal clock oscillator by 2 to reduce quiescent current for low power operation 0 : Normal mode 1 : Internal clock frequency divided by two. All timings are increased by two. Switching frequency of all DCDC converters are divided by two. Reduced transient performance of DCDC converters. 4 standby_mode_on 0 RW_SM Setting to 1 sets the PMU into standby mode. All regulators are disabled except those regulators enabled by Reg_standby_mod. XRESET will be pulled to low. A normal startup of all regulators will be done with any interrupt (has to be enabled before entering standby mode). During this startup, regulators defined by Reg standby mode register are continuously ON. 3:1 clk_int b000 RW_SM Sets the internal CLK frequency fCLK used for fuel gauge, DCDCs, PWM, ... (1) 0 : 4 MHz (default) 1 : 3.8 MHz 2 : 3.6 MHz 3 : 3.4 MHz 4 : 3.2 MHz 5 : 3.0 MHz 6 : 2.8 MHz 7 : 2.6 MHz 0 low_power_on 0 RW_SM Enable low power mode of internal reference. 0 : Standard mode 1 : Low power mode - all specification except noise parameters are still valid. Iq reduced by approx. 30uA

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 120: ResetControl Addr:36h ResetControl Bit Bit Name Default Access Bit Description 7m a s k _ o v t e m p 0 R W Inhibit reset caused by over temperature of SD4 0 : Over temperature of SD4 causes reset 1 : Over temperature of SD4 causes interrupt only 6:3 reset_reason b0000 RW_SM Flags to indicate to the software the reason for the last reset 0 : VPOR has been reached (battery or charger insertion from scratch) 1 : ResVoltFall was reached (battery voltage drop below 2.75V) 2 : Software forced by force_reset 3 : Wakeup from power OFF by ON key 4 : Wakeup from power OFF by charger 5 : Reset caused by XRES pin 6 : Reset caused by overtemperature T140 7 : Reset caused by watchdog 8 : Reset caused by 8 seconds ON key press 9 : Reset caused by overtemperature T140 of subdie (SD4) 10 : Wakeup from standby mode by interrupt 11 : Wakeup from standby mode by ON key 12 : Wakeup from standby mode or power OFF by EN1 pin 13 : Wakeup from standby mode or power OFF by EN2 pin 14 : Wakeup from standby mode or power OFF by EN3 pin 15 : Wakeup from standby mode or power OFF by EN4 pin 2 on_input 0 R_PUSH1 Read:This flag represents the state of the ON pad directly Write: Setting to 1 resets the 4/8 sec. ON key reset timer 1p o w e r _ o f f 0 R W _ S M Setting to 1 starts a reset cycle, but waits after the Reg_off state for a rising edge on the pin ON or until the charger is detected 0 force_reset 0 RW Setting to 1 starts a complete reset cycle

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 141: GPIO5control Addr:60h GPIO5control Bit Bit Name Default Access Bit Description 7g p i o 5 _ i n v e r t 0 R W Invert GPIO input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio5_iosf b0000 RW Select the GPIO special function 0 : Normal I/O operation 1 : Interrupt output 2 : VSUP_low output 3 : GPIO interrupt input 4 : Current sink PWM input 5 : Vselect input, (apply on RegSelect1 and RegSelect2 and RegSelect3) 6 : standby + Vselect + GPIO restart interrupt input 7 : pwr_good output 8 : 32 kHz output (derived from oscillator) 9 : Watchdog input 10 : Charger active output 11 : EOC output 12 : 100/841mA charger input 13 : 841mA/2.5A charger input 14 : PWM output 15 : Charging_enable input 2:0 gpio5_mode b011 RW Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pullup 5 : Input with pulldown 6 : Output/Input open drain (NMOS) with pullup, 7 : ADC input with pulldown

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 142: GPIO6control Addr:61h GPIO6control Bit Bit Name Default Access Bit Description 7g p i o 6 _ i n v e r t 0 R W Invert GPIO input/output 0 : Normal mode 1 : Invert input or output 6:3 gpio6_iosf b0000 RW Select the GPIO special function 0 : Normal I/O operation 1 : Interrupt output 2 : VSUP_low output 3 : GPIO interrupt input 4 : Current sink PWM input 5 : Vselect input, (apply on RegSelect1 and RegSelect2 and RegSelect3) 6 : standby + Vselect + GPIO restart interrupt input 7 : pwr_good output 8 : 32 kHz output (derived from oscillator) 9 : Watchdog input 10 : Charger active output 11 : EOC output 12 : 100/841mA charger input 13 : 841mA/2.5A charger input 14 : PWM output 15 : Charging_enable input 2:0 gpio6_mode b011 RW Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pullup 5 : Input with pulldown 6 : Output/Input open drain (NMOS) with pullup, 7 : ADC input with pulldown

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 150: InterruptMask1 Figure 151: InterruptMask2 Addr:74h InterruptMask1 Bit Bit Name Default Access Bit Description

7 LowBat_int_m 1 RW Rising edge only

6 ovtmp_int_m 1 RW Rising edge only 5 onkey_int_m 1 RW Rising and falling edge 4 chdet1_int_m 1 RW Rising and falling edge 3 eoc_int_m 1 RW Rising and falling edge 2 resume_int_m 1 RW Rising and falling edge 1 nobat_int_m 1 RW Rising and falling edge 0 trickle_int_m 1 RW Rising and falling edge Addr:75h InterruptMask2 Bit Bit Name Default Access Bit Description 7e b a t _ i n t _ m 1 R W 0 : Interrupt enabled 1 : Interrupt masked (disabled) 6 temp_sd4_shutdown_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 5 temp_sd4_alarm_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 4 bat_temp_int_m 1 RW Rising and falling edge of high and low temp 3 sd4_lv_int_m 1 RW Rising edge only 2 sd3_lv_int_m 1 RW Rising edge only 1 sd2_lv_int_m 1 RW Rising edge only 0 sd1_lv_int_m 1 RW Rising edge only

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 152: InterruptMask3 Figure 153: InterruptStatus1 Addr:76h InterruptMask3 Bit Bit Name Default Access Bit Description 1 gpio_int_m 1 RW Rising and falling edge 2 gpio_restart_int_m 1 RW Falling edge 3 en1_int_m 1 RW Rising and falling edge 4 en2_int_m 1 RW Rising and falling edge 5 en3_int_m 1 RW Rising and falling edge 6 en4_int_m 1 RW Rising and falling edge 7 chdet2_int_m 1 RW Rising and falling edge Addr:77h InterruptStatus1 Bit Bit Name Default Access Bit Description

7 LowBat_int_i 0 POP Bit is set when VSUP drops below vres_fall

6 ovtmp_int_i 0 POP Bit is set when 110deg is exceeded 5 onkey_int_i 0 POP 4c h d e t 1 _ i n t _ i 0 P O P 3e o c _ i n t _ i 0 P O P 2 resume_int_i 0 POP 1 nobat_int_i 0 POP 0 trickle_int_i 0 POP

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 156: ChargerControl0 Addr:7fh ChargerControl0 Bit Bit Name Default Access Bit Description 4 usb12_feedthrough 0 RW 0 : Switch VSUP_CHG-CHGIN2 is OFF 1 : Switch VSUP_CHG-CHGIN2 is ON, charging with CHGIN2 is disabled 3:0 usb2_current b0100 RW_SM Sets the USB input current limit 0 : 94mA 1 : 187mA 2 : 280mA 3 : 374mA 4 : 463mA 5 : 623mA 6 : 727mA 7 : 841mA 8 : 998mA 9 : 1100mA 10 : 1395mA 11 : 1600mA 12 : 1740mA 13 : 1956mA 14 : 2230mA 15 : 2600mA

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 157: ChargerControl1 Addr:80h ChargerControl1 Bit Bit Name Default Access Bit Description 7 cc_eoc_hcurr 1 RW 0 : Low current mode for eoc- and constant-current. The current is scaled by a factor of 2/5 of the nominal current value (eoc-current-range=24 - 96mA; constant-current range=300 - 600mA) 1 : High current mode for eoc- and constant-currrent. The nominal current values are used.(refer to Reg 82h). 6A u t o _ R e s u m e 1 R W 5 bat_charging_enable 0 RW 0 : USB is supplying VSUP , but battery switch is open. USB charger regulates to Vsup_voltage 1 : Normal battery charger operation form usb charger 4:1 usb_current b0100 RW_SM Sets the USB input current limit, if not GPIO controlled 0 : 94mA (USB low current,also if gpiox_iosf=12 and gpiox=0) 1 : 187mA 2 : 280mA 3 : 374mA 4 : 463mA (USB high current,also if gpiox_iosf=12 and gpiox=1) 5 : 623mA 6 : 727mA 7 : 841mA 8 : 998mA 9 : 1100mA 10 : 1395mA 11 : 1600mA 12 : 1740mA 13 : 1956mA 14 : 2230mA 15 : 2600mA 0 usb_chgEn 1 RW ON/OFF control of USB charger input

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 158: ChargerVoltageControl Addr:81h ChargerVoltageControl Bit Bit Name Default Access Bit Description 7:6 vsup_min b01 RW Regulate down battery charging current on that level of Vsup during trickle charging and constant current charging, to prevent voltage drop on vsup 0 : 3.9V 1 : 4.2V 2 : 4.50V 3 : 4.70V 5:0 ChVoltEOC b100011 RW Sets the end-of-charge voltage level VCHOFF. Voltage levels for jeita_warm and normal state 0 : 3.50/3.50V 1 : 3.52/3.52V 4 : 3.58/3.58V 5 : 3.50/3.60V 6 : 3.52/3.62V 35 : 4.10/4.20V 47-63 : 4.34/4.44V

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 159: ChargerCurrentControl Addr:82h ChargerCurrentControl Bit Bit Name Default Access Bit Description 7 eoc_current 0 RW Sets eoc_current 0 : eoc current = trickle current 1 : eoc current = trickle current / 2 6 cc_lowlimit 1 RW Sets the range of the charging current limit in constant current mode. 0 : Normal mode Current = CCurrent 1 : Low current mode Current = CCurrent / 2 5:2 ConstantCurrent b0000 RW Sets the charging current limit in constant current mode. Current values for low current(jeita_cool or cc_lowlimit) and normal mode 0 : 350/750mA 1 : 400/800mA 2 : 400/850mA 3 : 450/900mA 4 : 450/950mA 5 : 500/1000mA 6 : 500/1050mA 7 : 550/1100mA 8 : 550/1150mA 9 : 600/1200mA 10 : 600/1250mA 11 : 650/1300mA 12 : 650/1350mA 13 : 700/1400mA 14 : 700/1450mA 15 : 750/1500mA 1:0 TrickleCurrent b01 RW Sets the charging current limit in trickle current mode. Current values for low current(jeita_cool) and normal mode 0 : 60/60mA 1 : 60/120mA 2 : 60/180mA 3 : 120/240mA

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 160: Chargerconfig Addr:83h Chargerconfig Bit Bit Name Default Access Bit Description 7 usb_combined 0 RW Enables the combined mode for USB1 with 2 PMOS in parallel for highest efficiency 0 : Combined mode for USB1 disabled 1 : Combined mode for USB1 enabled 6u s b 2 _ o n 1 R W USB1/USB2 charger selection 0 : USB1 enabled; USB2 disabled 1 : USB1 enabled; USB2 enabled; with higher priority on USB1

5 ChVoltResume 0 RW

Sets the resume voltage level VCHRES. 0 : 0.9666*VCHOFF (120mV @ 4.2V) 1 : 0.9444*VCHOFF (233mV @ 4.2V) 4:3 temp_sel b00 RW Selects temperature regulation of charging current (die temp.) 0 : 110degC 1 : 90degC 2 : 120degC 3 : 130degC 2:0 vsup_voltage b101 RW Voltage regulation of VSUP of the input current limiter 0 : 4.4V 1 : 4.5V 2 : 4.6V 3 : 4.7V 4 : 4.8V 5 : 4.9V 6 : 5.0V 7 : 5.5V

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 161: Chargerconfig2 Addr:84h Chargerconfig2 Bit Bit Name Default Access Bit Description 6 ebat_enable 1 RW_SM 0 : External battery is disabled 1 : External battery is enabled 3j e i t a _ o n 0 R W 0 : JEITA temperature supervision is OFF 1 : JEITA temperature supervision is ON 2 zero_temp_on 0 RW 0 : 0degC battery temperature supervision OFF 1 : 0degC battery temperature supervision ON 1n t c _ 1 0 k 0 R W Select NTC resistor type 0 : 100kOhm 1 : 10kOhm 0n t c _ o n 0 R W ON/OFF control of battery ntc supervision 0 : Enabled 1 : Disabled

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 162: Chargersupervision Addr:85h Chargersupervision Bit Bit Name Default Access Bit Description 7C h a r g i n g _ 1 H z _ c l k 0 R W Sets the mode for the charging output status (gpioX_iosf==10) 0 : Normal operation: charging=1, not charging=0 1 : 1Hz blinking operation: charging=1Hz, not charging=0 6 ovprot_dis 1 RW_SM Disables external overvoltage protection, function of XOFF pin 0 : Overvoltage protection enabled 1 : Overvoltage protection disabled 5 dcdc_chmode 1 RW_SM Enables dcdc charger mode 0 : Linear charger mode enabled 1 : Step down charger enabled 4c h a r g i n g _ t m a x 1 R _ P U S H 0 0 : Read: no timeout reached, Write: reset charger timeout counter 1 : Charging timeout reached and charging stopped 3:0 ch_timeout b0000 RW Sets the charger timeout timer 0 : OFF 1 : 0.5 hour 2 : 1 hour 3 : 1.5 hour 4 : 2 hour 5 : 2.5 hour 6 : 3 hour 7 : 3.5 hour 8 : 4 hour 9 : 4.5 hour 10 : 5 hour 11 : 5.5 hour 12 : 6 hour 13 : 6.5 hour 14 : 7 hour 15 : 7.5 hour

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 163: ChargerStatus1 Addr:86h ChargerStatus1 Bit Bit Name Default Access Bit Description

7 Nobat 0 RO Bit is set if no battery has been detected

6C h D e t 2 0 R O Bit is set when external charge adapter has been detected on pin VCHGIN2

5 EOC 0 RO Bit is set if End of charge state has been reached

4 CVM 0 RO Bit is set if charger is operating in constant voltage mode

3 Trickle 0 RO Bit is set, if charger is operating in trickle current. Vbat<2.9V

2 Resume 0 RO Bit is set if Battery voltage is below resume level

1 CCM 0 RO Bit is set if charger is operating in constant current mode

0C h D e t 1 0 R O Bit is set when external charge adapter has been detected on pin VCHGIN1

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 176: Fuse8 Addr:a8h Fuse8 Bit Bit Name Default Access Bit Description 7s d 3 _ s l a v e b 0 R W Enables slave mode of SD3 0 : Normal mode of SD3 1 : SD3 is slave of SD2. 6 sd3_fsel b0 RW Selects between high and low frequency range 0 : 2 or 3MHz frequency (selectable by sd3_frequ) 1 : 3 or 4MHz frequency (selectable by sd3_frequ) 5 sd2_fsel b0 RW Selects between high and low frequency range 0 : 2 or 3MHz frequency (selectable by sd2_frequ) 1 : 3 or 4MHz frequency (selectable by sd2_frequ) 4s d 2 _ s l a v e b 0 R W Enables slave mode of SD2 0 : Normal mode of SD2 1 : SD2 is slave of SD1. 3 sd4_fast b0 RW Selects a faster regulation mode for SD4 suitable for larger load changes. 0 : Normal mode, Cext=20uF 1 : Fast mode, Cext=40uF required 2 sd3_fast b0 RW Selects a faster regulation mode for SD3 suitable for larger load changes. 0 : Normal mode, Cext=10uF 1 : Fast mode, Cext=22uF required 1 sd2_fast b0 RW Selects a faster regulation mode for SD2 suitable for larger load changes. 0 : Normal mode, Cext=10uF 1 : Fast mode, Cext=22uF required 0 sd1_fast b0 RW Selects a faster regulation mode for SD1 suitable for larger load changes. 0 : Normal mode, Cext=10uF 1 : Fast mode, Cext=22uF required

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 177: Fuse9 Addr:a9h Fuse9 Bit Bit Name Default Access Bit Description 7 auto_off b0 RW Defines startup behavior at first battery insertion 0 : Startup of chip if VBAT>ResVoltRise 1 : Enter power OFF mode (Startup with ON key or charger insertion) 6 chg_pwr_off_en 0 RW_SM Enable power OFF mode, if charger is detected 0 : Exit of Power OFF mode, if charger is detected (level) 1 : Exit of Power OFF mode, if charger is attached or detached 5:4 res_timer b00 RW Set RESTime, after the last regulator has started 0 : RESTIME=10ms 1 : RESTIME=50ms 2 : RESTIME=100ms 3 : RESTIME=150ms 3:1 ResVoltRise b000 RW This value determines the reset level ResVoltRise for rising VBAT. ResVoltFall is set to ResVoltRise-2 by default 0 : 2.7V 1 : 2.9V 2 : 3.1V 3 : 3.2V 4 : 3.3V 5 : 3.4V 6 : 3.5V 7 : 3.6V 0 i2c_deva_bit1 b0 RW

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Register Description Figure 178: Fuse10 Addr:aah Fuse10 Bit Bit Name Default Access Bit Description 7:4 usb2_current b0000 RW Sets the USB2 input current limit 0 : 94mA 1 : 187mA 2 : 280mA 3 : 374mA 4 : 463mA 5 : 623mA 6 : 727mA 7 : 841mA 8 : 998mA 9 : 1100mA 10 : 1395mA 11 : 1600mA 12 : 1740mA 13 : 1956mA 14 : 2230mA 15 : 2600mA 3:0 usb_current b0000 RW Sets the USB input current limit, if not GPIO controlled 0 : 94mA (USB low current,also if gpiox_iosf=12 and gpiox=0) 1 : 187mA 2 : 280mA 3 : 374mA 4 : 463mA (USB high current,also if gpiox_iosf=12 and gpiox=1) 5 : 623mA 6 : 727mA 7 : 841mA 8 : 998mA 9 : 1100mA 10 : 1395mA 11 : 1600mA 12 : 1740mA 13 : 1956mA 14 : 2230mA 15 : 2600mA

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 179: Fuse11 Note(s) and/or Footnote(s): 1. If VSUP falls below ResVoltFall only an interrupt is generated (if enabled) and the uProcessor can shut down the system Addr:abh Fuse11 Bit Bit Name Default Access Bit Description 7 power_off_at_vsuplow b0 RW Switch ON Power OFF mode if low VSUP is detected during active or standby mode (Pin ON= low and bit auto_off=0) 0 : If low battery is detected, continuously monitor battery voltage and startup if battery voltage is above ResVoltrise 1 : If low battery is detected, enter power OFF mode 6o v p r o t _ d i s b 0 R W Enables external overvoltage protection, function of xoff 0 : Overvoltage protection disabled 1 : Overvoltage protection enabled 5o n _ r e s e t _ d e l a y b 0 R W Sets the ONKEY/ENx long press delay time 0 : 8 sec 1 : 4 sec if onkey_lpress_reset=0; ONKEY/ENx long press is disabled if onkey_lpress_reset=1 4 onkey_lpress_reset b0 RW Selects behavior for ONKEY/ENx long press 0 : Change to power_off mode 1 : Reset cycle started if on_reset_delay=0; ONKEY/ENx long press is disabled if on_reset_delay=1 3 dcdc_chmode b0 RW Selects between linear and step down charger 0 : Linear charger enabled 1 : Step down charger enabled 2S u p R e s E n b 0 R W 0 : A reset is generated if VSUP falls below 2.7V. (1) 1 : A reset is generated if VSUP falls below ResVoltFall 1g p i o 1 2 _ i n _ e n b 0 R W Enables input_pulldown for gpio1,gpio2 if this bit is set 0 : gpio1_mode and gpio2_mode are default (b011) 1 : gpio1_mode and gpio2_mode set to (b101) input with pulldown 0 dis_bypass b0 RW Used in charger FSM

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Register Description Figure 183: Fuse30 Addr:beh Fuse30 Bit Bit Name Default Access Bit Description 7:4 ibattemp10k b0000 RW BATTEMP NTC current for correction calculation Fh: 133.8uA Eh: 136.4uA Dh: 139.0uA Ch: 141.6uA Bh: 144.2uA Ah: 146.8uA 9h: 149.4uA 0h: 152.0uA 1h: 154.6uA 2h: 157.2uA 3h: 159.8uA 4h: 162.4uA 5h: 165.0uA 6h: 167.6uA 7h: 170.2uA 8h: n/a 3:0 Reg11_select b0000 RW

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Application Information Application Schematics Figure 184: Application Schematic Application Schematic: Shows basic connections and external components

Application Information

AS3715 Evalboard WLCSPA3 1.0 23.08.2013 16V 0603 C39 1μF VIN_LDO78 VIN_LDO456 VIN_LDO123 VIN_LDO123 J31 Jumper3_THMD VSUP VIN_LDO456 J30 Jumper3_THMD VSUP VIN_LDO78 J29 Jumper3_THMD VSUP VSUP VSUP VLF403215MT-100M 10μH GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PMEG4010BEA 0603 R16 0603 R18 100k GND 50V 0603 C35 1.5nF 50V 0603 C37 15nF 25V 0805 C36 2.2μF GND GND SU 0603 16V C31 470nF 5V 0603 C32 4.7μF 16V 0603 C33 1μF GND GND VSUP GND TEMP_SD4 CTRL1_SD4 CTRL2_SD4 FB_SD4_N 16V 0603 C19 2.2uF 10V 1206 C20 47μF 10V 0805 C25 10μF 10V 0805 C27 10μF TFM252010GHM 1μH 16V 0603 C21 2.2uF 16V 0603 C26 2.2uF TFM252010GHM 1μH TFM252010GHM 1μH GND GND GND GND GND GND GND GND GND SI2306BDS-T1-E3 16V 0603 C16 4.7μF 16V 0603 C17 4.7μF GNDGND V_USB1 J17short NMOS V_USB1V_USB2 16V 0603 C38 100nF GND SW_SPST2_GND GND V2_5 V2_5 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 16V 0603 C34 1μF GND VSUP SD1 SD2 SD3 TP9 SD1 1 TP10 SD21 TP11 SD3 TP12 V5_0 V5_0 V5_0 TP13 SU SCL SDA 10V 1206 C22 47μF 25V 0603 C23 10μF 16V 0603 C24 2.2uF VSUP GND GND GND TFM252010GHM 1μH PMEG4010BEA 25V 0603 C29 10μF GND VEBAT VIBAT PMEG4010BEA BATTEMP BATTEMP J27 R10k GND Q2A Q2B VEBAT GND J19 Linear mode 0603D110603D100603D90603D8 0603D150603D140603D130603D12 0603D190603D180603D170603D16 SU J24 CURR1 J25 CURR2 J26 CURR3 VSUP CTRL1_SD4 CTRL2_SD4 TEMP_SD4 FB_SD4_P FB_SD4_P LDO1 LDO2 LDO3 LDO4 LDO5 LDO6 LDO7 LDO8 1 TP16 LDO3 TP17 LDO4 TP18 LDO5 TP19 LDO6 TP20 LDO7 TP21 LDO8 TP15 LDO2 TP14 LDO1 LDO1 LDO2 LDO3 LDO4 LDO5 LDO6 LDO7 LDO8 16V 0603 C18 4.7μF GND (nm) 16V 0603 C15 4.7μF GND J18 CHGIN 25V 0603 C28 10μF GND 0603 R19 10k J28 R15k GND 0603 R13 0603D20 J32 GPIO1 0603 R21 6k8 GND GPIO1 J20 EN1 2V5 J21 EN2 2V5 J22 EN3 2V5 J23 EN4 2V5 V2_5V2_5V2_5V2_5 0603R17 1MVSUP VSUP VSUP VSUP 0603D22 J34 GPIO2 0603 R23 6k8 GND GPIO2 0603D24 J36 GPIO3 0603 R25 6k8 GND GPIO3 0603D26 J38 GPIO4 0603 R27 6k8 GND GPIO4 0603D21 J33 GPIO5 0603 R22 6k8 GND GPIO5 0603D23 J35 GPIO6 0603 R24 6k8 GND GPIO6 0603D25 J37 GPIO7 0603 R26 6k8 GND GPIO7 0603D27 J39 GPIO8 0603 R28 6k8 GND GPIO8 FDC604PQ3 ± 0.1% 0603 R20 15k GND PVSS1 B4 LX1 B3VSUP1B2 CTRL2D1 PVSS2 D4 LX2 D3VSUP2D2 TEMPB1 PVSS1 A4 LX1 A3VSUP1A2 CTRL1A1 PVSS2 C4 LX2 C3VSUP2C2 AGNDC1 AS3729 5A Power Stage SDXa*1 AS3729 GND LX1(29)-2 LX1(29)-2 LX1(29)-1 LX1(29)-1 GND GND GND GND GND GND GND10V 1206 C13 47μF (nm) 10V 1206 C14 47μF 10V 1206 C11 47μF (nm) 10V 1206 C12 47μF (nm) 10V 0805 C10 10μF 10V 0805 10μF 10V 0805 10μF (nm) 10V 0805 10μF GND XFL4012-471L1 0.47μH XFL4012-471L2 0.47μH EN1 EN2 EN3 EN4 VINLDO123 G2 LDO1 H1 LDO2 G1 LDO3 F2 LDO4 A5 LDO5 A4 LDO6 A3 VINLDO78 H5 LDO7 J4 LDO8 J5 VINLDO456 B3 EBATSWD7 XOFFC8 CHGIN1A6 VSUP_CHGA7 CHGOUTA9 VUSBE6 VEBATD3 V2_5F1 CREFF3 BATTEMPE5 ONKEYH4 SCLH3 SDAF6 XRESJ2 VSUP_GPIOJ3 GPIO1G5 GPIO2G4 GPIO3H2 GPIO4J1 CURR1J6 CURR2H6 CURR3G6 LX_SD1 H7FB_SD1 G7 VSUP_SD1 H8 LX_SD2 G9FB_SD2 E8VSUP_SD2 G8 LX_SD3 D9FB_SD3 D8VSUP_SD3 C9 FB_SD4_N B1 V5_0 E1 VSS_CP D2 CTRL1_SD4 C1 CAPN D1CAPP E2 FB_SU C5GATE_SU B2 VSUP_CP E3 SENSEP_SU D5VSUP_SU C3 TEMP_SD4 C2 AS3715 VSS_SD1 J8 VSS_SD2 F9 VSS_SD1 J9 VSUP_SD1 H9 VSS_SD3 E9 CTRL2_SD4 D4 FB_SD4_P C4 SD1 VSS_SU A1 SENSEN_SU A2 LX_SD1 J7 Dual Power Path PMIC OVP Limiter CHGIN1B6 CHGIN2A8 CHGIN2B8 Charger IBATSWC7 VIBATE4 CHGOUTB9 VSUP_CHGB7 I2C GPIOGPIO5G3 GPIO6F5 GPIO7F4 GPIO8B4 Control & Ref EN1C6 EN2B5 EN3E7 EN4D6 LDO1-8 VSS_ANAF7 VSSAF8 SINK SD2 SD3 SD4 CP BOOST AS3715 16V 0603 C30 2.2uF 16V 0603 C40 2.2uF 16V 0603 C41 2.2uF 16V 0603 C42 2.2uF 16V 0603 C43 2.2uF 16V 0603 C44 2.2uF 16V 0603 C45 2.2uF 16V 0603 C46 2.2uF 16V 0603 C47 2.2uF 16V 0603 C48 2.2uF 16V 0603 C49 2.2uF 16V 0603 C50 2.2uF 0603 0603 R14 0805 250mW R15 0R15 SI1304BDL-T1-E3 FB_SD1 LX_SD1 FB_SD2 FB_SD3 LX_SD2 LX_SD3 VSUP_CP CAPP CAPN VSUP_SU SENSEN_SU GATE_SU FB_SU CURR1 CURR2 CURR3 ONKEY XRES CREF V2_5 VIBAT CHGOUT XOFF CHGIN1 CHGIN2 EBATSW IBATSW 0603 0603 0603 (nm) 0603 R29 CTRL1 CTRL2 CTRL1 CTRL2 0603 R10 0603 R11 0603 R12 FB_SD4_P GND VSUP_SU GND 16V 0603 C51 1μF TP22 SD4 J41 Stipline3 J40 Stipline3 GND FB_SD4_P VSUP_GPIO SD2 SD3 SD3 R30 R31 1(nm) TP24 1(nm) TP25

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Application Information PCB Routing Recommendations Internal DCDC Attention should be paid to the routing of the VSUP , LX and GND traces of the DCDC converter.

• Keep the VSUP traces to the input capacitor as short as possible. Do not use vias for this connection.
• Make a common ground area fo r the input cap, output cap and PVSS terminal of the DCDC . Connect this ground area with vias to the system ground plane.
• Use short wide traces for LX no de. If you need to set vias, use it on the LX trace and not on the capacitor connections. Power Stage Connections To avoid cross talk to other lines a minimum spacing of minimum 3W should be kept. For a proper DCDC operation it’s recommended to avoid routing other clock traces being routed in parallel (also on other layers) to the control lines. Figure 185: PCB Control Line Routing PCB Control Line Routing: Shows an example PCB routing for the control lines of the multiphase controllers. CTRL1&2, are not interfering wi th each other as they are running at 180° phase shift. They can be routed with a minimum spacing. The TEMP lines should be used as “guard traces” to other control line pairs (e.g. CTRL3&4 or CTRL 5&6 or CTRL 7&8) as well as to other sensitive or clock traces on the PCB. A minimum spacing of >1.5W should be used as spacing bet ween TEMP and CTRL traces. CTRL1 GND H εr W ≥ 3W > 1W CTRL2 W> 1. 5W TEMP1 W> 1.5W CTRL3 W> 1W CTRL 4 W

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Application Information To minimize the cross talk of these clock lines, the width of the traces (W) should be the minimum acceptable width for manufacturing (e.g. 4mil).The di fferential feedback lines are less critical, nevertheless to en sure a good coupling between the differential lines and a low coupling to other traces and ground planes its recommended to have: S<W, S<H, X≥2W and 2S Figure 186: PCB Differential Feedback Routing PCB Differential Feedback Routing: Shows an example PCB routing for the differential feedback lines of the multiphase controllers. FB_ N W FB_P S W X GND H εr

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Package Drawings & Markings Figure 187: Package Drawing (WL-CSP) Note(s) and/or Footnote(s): 1. Pin 1 = A1 2. ccc Coplanarity 3. All dimensions are in μm Package Drawings & Markings Green RoHS

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Package Drawings & Markings Figure 188: Package Marking Marking: Shows the package marking for different product versions. Figure 189: Package Code Package Code: Shows the coding of the package marking. Figure 190: Start-Up Revision Code Start-Up Revision Code: Shows the coding of the different startup sequences. YY WW I ZZ Year Manufacturing week Plant identifier Free choice xx Sequence ES Engineering samples, no sequence prog rammed or sequence programmed on request

00 Standard programming (no sequence programmed)

xx Other customer specified sequence programmed during production test YYWWIZZ AS3715 J2V2-ES YYWWIZZ AS3715 J2V2-xx

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Ordering & Contact Information Figure 191:

Ordering Information

Ordering Information: Shows the ordering information for the different product versions Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbaderstrasse 30

8141 Unterpremstaetten

Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code Marking OTP programming Delivery Form Package AS3715-BWLW-ES J2V2-ES Sequence programmable on request Waffle Pack 81-pin WL-CSP 0.4mm pitch AS3715-BWLT-xx J2V2-xx Other customer specified programming Tape & Reel 81-pin WL-CSP 0.4mm pitch Ordering & Contact Information

Document Feedback [v1-03] 2015-Aug-10 AS3715 − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specif ied lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are unde rway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to prov ide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appe aring in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding th e information set forth herein. ams AG reserves the right to ch ange specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any th ird party shall arise or flow out of ams AG rendering of technical or other services. Copyrights & Disclaimer

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Revision Information Note(s) and/or Footnote(s): 1. Page and figure numbers for the previous version may diff er from page and figure numbers in the current revision. 2. Correction of typographical er rors is not explicitly mentioned. Changes from 1-00 (2014-Sep-10) to current revision 1-03 (2015-Aug-10) Page 1-00 (2014-Sep-10) to 1-01 (2014-Sep-10) Added LDO noise parameter, updated LDO block diagrams Corrected max output voltage for LDO7&8 Updated Figure 2 3 Updated Figure 4 5 Updated SD4 efficiency curves 24 Corrected GPIO Vselect description 67 1-01 (2014-Sep-10) to 1-02 (2015-Jul-21) Updated Figure 4 5 Updated Figure 5 9 Updated summary of Figure 40 39 Updated text under Constant Current Charging 44 Corrected text under Figure 47 47 Corrected text above Figure 51 51 1-02 (2015-Jul-21) to 1-03 (2015-Aug-10) Removed Confidential Updated Figure 5 9 Revision Information

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Content Guide

1 General Description

1 Key Benefits and Features

2 Applications

3 Block Diagram

4 Pin Assignments

9A b s o l u t e M a x i m u m R a t i n g s

12 Typical Operating Characteristics

13 Detailed Descriptio n – Power Management

13 DCDC Step-Down Converter

13 Description

14 Mode Settings

14 Low Ripple, Low Noise Operation

15 High Efficiency Operation (Default Setting)

16 Power Save Operation (A utomatically Controlled)

16 DVM (Dynamic Voltage Management)

17 Fast Regulation Mode

17 Selectable Frequency Operation

17 100% PMOS ON Mode for Low Dropout Regulation

17 Step-Down Converter Configuration Modes

17 Parameter

20 DCDC Step-Down Controller

20 Description

21 Mode Settings

21 Low Ripple, Low Noise Operation

21 High Efficiency Operation (Default Setting)

21 Low Power Operation (sdX_low_power=1)

21 Power Save Operation (A utomatically Controlled)

22 Force PWM Mode Operation

22 Fast Regulation Mode

22 100% PMOS ON Mode for Low Dropout Regulation

22 DVM (Dynamic Voltage Management)

23 Parameter

27 Analog LDO Regulators

27 Description

28 Parameter

29 Universal IO LDO Regulators

29 Description

30 Parameter

31 Low Power LDO V2_5 Regulator

31 Description

31 Parameter

32 DCDC Step-up Converter

32 Description

34 Feedback Selection

34 Current Feedback

34 Current Feedback with Au tomatic Feedback Selection

34 Voltage Feedback

34 Calculating Resistors fo r Voltage Feedback or

36 Parameter

[v1-03] 2015-Aug-10 Document Feedback AS3715 − Content Guide

38 Current Sinks

38 Description

38 Parameter

39 Charge Pump

39 Description

39 Parameter

40 Charger

40 Description

44 Charging Cycle Description

44 Charger Adapter Detection

44 Soft Charging

44 Low Current (Trickle) Charging

44 Constant Current Charging

44 Constant Voltage Charging

45 Stop Charging Conditions

46 Battery Presence Indication

46 Charger Overvoltage Protection

46 NTC Supervision

46 NTC ß-Correction

48 Charger MIN/MAX Temp Supervision

49 Charger JEITA Temp Supervision

49 Dual Battery Switching

51 Dual Power Path

52 Parameter

55 Detailed Descriptio n – System Functions

55 Start-Up

56 Normal Startup

57 Start-Up Reasons

57 Parameter

57 Reset

57 Description

58 Reset Reasons

58 Voltage Detection:

59 Power OFF

59 Software Forced Reset

59 External Triggered Reset

59 Over-temperature Reset

60 Watchdog Reset

60 Long ONKEY/ENx Press

60 Reset and Power-OFF Sequence

62 Parameter

63 Stand-By

63 Description

64 Internal References

64 Description

64 Low Power Mode

64 Parameter

65 GPIO Pins

65 Description

66 IO Functions

66 Normal IO Operation

66 Interrupt Output

66 VSUP_low Output

Document Feedback [v1-03] 2015-Aug-10 AS3715 − Content Guide

66 GPIO Interrupt Input

67 Current Sink PWM Input

67 Vselect Input

67 Stand-By and Vselect Input

67 PWRGOOD Output

68 Q32k Output

68 Watchdog Input

68 SU1 OC Output

68 Charger Active Output

68 EOC Output

68 100/900mA Charger Input 68 900mA/2.5A Charger Input

68 Charging Enable Input

68 PWM Output

69 Parameter

69 Supervisor

69 Temperature Supervision (Main Die)

70 Temperature Supervision SD4 (Sub Die)

70 Watchdog

70 Description

71 Interrupt Generation

71 Description

72 Description

73 Parameter

74 Serial Control Interfaces

74 I²C Feature List

74 I²C Protocol

75 I²C Write Access

76 I²C Read Access

77 I²C Parameter

78 Register Description

78 Register Overview

86 Detailed Register Description

147 PCB Routing Recommendations

147 Internal DCDC

147 Power Stage Connections

152 RoHS Compliant & ams Green Statement

153 Copyrights & Disclaimer

154 Document Status