AS3412 AMSOSRAM | Alldatasheet
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[v1-00] 2016-Apr-06 Document Feedback AS3412 Ultra Small ANC Speaker Driver The AS3412 is a speaker driver with Ambient Noise Cancelling function for headsets, headphones or ear pieces. They are intended to improve quality of e.g. music listening, a phone conversation etc. by reducing background ambient noise. The fully analog implementation allows the lowest power consumption, lowest system BOM cost and most natural received voice enhancement otherwise difficult to achieve with DSP implementations. The device is designed to be easily applied to existing architectures. An internal OTP-ROM can be optionally used to store the microphones gain calibration settings. The AS3412 can be used in different configurations for best trade-off in terms of noise cancellation, required filtering functions and mechanical designs. The AS3412 targeting feed-forward topology is used to effectively reduce frequencies typically up to 2-3 kHz. The filter loop for the system is determined by measurements, for each specific headset indivi dually, and depends very much on mechanical designs. The gain and phase compensation filter network is implemented with cheap resistors and capacitors for lowest system costs. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of this device are listed below: Figure 1: Added Value of Using AS3412
Applications
The devices are ideal for Ear Pieces, Headsets, Hands-Free Kits, Mobile Phones, and Voice Communicating Devices. Benefits Features
- Low noise floor • Low noise amplifiers
- Integrated music bypass switch • Depletion mode transistors for passive music bypass
- Smallest ANC form factor • WL-CSP package (2.2x2.2mm, 0.4mm pitch) General Description
Document Feedback [v1-00] 2016-Apr-06 AS3412 − General Description Block Diagram The functional blocks of the AS3412 are shown below: Figure 2: Functional Blocks of AS3412 AS3412 Block Diagram: This figure shows the functional blocks of the AS3412. VBAT CPN CPP GND VNEG Charge Pump MICS MICL VMIC VMIC VMIC VNEG I2C On/Off/Monitor/PBO VBA T LINL LINR MICR ANC Filter Left ANC Filter Right QMICR IOP1R QOP1R QMICL IOP1L QOP1L HPL HPR AGND ANC/CSDA MODE/CSCL ANC Processing MIC Supply TRSCL/BPR Musi c Bypass Musi c Bypass MUTE MUTE CVBA T CFL Y CVNEG CMI CS CMI CL CMI CR AS3412 TRSDA/BPL CACR CACL MICACLMICACR 3 x PROM
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Pin Assignment TRSCL/ BPR E1 ANA IN/OUT Clock input for production trimming. Can be connected to LINR pin to enable production trimming via 3.5mm audio jack. Furthermore this pin features also music bypass function for the right audio channel in off mode operation in order to replace an external analog switch. LINR C2 ANA IN Line input EQ right channel. ANC / CSDA C5 DIG IN Serial interface data for I²C interface and ANC control to enable/disable ANC. MODE / CSCL D5 DIG IN Serial Interface Clock for I²C interface and control pin for power up/down and Monitor mode. MICACL E3 ANA OUT Microphone preamplifier AC coupling ground terminal. This pin requires a 10μF capacitor connected to AGND pin. MICL D4 ANA IN ANC micropho ne input left channel. MICS E4 SUP OUT Microphone Supply output. This pin needs an output blocking capacitor with 10μF. MICR C4 ANA IN ANC microphone pr eamplifier input right channel. MICACR E5 ANA OUT Microphone preamplifier AC coupling ground terminal. This pin requires a 10μF capacitor connected to AGND pin. QMICR A5 ANA OUT ANC microphone preamplifier output right channel. IOP1R B4 ANA IN ANC filter OpAmp1 input right channel. QOP1R A4 ANA OUT ANC filter OpAmp1 output right channel. HPL B2 ANA OUT Headphone amplifier output left channel HPR D1 ANA OUT Headphone amplifier output right channel VBAT B1 SUP IN Positive supply terminal of IC. CPP A1 ANA OUT V NEG charge pump flying capacitor positive terminal. GND A2 GND VNEG charge pump ground terminal. Has to be connected to AGND pin. For better noise performance a star shaped ground concept is the preferred option to connect these pins together. CPN B3 ANA OUT V NEG charge pump flying capacitor negative terminal. VNEG A3 SUP OUT VNEG charge pump output. QOP1L D2 ANA IN Filter OpAmp1 output left channel. IOP1L D3 ANA OUT Filter OpAmp1 input left channel. QMICL E2 SUP IN ANC microphone preamplifier output left channel. Pin Name Pin Number Pin Type Description
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Symbol Parameter Min Max Units Comments Electrical Parameters VGND_MAX Ground Terminals -0.5 0.5 V Applicable for pin AGND and GND VSUP_MAX Supply Voltage to Ground -0.5 2.1 V Applicable for pin VBAT VNEG_MAX Negative Terminals -2.0 0.5 V Applicable for pin VNEG VCP_MAX Charge Pump Terminals VNEG-0.5 V NEG+0.5 V Applicable for pins CPN and CPP VHP_MAX Headphone Pins VNEG-0.5 V NEG+0.5 V Applicable for pins HPR and HPL VANA_MAX Analog Pins VNEG-0.5 V NEG+0.5 V Applicable for pins LINL, LINR, MICL/R, HPR, HPL, QMICL/R, IOP1x, QOP1x, CPP , CPN, TRSCL/BPR, TRSDA/BPL, MICACL and MICACR V CON_MAX Control Pins VNEG-0.5 5V Applicable for pins ANC/CSDA and MODE/CSCL VOTHER_MAX Other Pins VNEG-0.5 5 V Applicable for pins MICS ISCR Input Current (latch-up immunity) (1) (2) ±100 mA JEDEC 17 Continuous Power Dissipation (TA = 70°C) PT Continuous power dissipation - tbd mW Electrostatic Discharge ESDHBM Electrostatic Discharge HBM ± 2000 V JEDEC JESD22-A114C Temperature Ranges and Storage Conditions RTHJA Junction to Ambient Thermal Resistance tbd tbd °C/W Absolute Maximum Ratings
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Absolute Maximum Ratings Note(s): 1. Latch-up test was performed with VBAT supplied and both AGND and GND grounded. 2. VNEG, CPP , CPN, MICACL and MICACR are not Latch-up stressed because these are passive pins. TJ Operating Junction Temperature 85 °C TSTRG Storage Temperature Range -55 125 °C TBODY Package Body Temperature 260 °C IPC/JEDEC J-STD-020 The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices. ” RH NC Relative Humidity (non-condensing) 58 5 % MSL Moisture Sensitivity Level 1 Unlimited floor lifetime Symbol Parameter Min Max Units Comments
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Electrical Characteristics VBAT = 1.6V to 1.8V, T A = -20ºC to 85ºC. Typical values are at VBAT = 1.6V, TA = 25ºC, unless otherwise specified. All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 6: Symbol Parameter Condition Min Max Unit TA Ambient Temperature Range -20 85 °C Supply Voltages GND Reference Ground 0 0 V V BAT Battery Supply Voltage 1.6 1.8 V VNEG Charge Pump Voltage -1.8 -1.45 V VDELTA Difference of Ground Supplies GND, AGND To achieve good performance, the negative supply terminals should be connected to a low impedance ground plane. -0.1 0.1 V Other Pins V MICS Microphone Supply Voltage MICS 0 3.7 V VANALOG Analog Pins MICACL, MICACR,LINR, LINL, HPR, HPL, QMICL, QMICR, IOP1x, and QOP1x V NEG VBAT V VCONTROL Control Pins MODE/CSCL, ANC/CSDA 0 3.7 V VCP Charge Pump pins CPN and CPP VNEG VBAT V or -1.8 VBAT +0.5 or 1.8 V VMIC Microphone Inputs MICL and MICR VNEG VBAT V
Electrical Characteristics
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Electrical Characteristics Figure 7: Electrical Characteristics (continued) Electrical Characteristics: Shows the electrical characteristics like typical supply voltages as well as system current consumption. Symbol Parameter Condition Min Typ Max Unit Block Power Requirements IOFF Off mode current MODE/CSCL pin low, device switched off 0.4 1 10 μA ISYS Reference supply current VBAT = 1.8V; Bias generation, oscillator, POR; VNEG disabled 0.16 0.25 0.3 mA IMIC Mic gain stage current VBAT = 1.8V; no signal, stereo, normal mode 0.82 1.4 2 mA VBAT = 1.8V; no signal, stereo, ECO mode 0.58 1.1 1.4 mA IHP Headphone stage current VBAT = 1.8V; no signal, normal mode 1.5 2.4 3.1 mA VBAT = 1.8V; no signal, ECO mode 1.18 2.0 2.9 mA IMICS MICS charge pump current VBAT = 1.8V; no load 0.36 0.5 0.9 mA VBAT = 1.6V; no load 0.36 0.4 0.85 mA IOP1 OP1 supply current VBAT = 1.8V; OP1L and OP1R enabled, normal mode 0.85 1.25 1.75 mA VBAT = 1.8V; OP1L and OP1R enabled, ECO mode 0.65 0.9 1.37 mA VBAT = 1.6V; OP1L and OP1R enabled, normal mode 0.8 1.2 1.68 mA VBAT = 1.6V; OP1L and OP1R enabled, ECO mode 0 . 60 . 8 51 . 3 2m A Typical System Power Consumption PFF Typical power consumption feed forward application OP1L, OP1R enabled, Microphone supply enabled, no load, V BAT=1.6V 10 mW PFF_ECO Typical power consumption feed forward application in ECO mode All blocks in ECO mode OP1L, OP1R enabled Microphone supply enabled, no load, V BAT=1.6V 8m W
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Detailed Description This section provides a detail ed description of the device related components. Audio Line Input The chip features one stereo line input for music playback. In monitor mode the line inputs can also be muted in order to stop music playback and increase speech intelligibility. Figure 8: Stereo Line Input Stereo Line Input: This diagram shows the internal structure of the line input. If there is a high pass function desi red in an application, to block very low frequencies that could harm the speaker, or eliminate little offset voltages a simple capacitor C LIN could do this function. The implementation is shown in Figure 8 . The correct capacitor value for the desired cut-off frequency can be calculated with the following formula: A typical cut-off frequency in an audio application is 20Hz. With an input impedance R LIN of typ. 2k and a desired cut off frequency of 20Hz the input capacitor should be bigger than 4μF . Therefore a typical value of 4.7μF is recommended. Detailed Description to le ft he adp hon e amplifierMUTE to right he adp hon e amplifierMUTE Musi c Left LINL Music Right LINR RLI N RLI N CLI N CLI N (EQ1) CLIN
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Detailed Description The cut-off frequency for this filter can be calculated with the following formula: The simulated frequency resp onse for the microphone preamplifier with the recommended component values is shown in Figure 13 . Figure 13: Simulated Microphone Frequency Response In application with PCB space limi tations it is also possible to remove the capacitors C AC and connect MICACL and MICACR pins directly to A GND. In this configuration AC coupling of the QMICR and QMICL signals is recommended. Microphone Frequency Response: This graph shows the frequency response of the microphone preamplifier with different gain settings with C AC=10μF, CMIC=2.2μF and RMICIN=22kΩ. (EQ3) fcut off– 10 100 1k 10k Frequency Response [dB] f [Hz] 0dB 6dB 12dB 18dB 24dB 30dB
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Detailed Description Parameter VBAT=1.8V, T A= 25ºC, C AC=10μF , CMIC=4.7μF and R MICIN =2.2kΩ unless otherwise specified. Figure 14: Microphone Parameter Symbol Parameter Condition Min Typ Max Unit VMICIN0 Input Signal Level AMIC = 10dB 80 mVRMS VMICIN1A MIC = 20dB 40 mVRMS VMICIN2A MIC = 30dB 10 mVRMS SNR Signal to Noise Ratio 0dB gain, High quality mode, AGC off 118.5 dB 10dB gain, High quality mode, AGC off 109 dB 20dB gain, High quality mode, AGC off 99.5 dB 0dB gain, ECO mode, AGC off 117 dB 10dB gain, ECO mode, AGC off 107 dB 20dB gain, ECO mode, AGC off 98 dB V NOISE-A A-Weighted Output Noise Floor 0dB gain, 20Hz – 20kHz bandwidth, high quality 1.2 μV 10dB gain, 20Hz – 20kHz bandwidth, High quality 4.2 μV 20dB gain, 20Hz – 20kHz bandwidth, High quality 13.5 μV 0dB gain, 20Hz – 20kHz bandwidth, ECO mode 1.4 μV 10dB gain, 20Hz – 20kHz bandwidth, ECO mode 4.6 μV 20dB gain, 20Hz – 20kHz bandwidth, ECO mode 14.8 μV IMIC Block Current Consumption VBAT = 1.8V; no signal, stereo, normal mode 0.82 1.4 2 mA VBAT = 1.8V; no signal, stereo, ECO mode 0.58 1.2 1.4 mA
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Detailed Description Microphone Parameter: This table shows the detailed electrical characteristics of the microphone preamplifier gain stage. Figure 15: Microphone Frequency Response AMIC Programmable Gain Discrete logarithmic gain steps 0+ 3 1 d B Gain Steps Size 0.5 dB Gain Step Precision 0.2 dB ΔAMIC Gain Ramp Rate VPEAK related to VBAT or VNEG 1 ms/step VAT TACK Limiter Activation Level VPEAK related to VBAT or VNEG 64 @ 0.5dB 0.40 1 VDECAY Limiter Release Level 0.31 1 AMICLIMIT Limiter Minimum Gain 0 dB tAT TACK Limiter Attack Time 5 μs/step tDECAY Limiter Decay Time 1 ms/step Microphone Frequency Response: This graph shows the frequency response of the microphone preamplifier with different gain settings without R MICIN resistor, CAC capacitor (MICACx pin connected to AGND) and CMIC=10uF. Symbol Parameter Condition Min Typ Max Unit 10 100 1k 10k Frequency Response [dB] f [Hz] 0dB 30dB 10dB 20dB
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Detailed Description Microphone Supply The AS3412 features an integrated microphone supply charge pump. This charge pump provides the proper microphone supply voltage even with a 1.8V chip supply voltage in order to increase the sensitivit y of the microphone. Figure 18: Microphone Supply Therefore the integrated charge pump generates a microphone supply voltage which is typically 2.7V. The microphone supply voltage is also used to switch off the integrated music bypass switch of the AS3412 is in active mode. Therefore, during normal operation the microphone supply must not be switched off if the TRSDA/BPL and TRSCL/BPR pins are in use. MIC Charge Pump VBAT MICS_ON CP Byp ass MICSMicrophone BIAS resi stors CMI CSCMI CSF RMI CSF
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Detailed Description Headphone Amplifier The headphone amplifier is a true ground output using V NEG as negative supply. It is designed to feature an output power of 2x34mW @ 32 Ω load . For higher output requirements, the headphone amplifier is also ca pable of operating in bridged mode. In this mode the left output is carrying the inverted signal of the right output shown in Figure 22 . With a V BAT voltage of 1.8V, a maximum output power of 90mW can be achieved. This is required for over- and on ear headsets with higher output power requirements. The amplifier itself features various input sources. The line in put signal is directly connected to the headphone amplifier. Th e input multiplexer supports three different input signals whic h can be configured according to the HPH_MUX register. The “Open” setting is being used to disable the active noise cancelling function. Figure 21: Headphone Amplifier Single Ended Headphone Amplifier Single Ended: This figure shows the block diagram of the headphone amplifier including the integrated music bypass switches as well as the summation input of the amplifier in single ended configuration. MUX QMICR QOP1R open MUX QMICL QOP1L open HPR HPL LINL AGND LINR RLI N RLI N 2kΩ 2k Ω 2kΩ 2kΩ 2kΩ 2kΩ HPH_MUX HPH_MUX LI NE_MUTE LI NE_MUTE
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Detailed Description Figure 22: Headphone Amplifier Differential Headphone Amplifier Differential: This figure shows the block diagram of the headphone amplifier including the integrated music bypass switches as well as the summation input of the amplifier in differential output mode. MUX QMICL QOP1L open HPL HPR AGND LINL RLI N 2kΩ 2k Ω 2kΩ 2kΩ 2kΩ HPH_MUX LI NE_MUTE
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Detailed Description Parameter VBAT =1.8V, T A= 25ºC, unless otherwise specified. Figure 23: Headphone Amplifier Parameter Symbol Parameter Condition Min Typ Max Unit RL_HP Load Impedance Stereo mode 16 32 Ω Mono 32 Ω CL_HP Load Capacitance Stereo mode 100 pF PHP Nominal Output Power Stereo Mode Vbat = 1.8V; 32Ω load; THD<0.1% 34 mW Vbat = 1.65V; 32Ω load; THD<0.1% 29 mW Vbat = 1.8V; 16Ω load; THD<0.1% 50 mW Vbat = 1.65V; 16Ω load; THD<0.1% 41 mW PHP_BRIDGE Nominal Output Power Differential Mode V bat = 1.8V; 32Ω load 90 mW Vbat = 1.65V; 32Ω load 75 mW IHPH Supply current VBAT = 1.8V; no signal, normal mode 1.5 2.4 3.1 mA VBAT = 1.8V; no signal, ECO mode 1.18 2 2.9 mA PSRRHP Power Supply Rejection Ratio 1kHz 100 dB SNR Signal to Noise Ration High Quality Mode, Line Input -> HPH stereo in phase test signal; 32Ω load; V BAT = 1.8V; 111.5 dB High Quality Mode, Line Input -> HPH stereo out of phase test signal; 32Ω load; V BAT = 1.8V; 112.5 dB ECO Mode, Line Input -> HPH stereo in phase test signal; 32Ω load; V BAT = 1.8V; 109.5 dB ECO Mode, Line Input -> HPH stereo out of phase test signal; 32Ω load; V BAT = 1.8V; 110.5 dB Channel Separation 32Ω load 93 dB
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Detailed Description Figure 28: Headphone THD+N vs. Frequency 16Ω Stereo Headphone THD+N vs. Frequency: These figures shows the A-weighted THD+N measurements over frequency in stereo mode with V BAT=1.8V. The amplifier gain is 0dB and the load is 16Ω. 0,0001 0,001 0,01 0,1 10 100 1k 10k Pout [mW] THD+N [%] f [Hz] THD+N THD+N ECO Pout
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Detailed Description Figure 32: Bypass THD+N vs. Output Power 16Ω Load Figure 33: Bypass THD+N vs. Output Power 32Ω Load Bypass THD+N vs. Output Power: This graph shows A-weighted THD+N characteristics of the integrated bypass switch for 16Ω load. Bypass THD+N vs. Output Power: This graph shows A-weighted THD+N characteristics of the integrated bypass switch for 32Ω load. 0,001 0,01 0,1 11 0 1 0 0 THD+N [%] Pout [mW]
16 Ohm
0,001 0,01 0,1 11 0 1 0 0 THD+N [%] Pout [mW]
32 Ohm
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Detailed Description Operational Amplifier The AS3412 offers one general purpose operational amplifier for feed-forward ANC applications. The amplifier is used to develop the gain- and phase compensation filter for the ANC signal path. Figure 34: Operational Amplifiers Operational Amplifier: This figure shows the block diagram of the operational amplifiers to be used for ANC filter design. AGND OP1L OP1R QOP1R QOP1L
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Detailed Description Parameter VBAT =1.8V, T A= 25ºC, R input = R FB = 1kΩ unless otherwise specified. Figure 35: Operational Amplifier Parameter Operational Amplifier: This table shows the detailed electrical characteristics of the operational amplifiers to be used for ANC signal processing. Note(s): 1. SNR figure measured with 20dB gain to minimize audio analyzer noise floor Symbol Parameter Condition Min Typ Max Unit VLIN Input Signal Level Gain=0dB 0.9*VBAT VBAT VPEAK SNR Signal to Noise Ratio 10kΩ load, Gain = 0dB(1), VBAT=1.8V, High Quality Mode 122.5 dB 10kΩ load, Gain = 0dB, VBAT=1.65V High Quality Mode 121.5 dB 10kΩ load, Gain = 0dB, VBAT=1.8V, ECO Mode 121 dB 10kΩ load, Gain = 0dB, VBAT=1.65V, ECO Mode 119.5 dB IOP1 Block Current Consumption VBAT = 1.8V; OP1L and OP1R enabled, normal mode 0.85 1.25 1.75 mA VBAT = 1.8V; OP1L and OP1R enabled, ECO mode 0.65 0.9 1.37 mA VBAT = 1.65V; OP1L and OP1R enabled, normal mode 0.8 1.2 1.68 mA VBAT = 1.65V; OP1L and OP1R enabled, ECO mode 0.6 0.85 1.32 mA VNOISE-A Input Referred Noise Floor A-Weighted High Quality Mode 900 nV ECO Mode 1.1 μV Voffset DC offset voltage Gain = 0dB 2 mV CL Load Capacitance 100 pF ALoop Open Loop Gain 100Hz 120 dB RL Load Impedance 1 kΩ
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Detailed Description System The system block handles the power up and power down sequencing as well as the mode switching. Power Up/Down Conditions The chip powers up when one of the following conditions is true: Figure 38: Power Up Conditions Power Up Conditions: This table shows the available power up conditions of the AS3412. The chip automatically shuts off if one of the following conditions arises: Figure 39: Power Down Conditions Power Down Conditions: This table shows the available power down conditions of the AS3412. # Source Description 1M O D E p i n In stand-alone mode, MODE pin has to be driven high for >2ms to turn on the device
2 I²C start In I²C mode, an I²C start condition turns on the device
# Source Description 1M O D E p i n Slider Mode: Mode pin has to be driven low for 10ms to turn off Push Button Mode: Mode pin has to be driven high for >2.4sec to turn off 2S e r i a l I n t e r f a c e Power down by serial interface by clearing the PWR_HOLD bit. (Please mind that the I²C_MODE bit has to be set before clearing the PWR_HOLD bit for security reasons) 3 V NEG CP OVC Power down if V NEG is higher than the VNEG off-threshold
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Detailed Description Start-Up Sequence The AS3412 has a defined startup sequence. Once the AS3412 MODE pin is pulled high, the device initiates the automatic startup sequence shown in Figure 40 . Figure 40: Start-Up Sequence Start-Up Sequence: This timing diagram shows the startup sequence of the AS3412 in detail. MODE/CSCL VOL/CSDA VBAT BIAS & OSC ON VNEG ON VNEG OK OTP READ PWR_HOLD MICS & OP1 ON MIC STAGE ON HPH & LINE ON PWRUP COMPLETE FADE IN MIC GAIN 01 234 2 0 3 405 981 Time Axis t [ms] min. 1.65V min. 70% VBAT don‘t care
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Detailed Description Playback Only Mode The active noise cancelling feature of the AS3412 can also be disabled with the ANC/CSDA pin. The ANC/CSDA pin has to be pulled high to enable the ANC function during startup (ANC MODE). If the pin is connected to ground, the chip enters playback only mode (PBO MODE ) in which the ANC function is disabled. The operating mode of the line input mute switch, as well as the mixer input, can be defined in register PBO_MODE . The microphone amplifier shuts do wn automatically, but it is possible to control the operational amplifiers in this mode separately. Typically only the line input amplifiers and the headphone amplifier are enabled in the playback only mode. If this function is not desired you just need to pull the pin high through a 22kΩ resistor. Figure 49: Playback Only Mode Timing Diagram Playback Only Mode Timing Diagram: The diagram shows the necessary voltages and timings for different operation modes in Playback Only Mode. ANC/CSDA Pin ANC ON Playback Only Mode ANC ON 200-400ms 200-400ms >65% VBAT <35% VBAT Operation Mode
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Detailed Description Independent of the OTP programming, it is possible to overwrite the OTP register temporarily if the chip is controlled via I²C. The chip configuration ca n be stored for example in the flash memory of a Bluetooth- or wireless chipset and can be loaded to the ANC chip during st artup of the device via the I²C interface. Because the OTP fuses upload their contents into the OTP register at power-up, the new OTP settings from the microcontroller will overwrite the default settings of the AS3412. All I²C OTP registers se ttings can be changed as many times as desired, but will be lost during power off. OPT Registers and Fuses: The OTP registers are volatile memory cells which lose the content once the device is switched off. Multiple read and write commands are possible but in order to store chip settings during power off mode, the OTP fuses have to be used. The OTP memory can be accessed in the following ways:
- LOAD Operation The LOAD operation reads the OTP fuses and loads the contents into the OTP register. A LOAD operation is automatically executed after each power-on-reset.
- WRITE Operation The WRITE operation allows a temporary modification of the OTP register. It does not program the OTP. This operation can be invoked multiple times and will remain set while the chip is supplied with power and while the OTP register is not modified with another WRITE or LOAD operation.
- READ Operation The READ operation reads the contents of the OTP register, for example to verify a WRITE command or to read the OTP memory after a LOAD command.
- STORE Operation The STORE operation programs the contents of the OTP register permanen tly into the OTP fuses. Don’t use old or nearly empty batteries for programming the fuses.
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Detailed Description Figure 57: Timing Diagram V NEG Buffering VNEG Buffer Timing: This timing diagram shows how to buffer the VNEG supply during the OTP programming process. To guarantee a successful trimming process it is important to follow the predefined trimming sequence shown in Figure 57 . As a first step it is important to do a register dump of all OTP registers. This register backup in your system memory is a backup of all register settings and is necessary for verification after the trim process to make sure that all bits are trimmed correctly. Once the register dump has been done it is important to check registers 0x30 and 0x31. These registers typically indicate if the device is already tr immed or not. If both registers have the value 0x80 you can enter the trim mode and start the trimming process. Once trimming is done, the most important step is comparing the values trimmed to the device with the original register dump performe d just before we started the actual trimming process. If the verification was successful we know that all bits have been trimmed correctly. What is important to mention is that the AS3412 has a couple of test bits inside which are by default set to ‘1’ . We do not recommend overwriting these bits. Furthermore, it is important to know that it is not possible to change bits once they are trimmed. It is not possible to change a bit from ‘1’ back to zero. If an additional trimming is done it is only possible to change bits from ‘0’ to ‘1’ . It is important that all nece ssary bits are trimmed exactly like in the block diagram shown in Figure 58 . VBAT MODE/CSCL VOL/CSDA VNEG OK VNEG BUFFER ON >10ms ~1ms ~1ms Start Trim-Process
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Detailed Description Figure 58: OTP Programming Process OTP Programming: This flow chart describes the OTP programming process in detail. Besides production trimming using the I²C interface, the AS3412 features a second uniq ue trimming mechanism. This very special mode enables the analog music inputs of the AS3412 to become a production trimming input. Re giste r dump of OTP registers 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x14 an d 0x15 ANC_L and AN C_R reg isters pro grammed Is ALT2_ENAB LE bit set in 0x11? Is ALT3_ENAB LE bit set in 0x13? Start a pplica tio n trim t o reg ister 0x30-0x35 an d 0x14 an d 0x15 Start trim verification w ith OTP load tests Start a lte rnative microp hon e trim to regist er 0x10 an d 0x11 with ALT2_ENAB LE bi t s et Start trim verification w ith OTP load tests Start a lte rnative microp hon e trim to regist er 0x12 an d 0x13 with ALT3_ENAB LE bi t s et Start trim verification w ith OTP load tests Veri fi cation OK? Veri fi cation OK? Veri fi cation OK? Device trimmin g failed Device trimmin g failed Device trimmin g failed De vice trimming successf ul De vice is alre ady trimmed. No more trimming p ossible. Exit trimming mode
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Detailed Description Figure 59: Production Trim Box Production Trim Box: This block diagram shows the connection of the Trim Box enabling the audio inputs to become a trim input for mass production. With this new system, there is no need for mechanical potentiometers any more. Up to now, operators in production use screw drivers to fine tune the ANC performance of each headset. The disadvantage of this is reliability and cost of potentiometers. Additionally, operators are not always precise in their work, thus yielding inconsistent results. With the new production trimming system from ams there are no mechanical potentiometers required. The operator connects a 3.5mm audio jack to a trimming box and this box enables the audio input of the headset to become the ANC tu ning input. This new feature also helps industrial designers of headset because there are no more considerations concerning leakage holes for the old mechanical trimming. Thus, the headset can be fully assembled and ready for the ANC test system at the end of the manufacturing process. The trim box can be easily controlled with an RS232 interface so it is also possible to create fully automated trimming systems. For further details please contact our local sales office; they can provide you with source code examples and application notes. LINR TRSCL/BPR MUTE MUTE TRSDA/BPL 3 x PROM to HPH to HPH LINL
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Detailed Description
2 Wire Serial Interface
In order to configure the device using the evaluation software or a MCU the AS3412 features a serial two wire interface. The I²C address for the device can be found in Figure 60 . Figure 60: I²C Slave Address I²C Slave Address Table: Shows the I²C address of the AS3412. Protocol Figure 61: I²C Serial Interface Symbol Definition Symbol Definition: The table shows the symbol definitions being used in the explanations for the data transfer between master and slave.
7 Bit I²C Address 8 Bit Read Address 8 Bit Write Address
S Start condition after stop R 1 bit Sr Repeated start R 1 bit DW Device address for write R 1000 1110b (8Eh) DR Device address for read R 1000 1111b (8Fh) WA Word address R 8 bit AA c k n o w l e d g e W 1 b i t NN o A c k n o w l e d g e R 1 b i t reg_data Register data/write R 8 bit data (n) Register data/read W 8 bit P Stop condition R 1 bit WA++ Increment word address internally R during acknowledge AS3412 (=slave) transmits data AS3412 (=slave) receives data
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Detailed Description To keep the access time as short as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes have to be responded with an acknowledge from the master. For termination of the transmission, the master sends a not-acknowledge following the last data byte and a subsequent STOP condition. Parameter Figure 67: I²C Serial Timing I²C Serial Timing: This figure shows the I²C timing diagram. 81-7 ANC/CSDA MODE/CSCL 8 9 81-7 8 9 81-7 8 9 Start Co ndition Addre ss R/W ACK Da ta ACK Da ta ACK Stop Co ndition TS T SU TH TLT HD T PD
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Detailed Description VBAT =1.8V, T A=25ºC, unless otherwise specified. Figure 68: I²C Serial Interface Parameter I²C Serial Interface Parameter: This table shows the serial interface timing parameter. Symbol Parameter Condition Min Typ Max Unit VCSL CSCL, CSDA Low Input Level (max 30% VBAT) 0 - 0.42 V VCSH CSCL, CSDA High Input Level CSCL, CSDA (min 70% VBAT) 1.16 - V HYST CSCL, CSDA Input Hysteresis 200 450 800 mV VOL CSDA Low Output Level at 3mA - - 0.4 V Tsp Spike insensitivity 50 100 - ns TH Clock high time max. 400kHz clock speed 500 ns TL Clock low time max. 400kHz clock speed 500 ns TSU CSDA has to change TSU before rising edge of CSCL 250 - - ns THD No hold time needed for CSDA relative to rising edge of CSCL 0- -n s TS CSDA H hold time relative to CSDA edge for start/stop/rep_ start 200 - - ns T PD CSDA prop delay relative to low going edge of CSCL 50 ns
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Register Description Register Overview Figure 69: Register Overview Addr Name b7 b6 b5 b4 b3 b2 b1 b0 System Registers 20h SYSTEM DESIGN_VERSION<3:0> 1111 EVAL_REG_ON - - PWR_HOLD 21h PWR_READ - LOW_BAT PWRUP COMPLETE HPH_ON MIC_ON - MICS_CP_ON MICS_ON 2h-2Fh Reserved OTP Registers 10h ANC_R2 TEST_BIT_1 - MICR_VOL_OTP2<5:0> Gain from MICR to QMICR or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB 11h ANC_L2 ALT2_ENABLE - MICL_VOL_OTP2<5:0> Gain from MICL to QMICL or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB 12h ANC_R3 TEST_BIT_2 - MICR_VOL_OTP3<5:0> Gain from MICR to QMICR or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB 13h ANC_L3 ALT3_ENABLE - MICL_VOL_OTP3<5:0> Gain from MICL to QMICL or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB 14h ANC_MODE HPH_MUX<1:0> 0: MIC; 1: OP1; 2: Do not use; 3: Not connected - LIN_MUTE - - OP1R_ON OP1L_ON Register Description
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Register Description 15h MON_MODE MON_HPH_MUX<1:0> 0: MIC; 1: OP1; 2: Do not use; 3: - - MON_LIN_ MUTE - - SLIDER_MON DISABLE_ MONITOR 16h PBO_MODE TEST_BIT_4 NO_PBO - PBO_LIN_MUTE - - PBO_OP1R_ ON PBO_OP1L_ ON 17h ECO SLIDE_PWR_ UP -- - ENABLE_HPH_ ECO ENABLE_MIC_ ECO - ENABLE_ OPAMP_ECO 30h ANC_R TEST_BIT_3.1 - MICR_VOL<5:0> Gain from MICR to QMICR or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB 31h ANC_L TEST_BIT_6 - MICL_VOL<5:0> Gain from MICL to QMICL or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB 32h MIC_MON_R - - MICR_MON<5:0> Gain from MICR to QMICL/R = 0dB...+31dB; MUTE and 63 steps of 0.5dB if MON_MODE is active 33h MIC_MON_L - - MICL_MON<5:0> Gain from MICL to QMICL/R = 0dB...+31dB; MUTE and 63 steps of 0.5dB if MON_MODE is active 34h MODE_1 MICS_CP_OFF MICS_OFF MI C_AGC_ON MIC_OFF - CP_OFF HPH_OFF - 35h MODE_2 TEST_BIT_7 - - - MICS_DC_OFF DELAY_HPH_ MUX HPH_MODE 0: Stereo 1: Mono Differential I2C_MODE Addr Name b7 b6 b5 b4 b3 b2 b1 b0
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Register Description Register Overview: This table provides a handy overview of all AS3412 registers. Evaluation Registers 3Dh EVAL EVAL_ON - - MASTER_ LIN_MUTE MON_MODE PBO_MODE MICR_MUTE MICL_MUTE 3Eh CONFIG_1 EXTBURNCLK 3Fh CONFIG_2 TM34 BURNSW TM_REG34-35 TM_REG30-33 OTP_MODE<1:0> 0: READ; 1: LOAD; 2: WRITE; 3: BURN Addr Name b7 b6 b5 b4 b3 b2 b1 b0
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Register Description Detailed Register Description System Registers Figure 70: SYSTEM Register Description Name Address Default Value SYSTEM 0x20 81h This register contains control bits for monitor mode, OTP register and power up/down functions. Bit Bit Name Default Access Bit Description 7:4 DESIGN_VERSION 1111 R Design version number to identify the design version of the AS3412. 1111: for chip version 1v0 3E V A L _ R E G _ O N 0 R / W This register controls read and write access to the OTP register banks. 0: Normal operation 1: Enables writing to register 0x3D, 0x3E and 0x3F to configure the OTP and set the access mode. 0P W R _ H O L D 1 R / W This bit allows an MCU using the I²C interface a power down of the AS3412. A start condition on the I²C interface will wake up the device again. This function works only if the I2C_MODE bit is set before you write this register. 0: Power up hold is cleared and chip powers down 1: It is automatically set to on after power on
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Register Description Figure 71: PWR_SET Register Description Name Address Default Value PWR_READ 0x21 0x3F A readout of this register returns the status of each block o f the chip. Bit Bit Name Default Access Bit Description 6L O W _ B A T x R VBAT supervisor status 0: VBAT is above brown out level 1: VBAT has reached brown out level
5 PWRUP_
0: Power-up sequence incomplete 1: Power-up sequence completed
4 HPH_ON 0 R
This register returns the power status of the headphone amplifier. 0: Headphone amplifier switched off 1: Headphone amplifier switched on
3 MIC_ON 0 R
This register returns the power status of the microphone preamplifier. 0: Microphone preamplifier switched off 1: Microphone preamplifier switched on 1M I C S _ C P _ O N 0 R This register returns the power status of the microphone charge pump. 0: Microphone charge pump switched off 1: Microphone charge pump switched on 0M I C S _ O N 0 R This register returns the power status of the microphone supply (MICS). 0: Microphone supply switched off 1: Microphone supply switched on
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Register Description OTP Register Figure 72: ANC_R2 Register Description Name Address Default Value ANC_R2 0x10 80h The ANC_R2 register configures the gain for the right microphone input. This register is the first alternative microphone gain register for OTP programming in case the ANC_R register is already programmed. Bit Bit Name Default Access Bit Description 7 TEST_BIT_1 1 R Test register. Please do not write this register. 5:0 MICR_VOL_ OTP2<6:0> 000 0000 R/W Volume settings for right microphone input, adjustable in 63 steps of 0.5dB 00 0000: MUTE 00 0001: 0 dB gain 00 0010: 0.5dB gain 00 0011: 1.0dB gain 11 1110: 30.5dB gain 11 1111: 31dB gain
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Register Description Figure 73: ANC_L2 Register Description Name Address Default Value ANC_L2 0x11 00h The ANC_L2 Register configures the gain for the left microphone input. This register is the first alternative microphone gain register for OTP programming in case the ANC_L register is already programmed. Bit Bit Name Default Access Bit Description 7A L T 2 _ E N A B L E 0 R / W In case the register is being used for microphone programming this bit has to be set. The bit is being used by the internal state machine of the AS3412 to determine which alternative microphone gain register has to be used during startup. 0: Microphone registers 0x10 and 0x11 are not active 1: Microphone registers 0x10 and 0x11 are active. Gain settings in registers 0x30 and 0x31 are ignored 5:0 MICL_VOL_ OTP2<6:0> 000 0000 R/W Volume settings for left microphone input, adjustable in 63 steps of 0.5dB 00 0000: MUTE 00 0001: 0dB gain 00 0010: 0.5dB gain 00 0011: 1.0dB gain 11 1110: 30.5dB gain 11 1111: 31dB gain
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Register Description Figure 74: ANC_R3 Register Description Name Address Default Value ANC_R3 0x12 80h The ANC_R3 Register configures the gain for the right microphone input. This register is the second alternative microphone gain register for OTP programming in case the ANC_R and ANC_R2 registers are already programmed. Bit Bit Name Default Access Bit Description 7 TEST_BIT_6 1 R Test register. Please do not write this register. 5:0 MICR_VOL_ OTP3<6:0> 000 0000 R/W Volume settings for right microphone input, adjustable in 63 steps of 0.5dB 00 0000: MUTE 00 0001: 0dB gain 00 0010: 0.5dB gain 00 0011: 1.0dB gain 11 1110: 30.5dB gain 11 1111: 31dB gain
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Register Description Figure 75: ANC_L3 Register Description Name Address Default Value ANC_L3 0x13 00h The ANC_L3 Register configures the gain for the left microphone input. This register is the second alternative microphone gain register for OTP programming in case the ANC_L and ANC_L2 registers are already programmed. Bit Bit Name Default Access Bit Description 7A L T 3 _ E N A B L E 0 R / W In case the register is being used for microphone programming this bit has to be set. The bit is being used by the internal state machine of the AS3412 to determine which alternative microphone gain register has to be used during startup. 0: Microphone registers 0x12 and 0x13 are not active 1: Microphone registers 0x12 and 0x13 are active. Gain settings in registers 0x30, 0x31, 0x10 and 0x11 are ignored. 5:0 MICL_VOL_ OTP3<6:0> 000 0000 R/W Volume settings for left microphone input, adjustable in 63 steps of 0.5dB 00 0000: MUTE 00 0001: 0dB gain 00 0010: 0.5dB gain 00 0011: 1.0dB gain 11 1110: 31dB gain 11 1111: 31dB gain
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Register Description Figure 76: ANC_MODE Register Description Name Address Default Value ANC_MODE 0x14 00h The ANC_MODE register controls various settings for the chipset in active noise cancelling mode like which amplifiers are enabled as well as which audio inputs are active. Bit Bit Name Default Access Bit Description 7:6 HPH_MUX<1:0> 00 R/W This register selects the ANC input source for the headphone amplifier in ANC mode. Depending on the register setting the outputs of microphone preamplifier or OPAMP1 can be connected to the headphone amplifier input. It is also possible to disconnect all ANC input sources which is sometimes desired in monitor mode. 00: QMIC outputs are connected to HPH input 01: OP1 outputs are connected to HPH input 10: Do not use this setting 11: Nothing connected to HPH input except line input in case it is enabled.
4 LIN_MUTE 0 R/W
This bit mutes the line input signal. If the bit is set the line input signal is disconnected from the headphone amplifier. 0: Line input signal enabled 1: Line input signal muted 1O P 1 R _ O N 0 R / W This register enables the right channel of OPAMP 1 in ANC mode. 0: Right OP1 is switched off 1: Right OP1 is switched on 0O P 1 L _ O N 0 R / W This register enables the left channel of OPAMP 1 in ANC mode. 0: Left OP1 is switched off 1: Left OP1 is switched on
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Register Description Figure 77: MONITOR_MODE Register Description Name Address Default Value MONITOR_MODE 0x15 00h The MONITOR_MODE register controls various settings for the chipset in monitor mode like line input monitor mode attenuation as well as which audio inputs are active. Bit Bit Name Default Access Bit Description 7:6 MON_HPH_ MUX<1:0> 00 R/W This register selects the ANC input source for the headphone amplifier in monitor mode. Depending on the register setting the outputs of microphone preamplifier, OPAMP1, OPAMP2 can be connected to the headphone amplifier input. 00: QMIC outputs are connected to HPH input 01: OP1 outputs are connected to HPH input 10: Do not use this setting 11: Nothing connected to HPH input except line input.
4 MON_LIN_MUTE 0 R/W
This bit mutes the audio line input pin in Monitor mode. 0: Line input enabled in Monitor mode 1: Line input muted in Monitor mode 1S L I D E R _ M O N 0 R / W This bit enables the Full Slider Mode configuration. Please mind that this bit must not be set without setting SLIDE_PWR_UP to ‘1’ . 0: Slider Mode activated 1: Full Slider Mode activated
0 DISABLE_
This bit disables the monitor mode in push button control mode. 0: Monitor mode enabled 1: Monitor mode disabled
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Register Description Figure 78: PBO_MODE Register Description Name Address Default Value PBO_MODE 0x16 0x00 The PBO_MODE register controls various settings for the chipset in playback only mode like which amplifiers are enabled as well as which audio inputs are active. Bit Bit Name Default Access Bit Description 7 TEST_BIT_4 1 R Test register. Please do not write this register.
6 NO_PBO 0 R/W
This bit disables the playback only mode function. No external pull up resistor is required on ANC / CSDA pin is necessary if this bit is set to ‘1’ 0: Playback only mode enabled 1: Playback only mode disabled
4 PBO_LIN_MUTE 0 R/W
This bit enables the eco mode of the microphone preamplifier. 0: Power save function disabled 1: Power save function enabled 1P B O _ O P 1 R _ O N 0 R / W This register enables the right channel of OPAMP 1 in playback only mode. 0: Right OP2 is switched off 1: Right OP2 is switched on 0P B O _ O P 1 L _ O N 0 R / W This register enables the left channel of OPAMP 1 in playback only mode. 0: Left OP2 is switched off 1: Left OP2 is switched on
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Register Description Figure 79: ECO Register Description Figure 80: ANC_R Register Description Name Address Default Value ECO 0x17 0x00 This register controls the economic (ECO) mode for all analog audio blocks. Furthermore it includes also other general settings. Bit Bit Name Default Access Bit Description
7 SLIDE_PWR_UP 0 R/W
This bit enables the slide switch control mode of the AS3512. If this bit is programmed the device can be powered up and powered down via a slide switch. 0: Slide switch control disabled 1: Slide switch control enabled
3 ENABLE_HPH_
This bit enables the eco mode of the headphone amplifier. 0: Power save function disabled 1: Power save function enabled
2 ENABLE_MIC_
This bit enables the eco mode of the microphone amplifier. 0: Power save function disabled 1: Power save function enabled
0 ENABLE_OPAMP_
This bit enables the eco mode of the operational amplifier amplifiers for ANC filter design. 0: Power save function disabled 1: Power save function enabled Name Address Default Value ANC_R 0x30 80h The ANC_R Register configures the gain for the right microphone input. Bit Bit Name Default Access Bit Description 7 TEST_BIT_5 1 R/W Please do not write this register. 5:0 MICR_VOL<5:0> 000 0000 R/W Volume settings for right microphone input, adjustable in 63 steps of 0.5dB 00 0000: MUTE 00 0001: 0dB gain 00 0010: 0.5dB gain 00 0011: 1dB gain 11 1110: 30dB gain 11 1111: 31dB gain
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Register Description Figure 83: MIC_MON_L Register Description Name Address Default Value MIC_MON_L 0x33 0x00 This register controls the microphone gain in monitor mode for the left microphone channel. Bit Bit Name Default Access Bit Description 5:0 MICL_MON<5:0> 00 0000 R/W Monitor mode gain setting for left microphone input adjustable in 63 steps of 0.5dB 00 0000: MUTE 00 0001: 0.5dB gain 00 0010: 1dB gain 00 0011: 1.5dB gain 11 1110: 30.5dB gain 11 1111: 31dB gain
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Register Description Figure 84: MODE_1 Register Description Name Address Default Value MODE_1 0x34 0x00 This register controls miscellaneous settings of the AS3512. Bit Bit Name Default Access Bit Description 7M I C S _ C P _ O F F 0 R / W This bit controls the microphone supply charge pump. The microphone charge pump has a second function besides the bias voltage generation for microphones. It is also used to disable the integrated music bypass switch if the AS3412 is active. In case the integrated bypass switch is used in an application the MICS_CP_ OFF bit must not be set to ‘1’ . 0: Microphone supply charge pump enabled 1: Microphone supply charge pump disabled 6M I C S _ O F F 0R / W This bit controls the microphone supply. In case this bit is set to ‘1’ the MICS pin is disconnected from the internal microphone supply. 0: Microphone supply switched on 1: Microphone supply switched off
5 MIC_AGC_ON 0 R/W
This bit disables the automatic gain control of the microphone preamplifier. 0: AGC disabled 1: AGC enabled 4M I C _ O F F 0 R / W This bit powers down the microphone preamplifier. 0: Microphone preamplifier enabled 1: Microphone preamplifier disabled
2 CP_OFF 0 R/W
NEG charge pump in case there is already a negative supply present in a system. 0: VNEG charge pump enabled 1: VNEG charge pump enabled 1H P H _ O F F 0 R / W This bit allows the user to power down headphone amplifier in case it is not used in the final application in order to save system power. 0: Headphone amplifier enabled 1: Headphone amplifier disabled
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Register Description Figure 85: MODE_2 Register Description Name Address Default Value MODE_2 0x35 0x00 This register controls miscellaneous settings of the AS3512. Bit Bit Name Default Access Bit Description 7 TEST_BIT_7 1 R/W Test register. Please do not write this register.
3 MICS_DC_OFF 0 R/W
This bit disables the internal microphone supply discharge function if the microphone supply is switched off. 0: MICS discharge enabled 1: MICS discharge disabled
2 DELAY_HPH_
With this bit it is possible to delay the HPH_MUX setting during startup of the device to avoid unwanted pop noise in case of long charging times of external components. 0: HPH_MUX_OTP delay disabled 1: HPH_MUX_OTP delay enabled 1H P H _ M O D E 0 R / W This register controls the operating mode of the headphone amplifier. The headphone amplifier supports single ended mode and differential mode. In differential output mode the right audio signal path is the active input signal for the headphone amplifier. 0: Stereo single ended mode 1: Mono differential mode 0I 2 C _ M O D E 0R / W This bit enables I²C power down of the AS3412. 0: I²C power down disabled 1: I²C power down enabled via PWR_HOLD bit.
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Register Description Evaluation Register Figure 86: EVAL Register Description Name Address Default Value EVAL 0x3D 0x00 This register enables miscellaneous operating modes, that are typically controlled via slide switch or push button, for evaluation purposes or MCU controlled applications. Bit Bit Name Default Access Bit Description
4 MASTER_LIN_
This register is the master register for the line input mute function. No matter in what operating mode the device is working the LINE_MUTE bit overrules any other setting in any operation mode. 0: Line Input master mute disabled 1: Line Input master mute enabled 3M O N _ M O D E 0 R / W This bit enables the monitor mode of AS3415/35 which can normally be enabled by pulling the MODE pin to VBAT/2. In case an MCU is connected to the device the Monitor mode can be enabled by setting this bit. 0: Monitor mode deactivated 1: Monitor mode activated
2 PBO_MODE 0 R/W
This bit enables the playback mode of AS3412 which can normally be enabled by pulling the ANC pin to 0V. In case an MCU is connected to the device Monitor mode can be enabled by setting this bit. 0: Monitor mode deactivated 1: Monitor mode activated 1M I C R _ M U T E 0 R / W This register is the master mute register for the left microphone amplifier. No matter in what operating mode the device is working the MICL_MUTE bit overrules any other setting in any operation mode. 0: Mute disabled 1: Mute enabled 0M I C L _ M U T E 0 R / W This register is the master mute register for the left microphone amplifier. No matter in what operating mode the device is working the MICR_MUTE bit overrules any other setting in any operation mode. 0: Mute disabled 1: Mute enabled
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Register Description Figure 87: CONFIG_1 Register Description Name Address Default Value CONFIG_1 0x3E 0x00 This bit controls the OTP programming clock source. Bit Bit Name Default Access Bit Description 3E X T B U R N C L 0 R / W This register controls the clock source for OTP programming. Typically the internal clock is being used for OTP programming. 0: External burn clock disabled 1: External burn clock enabled
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Register Description Figure 88: CONFIG_2 Register Description Name Address Default Value CONFIG_2 0x3F 0x00 This register controls the register access to all OTP registers. In order to get access to these registers it is necessary to set EVAL_REG_ON bit to ‘1’ . Bit Bit Name Default Access Bit Description 5T M 3 4 0 R / W This Register defines the register bank selection for register 0x30-0x35 and 0x10-0x17. Depending on TM34 you can select either between Register bank 0x10-0x17 or 0x30h-0x34. 0: Test mode Registers 14h-17h and 10h-13h disabled test mode Registers 30h-33h and 34h-37h enabled 1: Test mode Registers 14h-17h and 10h-13h enabled test mode Registers 30h-33h and 34h-37h disabled 4B U R N S W 0 R / W This register controls the internal buffer switch from line input to V NEG for VNEG buffering during OTP programming. 0: BURN switch disabled 1: BURN switch enabled 3T M _ R E G 3 4 - 3 5 0 R / W 0: Register 34h-35h disabled Register 14h-17h disabled 1: Register 34h-35h enabled Register 14h-17h enabled 2T M _ R E G 3 0 - 3 3 0 R / W 0: Register 30h-33h disabled Register 10h-13h disabled 1: Register 30h-33h enabled Register 10h-13h enabled 1:0 OTP_MODE<1:0> 00 R/W This register controls the OTP access. 00: READ 01: LOAD 10: WRITE 11: BURN
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Application Information Schematic Figure 89: Push Button Operation Mode – Application Example Push Button Operation Mode – Application Example: This application example shows the typical schematic in push button configuration for a Feed-Forward ANC headset. A single push button can control the headset. For details on Push Button control please refer to chapter Operation Modes.
Application Information
4.7µF 1µF GND VBAT VNEG AG ND L R GND Music Input AG ND On / Off / Monitor 10µF GND GND VBAT MIC1 Left ANC MIC 2k2 10µF 22µF GND 220 GND MICS MICS AG ND 1uFC2 10uF AG ND MIC2 Right ANC MIC 2k2 MICS 1uFC11 AG ND 10uF C10 AG ND CPP A1 HPR D1AS3412 TRSCL/BPRE1 WL-CSP MICACLE3 QMICLE2 MICS E4 MICLD4 IOP1LD3 QOP1LD2 LI NLC1 HPL B2 LI NRC2 TRSDA/BPLC3 VB ATB1 VNEG A3 CPNB3 GND A2 AG NDB5 MICRC4 ANC/CSDAC5 QOP1R A4 QMICRA5 IOP1RB4 MODE/CSCLD5 MICACRE5 2k2 AG ND 2k2 AG ND 150 150 AG ND AG ND 4.7µFC8 4.7µFC9 Push Button Left ANC Filter Right ANC Filter AG ND Speaker Left Speaker Right 1.8V – 1.65V
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Application Information Figure 90: Slider Operation Mode – Application Example Slider Operation Mode – Application Example: This application example shows the typical schematic in Slider configuration for a Feed-Forward ANC headset. A 3 pole slider is being used to switch the AS3412 on and off. A push button is used to enter Monitor mode. 4.7µF 1µF GND VBAT VNEG AG ND L R GND Music Input AGND 10µF GND GND VBAT MIC1 L eft ANC M IC 2k2 10µF 22µF GND 220 GND MICS MICS AG ND 1uFC2 10uF AG ND MIC2 Right ANC MIC 2k2 MICS 1uFC11 AG ND 10uF C10 AGND CPP A1 HPR D1AS3412 TRSCL/BPRE1 WL-CSP MICACLE3 QMICLE2 MICS E4 MICLD4 IOP1LD3 QOP1LD2 LI NLC1 HPL B2 LI NRC2 TRSDA/BPLC3 VB ATB1 VNEG A3 CPNB3 GND A2 AGNDB5 MICRC4 ANC/CSDAC5 QOP1R A4 QMICRA5 IOP1RB4 MODE/CSCLD5 MICACRE5 2k2 AG ND 2k2 AG ND 15 0 150 AG ND AG ND 4.7µFC8 4.7µFC9 Left ANC Filter Right ANC Filter AG ND Spea ker Left Sp eaker Right 1.8V – 1.65V GND MO NITOR GND ON OFF 22k 22k
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Application Information Figure 91: Full Slider Operation Mode – Application Example Full Slider Operation Mode – Application Example: This application example shows the typical schematic in Full Slider configuration for a Feed-Forward ANC headset. A multi pole slide switch is being used to switch the AS3412 on, off and enter Monitor mode. 4.7µF 1µF GND VBAT VNEG AG ND L R GND Music Input AGND 10µF GND GND VBAT MIC1 L eft ANC M IC 2k2 10µF 22µF GND 220 GND MICS MICS AG ND 1uFC2 10uF AG ND MIC2 Right ANC MIC 2k2 MICS 1uFC11 AG ND 10uF C10 AGND CPP A1 HPR D1AS3412 TRSCL/BPRE1 WL-CSP MICACLE3 QMICLE2 MICS E4 MICLD4 IOP1LD3 QOP1LD2 LI NLC1 HPL B2 LI NRC2 TRSDA/BPLC3 VB ATB1 VNEG A3 CPNB3 GND A2 AGNDB5 MICRC4 ANC/CSDAC5 QOP1R A4 QMICRA5 IOP1RB4 MODE/CSCLD5 MICACRE5 2k2 AG ND 2k2 AG ND 150 150 AG ND AG ND 4.7µFC8 4.7µFC9 Left ANC Filter Right ANC Filter AG ND Spea ker Left Sp eaker Right 1.8V – 1.65V GND GND 22k 22k R10 OFF ON MON
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Application Information External Components This chapter provides detailed information concerning recommended external components such as capacitors and resistors. Figure 92: External Components External Components: This table provides detailed information concerning the recommended external components to operate AS3412. Symbol Parameter Temp. Characteristic Min. Rated Voltage Max. Tolerance Min. Nom. Capacitance Capacitors C1, CVBAT Input Capacitor Y5R; X5R 4V ±20% 4.7μF C3, CFLY VNEG charge pump flying capacitor Y5R; X5R 4V ±20% 1μF C4, C10, CACR, CACR AC coupling capacitor Y5R; X5R 4V ±10% 10μF C5, CVNEG Output Capacitor Y5R; X5R 4V ±20% 10μF C8, C9 AC coupling input capacitor Y5R; X5R 4V ±20% 4.7μF C6, CMICS Output Capacitor Y5R; X5R 4V ±20% 10μF C7 Output Capacitor (optional component) Y5R; X5R 4V ±20% 22μF C2, C11, CMICL, CMICR AC coupling capacitor; value depends on ANC filter design Y5R; X5R 4V ±10% - C FILTER ANC filter related capacitors Y5R; X5R 4V ±10% - Resistors R1, R6 Bias current resistor for microphones - - 5% 2.2kΩ R4, R5 Pull down resistors to avoid humming noise - - 5% 150Ω R3, R7 Microphone input high pass filter; value depends on ANC filter design -- 5 % - Microphone supply filter resistor (optional component) - - 10% 220Ω R FILTER ANC filter related resistors - - 1% -
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Package Drawings & Markings Figure 93: Package Drawings WL-CSP Note(s): 1. Pin 1 = A1 2. ccc Coplanarity 3. All dimensions are in μm Package Drawings & Markings GreenRoHS 40 040 0 40 040 029 5 29 5 21 90 30 0 40 0 40 0 40 0 40 0 26 0 21 60 cc c 40 22 typ. 378 typ. 200 typ. 600 ± 30 Die si ze after cutting : 2235 x 2205 ± 20μm 31 7 .50 32 2 .50 28 2 .50 31 7 .5 Ball center to ed ge die size after cutti ng (X2): 317.5 μm Ball center to ed ge die size after cutti ng (Y2): 322.50μm
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Ordering & Contact Information Figure 96:
Ordering Information
Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbaderstrasse 30
8141 Premstaetten
Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code Package Marking Delivery Form Delivery Quantity AS3412-EWLT WL-CSP AS3412 Tape & Reel 10000 pcs/reel Ordering & Contact Information
[v1-00] 2016-Apr-06 Document Feedback AS3412 − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specif ied lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are unde rway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to prov ide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Copyrights & Disclaimer Copyright ams AG, Tobelbader St rasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used with out the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appe aring in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding th e information set forth herein. ams AG reserves the right to ch ange specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any th ird party shall arise or flow out of ams AG rendering of technical or other services. Copyrights & Disclaimer
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Revision Information Note(s): 1. Page and figure numbers for the previous version may diff er from page and figure numbers in the current revision. 2. Correction of typographical er rors is not explicitly mentioned. Changes from 0-91 (2016-Mar-22) to current revision 1-00 (2016-Apr-06) Page Initial production version for release Updated Figure 7 8 Updated Figure 14 14 Updated Figure 19 18 Updated Figure 23 21 Updated Figure 35 29 Updated Figure 68 51 Revision Information
[v1-00] 2016-Apr-06 Document Feedback AS3412 − Content Guide
1 General Description
1 Key Benefits & Features
1 Applications
2 Block Diagram
3 Pin Assignment
3 Pin Description
5A b s o l u t e M a x i m u m R a t i n g s
7 Electrical Characteristics
9 Detailed Description
9A u d i o L i n e I n p u t
10 Parameter
10 Microphone Inputs
11 Input Capacitor Selection
14 Parameter
17 Microphone Supply
18 Parameter
19 Headphone Amplifier
21 Parameter
25 Integrated Music Bypass Switch
26 Parameter
28 Operational Amplifier
29 Parameter
31 System
31 Power Up/Down Conditions
32 Start-Up Sequence
33 Operation Modes
34 Full Slider Mode
35 Slider Mode
36 Push Button Mode
37 Playback Only Mode
38 VNEG Charge Pump
38 Parameter
39 OTP Memory and Internal Registers
41 OTP Read/Write and Load Access
42 OTP Fuse Process
47 2 Wire Serial Interface
47 Protocol
50 Parameter
52 Register Description
52 Register Overview
55 Detailed Register Description
55 System Registers
57 OTP Register
69 Evaluation Register
Document Feedback [v1-00] 2016-Apr-06 AS3412 − Content Guide