AS1106WE

AS1106 AMSOSRAM | Alldatasheet

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Technical content

The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30

8141 Unterpremstaetten, Austria

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1 General Description

need for continuous device reprogramming. directly address each segment. be reset by software, and an external clock is also supported. Several test modes are available for easy application debugging. The devices are available in a SOIC 24Qpin package. Figure 1. AS1106, AS1107 - Typical Application Diagram

2 Key Features

3 Applications

equipment, industrial controllers and panel meters.

8 Digits

8 Segments

4 Pin Assignments

Figure 2. Pin Assignments (Top View)

4.1 Pin Descriptions

11 DIG 0:DIG 7

are highQimpedance when turned off. 4, 9 GND Ground . Both GND pins must be connected.

12 LOAD/CSN

13 CLK

the AS1107 or AS1106 SPIQenabled, the CLK input is active only while LOAD/CSN is low. Selecting RS ET Resistor Value and Using External Drivers on page 14). 9 VDD Positive Supply Voltage . Connect to +2.7 to +5.5V supply. pin is used to daisyQchain several AS1106/AS1107 devices and is never highQimpedance.

www.austriamicrosystems.com/LEDQDriverQICs/AS1106_07 Revision 2.29 3 Q 20 AS1106, AS1107 Datasheet Q Absolute Maximum Ratings

5 Absolute Maximum Ratings

Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute m aximum rating conditions for extended periods may affect device reliability. T able 2. Absolute Maximum Ratings Parameter Min Max Units Notes Electrical Parameters VDD to GND Q0.3 7 V All other pins to GND Q0.3 VDD + 0.3 (max 7V) V Current DIG 0:DIG 7 Sink Current 500 mA SEG A:SEG G, SEG DP 100 mA LatchQUp Immunity ±200 mA All pins except AS1106 pin 14: ±180 mA Norm: JEDEC 78 Electrostatic Discharge Digital outputs 1000 V Norm: MIL 883 E method 3015 All other pins 1000 V Continuous Power Dissipation (TA = +85°C) Wide SOIC 941 mW Derate 11.8mW/ºC above +70ºC Temperature Ranges and Storage Conditions Storage Temperature Range Q55 +150 ºC Package Body Temperature (Wide SOIC) +260 ºC The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/ JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead finish for PbQfree leaded packages is matte tin (100% Sn). Humidity 5 85 % NonQcondensing Moisture Sensitive Level 3 Represents a max. floor life time of 168h ams AG Technical content still valid

www.austriamicrosystems.com/LEDQDriverQICs/AS1106_07 Revision 2.29 4 Q 20 AS1106, AS1107 Datasheet Q Electrical Characteristics

6 Electrical Characteristics

parameters with min and max values are guaranteed with production tests or SQC (Statistical Qualification Control) methods. T able 3. Electrical Characteristics Symbol Parameter Conditions Min Typ Max Unit TAMB Operating Temperature Range Q40 +85 ºC VDD Operating Supply Voltage 2.7 5.0 5.5 V IDDSD Shutdown Supply Current All digital inputs at VDD or GND, TAMB = +25ºC 10 µA IDD Operating Supply Current RSET = open circuit. 1 mA All segments and decimal point on; ISEG = Q40mA. 330 fOSC Display Scan Rate 8 digits scanned 500 800 1300 Hz IDIGIT Digit Drive Sink Current VOUT = 0.65V 320 mA ISEG Segment Drive Source Current VDD = 5.0V, VOUT = (VDD Q1V) Q30 Q40 Q45 mA ΔISEG /Δt Segment Current Slew Rate (AS1107 only) TAMB = +25ºC, VDD = 5.0V, VOUT = (VDD Q1V) 10 20 50 mA/µs ΔISEG Segment Drive Current Matching 3.0 % IDIGIT Digit Drive Leakage (AS1107 only) Digit off, VDIGIT = VDD Q10 µA ISEG Segment Drive Leakage (AS1107 only) Segment off, VSEG = 0V 1 µA IDIGIT Digit Drive Source Current (AS1106 only) Digit off, VDIGIT = (VDD Q 0.3V) Q2 mA ISEG Segment Drive Sink Current (AS1106 only) Segment off, VSEG = 0.3V 5 mA tSLOWBLINK Slow Segment Blink Period (ON phase, Internal Oscillator) 0.64 1 1.65 s tFASTBLINK Fast Segment Blink Period (ON phase, Internal Oscillator) 0.32 0.5 0.83 s Fast or Slow Segment Blink Duty Cycle (Guaranteed by design) 49.9 50 50.1 % T able 4. Logic Inputs/Outputs Characteristics Symbol Parameter Conditions Min Typ Max Unit IIH, IIL Input Current DIN, CLK, LOAD/CSN VIN = 0V or VDD Q1 1 µA VIH Logic High Input Voltage 0.7 x VDD V VIL Logic Low Input Voltage VDD = 5.0V ± 10% 0.8 V VDD = 3.0V ± 10% 0.6 VOH Output High Voltage DOUT, ISOURCE = Q1mA, VDD = 5.0V ± 10% VDD Q 1 V DOUT, ISOURCE = Q1mA, VDD = 3.0V ± 10% VDD Q 0.5 VOL Output Low Voltage DOUT, ISINK = 1.6mA 0.4 V ΔVI Hysteresis Voltage DIN, CLK, LOAD/CSN 1 V ams AG Technical content still valid

www.austriamicrosystems.com/LEDQDriverQICs/AS1106_07 Revision 2.29 5 Q 20 AS1106, AS1107 Datasheet Q Electrical Characteristics T able 5. Timing Characteristics (see Figure 12 on page 8) Symbol Parameter Conditions Min Typ Max Unit tCP CLK Clock Period 100 ns tCH CLK Pulse Width High 50 ns tCL CLK Pulse Width Low 50 ns tCSS CSM Fall to CLK Rise Setup Time (AS1107 or AS1106 SPIQprogrammed) 25 ns tCSH CLK Rise to LOAD/CSN Rise Hold Time 0 ns tDS DIN Setup Time 25 ns tDH DIN Hold Time 0 ns tDO Output Data Propagation Delay CLOAD = 50pF 25 ns tLDCK LOAD Rising Edge to Next Clock Rising Edge (AS1106 only) 50 ns tCSW Minimum LOAD/CSN Pulse High 50 ns tDSPD DataQtoQSegment Delay 2.25 ms ams AG Technical content still valid

7 Typical Operating Characteristics

V DD = 5V, RSET = 9.53kΩ , TAMB = 25ºC (unless otherwise specified). Figure 3. Scan Frequency vs.T emperature Figure 4. Scan Frequency vs. V DD Figure 5. ISEG vs. T emperature Figure 6. ISEG vs. VDD

8 Detailed Description

/square6 The AS1107 segment drivers are slewQrate limited to reduce electromagnetic interference (EMI). /square6 The AS1107 serial interface is fully SPI compatible (programmable for AS1106).

8.2 Serial-Addressing Format

serial interface. A programming sequence consists of 16Qbit packages as listed in Table 6. latched into a digitQ or controlQregister. The LOAD/CSN signal must go high after the 16th rising clock edge. contents of the internal shift register are applied 16.5 clock cycles later to pin DOUT. The data is clocked out at the falling edge of CLK. significant bit (MSB). The exact timing is shown in Figure 12.

8.3 Initial Power-Up

mode. At this time, all registers should be programmed for normal operation. is set to the minimum values. Figure 12. Interface Timing

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8.4 Shutdown Mode

The AS1106/AS1107 devices feature a shutdown mode, where they consume only 10µA (max) current. Shutdown mode is entered via a write to the Shutdown Register (see Table 8). For the AS1106, at that point, all segment curren t sources are pulled to ground and all digit drivers are connected to VDD , so that all segments are blanked. The AS1107 behavior is identical except the drivers are high impedance. Note: During shutdown mode the DigitQRegisters maintain their data. Shutdown mode can either be used as a means to reduce power consumption or for generating a flashing display (repeatedly entering and leaving shutdown mode). For minimum supply current in shutdown mode, logic input should be at GND or VDD (CMOS logic level). The devices need typically 250µs to exit shutdown mode, and during shutdown mode the AS1106/AS1107 is fully programmable. Only the display test mode (see page 11) overrides shutdown mode. When entering or leaving shutdown mode, the Feature Register is reset to its default values (all 0s) when Shutdown Register bit D7 (page 10) = Note: If the AS1106/AS1107 is used with an external clock, Shutdown Register bit D7 should be set to 1 when writing to the Shutdown RegisQ ter.

8.5 Digit- and Control-Registers

The AS1106/AS1107 devices contain 8 DigitQRegisters and 6 controlQregisters, which are listed in Table 7. All registers are selected using a 4Qbit a ddress word, and communication is done via the serial interface. /square6 Digit Registers – These registers are realized with an onQchip 64Qbit memory. Each digit can be controlled directly without rewriting the whole register contents. /square6 Control Registers – These registers consist of decode mode, display intensity, number of scanned digits, shutdown, display test and feaQ tures selection registers. 1. When Shutdown Register bit D7 = 1, the Feature Register is left unchanged when entering or leaving shutdown mode. T able 7. Register Address Map Register HEX Code Address Page D15:D12 D11 D10 D9 D8 NoQOp 0xX0 X 0 0 0 0 13 Digit 0 0xX1 X 0 0 0 1 N/A Digit 1 0xX2 X 0 0 1 0 N/A Digit 2 0xX3 X 0 0 1 1 N/A Digit 3 0xX4 X 0 1 0 0 N/A Digit 4 0xX5 X 0 1 0 1 N/A Digit 5 0xX6 X 0 1 1 0 N/A Digit 6 0xX7 X 0 1 1 1 N/A Digit 7 0xX8 X 1 0 0 0 N/A DecodeQMode 0xX9 X 1 0 0 1 10 Intensity Control 0xXA X 1 0 1 0 12 Scan Limit 0xXB X 1 0 1 1 12 Shutdown 0xXC X 1 1 0 0 10 N/A 0xXD X 1 1 0 1 N/A Feature 0xXE X 1 1 1 0 13 Display Test 0xXF X 1 1 1 1 11 ams AG Technical content still valid

8.5.1 Shutdown Register (0xXC)

The Shutdown Register controls AS1106/AS1107 shutdown mode (see Shutdown Mode on page 9).

8.5.2 Decode Enable Register (0xX9)

bit D1 corresponds to digit 1 and so on). Table 10 lists some examples of the possible settings for th e Decode Enable Register bits. Note: A logic high enables decoding and a logic low bypasses the decoder altogether. When decode mode is used, the decoder looks only at the lowerQnibble (bits D3:D0) of the data in the DigitQRegisters, disregarding bits D6:D4. odeQB font; Table 11 lists the HEX font. hows the 1:1 pairing of each data bit to the appropriate segment line. Figure 13. Standard 7-Segment LED Intensity Control and Inter-Digit Blanking Table 9. Decode Enable Register Format (Address (HEX) = 0xX9))

0 X 0 0 0 0 1 1 1 1 1 1 0

1 X 0 0 0 1 0 1 1 0 0 0 0

2 X 0 0 1 0 1 1 0 1 1 0 1

3 X 0 0 1 1 1 1 1 1 0 0 1

4 X 0 1 0 0 0 1 1 0 0 1 1

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8.5.3 Display-Test Register (0xXF)

The AS1106/AS1107 devices can operate in two modes: normal mode and display test mode. In display test mode all LEDs are switched on at maximum brightness (duty cycle is 15/16 (AS1106) or 31/32 (AS1107). The devices remain in displayQtest mode until the DisplayQTest Register is set for normal operation. Note: All settings of the digitQ and controlQregisters are maintained.

5 X 0 1 0 1 1 0 1 1 0 1 1

6 X 0 1 1 0 1 0 1 1 1 1 1

7 X 0 1 1 1 1 1 1 0 0 0 0

8 X 1 0 0 0 1 1 1 1 1 1 1

9 X 1 0 0 1 1 1 1 1 0 1 1

Blank X 1 1 1 1 0 0 0 0 0 0 0 The decimal point is enabled by setting bit D7 = 1. T able 11. HEX Font 7-Segment Character Register Data On Segments = 1 D6:D4 DP A B C D E F G The decimal point is enabled by setting bit D7 = 1. T able 12. No-Decode Mode Data Bits and Corresponding Segment Lines D7 D6 D5 D4 D3 D2 D1 D0 Corresponding Segment Line DP A B C D E F G T able 13. Display-T est Register Format (Address (HEX) = 0xXF)) Mode Register Data D7 D6 D5 D4 D3 D2 D1 D0 Normal Operation X X X X X X X 0 Display Test Mode X X X X X X X 1 T able 10. Code-B Font (Continued) 7-Segment Character Register Data On Segments = 1 D6:D4 DP A B C D E F G ams AG Technical content still valid

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8.5.4 Intensity Control Register (0xXA)

The brightness of the display can be controlled by digital means using the Intensity Control Register and by analog means using RSET (see Selecting RS ET Resistor Value and Using External Drivers on page 14). D isplay brightness is controlled by an integrated pulseQwidth modulator which is controlled by the lowerQnibble of the Intensity Control Register. The modulator scales the average segmentQcurrent in 16 steps from a maximum of 31/32 down to 1/32 (15/16 to 1/16 for the AS1107) of the peak current set by RSET .

8.5.5 Scan-Limit Register (0x0B)

The ScanQLimit Register controls which of the digits are to be displayed. When all 8 digits are to be displayed, the update frequency is typically 800Hz. If the number of digits displayed is reduced, the update frequency is increased. The frequency can be calculated using 8fOSC/N, where N is the number of digits. Since the number of displayed digits influences the brightness, R SET should be adjusted accordingly. Table 16 lists the m aximum allowed current when fewer than 4 digits are used. Note: To avoid differences in brightness this register should not be used to blank parts of the display (leading zeros). T able 14. Intensity Register Format (Address (HEX) = 0xXA)) Duty Cycle HEX Code Register Data AS1106 AS1107 D7 D6 D5 D4 D3 D2 D1 D0 1/32 (min on) 1/16 (min on) 0xX0 X X X X 0 0 0 0 3/32 2/16 0xX1 X X X X 0 0 0 1 5/32 3/16 0xX2 X X X X 0 0 1 0 7/32 4/16 0xX3 X X X X 0 0 1 1 9/32 5/16 0xX4 X X X X 0 1 0 0 11/32 6/16 0xX5 X X X X 0 1 0 1 13/32 7/16 0xX6 X X X X 0 1 1 0 15/32 8/16 0xX7 X X X X 0 1 1 1 17/32 9/16 0xX8 X X X X 1 0 0 0 19/32 10/16 0xX9 X X X X 1 0 0 1 21/32 11/16 0xXA X X X X 1 0 1 0 23/32 12/16 0xXB X X X X 1 0 1 1 25/32 13/16 0xXC X X X X 1 1 0 0 27/32 14/16 0xXD X X X X 1 1 0 1 29/32 15/16 0xXE X X X X 1 1 1 0 31/32 (max on) 15/16 (max on) 0xXF X X X X 1 1 1 1 T able 15. Scan-Limit Register Format (Address (HEX) = 0xXB)) Scan Limit HEX Code Register Data D7 D6 D5 D4 D3 D2 D1 D0 Display digit 0 only (see Table 16) 0xX0 X X X X X 0 0 0 D isplay digits 0:1 (see Table 16) 0xX1 X X X X X 0 0 1 D isplay digits 0:2 (see Table 16) 0xX2 X X X X X 0 1 0 D isplay digits 0:3 0xX3 X X X X X 0 1 1 Display digits 0:4 0xX4 X X X X X 1 0 0 Display digits 0:5 0xX5 X X X X X 1 0 1 Display digits 0:6 0xX6 X X X X X 1 1 0 Display digits 0:7 0xX7 X X X X X 1 1 1 T able 16. Maximum Segment Current for 1-, 2-, or 3-Digit Displays Number of Digits Displayed Maximum Segment Current (mA) 1 10 2 20 3 30 ams AG Technical content still valid

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8.5.6 Feature Register (0xXE)

The Feature Register is used for enabling various features including switching the device into external clock mode, applying an external reset, selecting codeQB or HEX decoding, enabling or disabling blinking, enabling or disabling the SPIQcompatible interface (AS1106 only), setting the blinking rate, and resetting the blink timing. Note: At powerQup the Feature Register is initialized to 0.

8.5.7 No-Op Register (0xX0)

The NoQOp Register is used when multiple AS1106 or AS1107 devices are cascaded in order to support displays with more than 8 digits. The cascading must be done in such a way that all DOUT pins are connected to DIN of the next AS1106/AS1107 (see Figure 14 on page 16). The LOAD/CSN and CLK signals are connected to all devices. For example, if five devices are cascaded, in order to perform a write operation to the fifth device, the writeQcommand must be followed by four noQoperation commands. When the LOAD/CSN signal goes high, all shift registers are latched. The first four devices will receive noQoperation commands and only the fifth device will receive the intended operation command, and subsequently update its register. T able 17. Feature Register Summary D7 D6 D5 D4 D3 D2 D1 D0 blink_ start sync blink_ freq_sel blink_en spi_en decode_sel reg_res clk_en T able 18. Feature Register Bit Descriptions (Address (HEX) = 0xXE)) Addr: 0xXE Feature Register Enables and disables various device features. Bit Bit Name Default Access Bit Description D0 clk_en 0 R/W External clock active. 0 = Internal oscillator is used for system clock. 1 = Pin CLK of the serial interface operates as system clock input. D1 reg_res 0 R/W Resets all control registers except the Feature Register. 0 = Reset Disabled. Normal operation. = All control registers are reset to default state (except the Feature Register) identically after powerQup. Note: The Digit Registers maintain their data. D2 decode_sel 0 R/W Selects display decoding. 0 = Enable CodeQB decoding (see Table 10 on page 10). 1 = Enable HEX decoding (see Table 11 on page 11). D3 spi_en 0 R/W Enables the SPIQcompatible interface. 0 = Disable SPIQcompatible interface (AS1106 only). 1 = Enable the SPIQcompatible interface (AS1106 only). Note: The SPIQcompatible interface is always enabled in the AS1107. D4 blink_en 0 R/W Enables blinking. 0 = Disable blinking. 1 = Enable blinking. D5 blink_freq_sel 0 R/W Sets blink with low frequency (with the internal oscillator enabled): 0 = Blink period typically is 1 second (0.5s on, 0.5s off). 1 = Blink period is 2 seconds (1s on, 1s off). D6 sync 0 R/W Synchronizes blinking on the rising edge of pin LOAD/CSN. The multiplex and blink timing counter is cleared on the rising edge of pin LOAD/CSN. By setting this bit in multiple AS1106/AS1107 devices, the blink timing can be synchronized across all the devices. D7 blink_start 0 R/W Start Blinking with display enabled phase. When bit D4 (blink_en) is set, bit D7 determines how blinking starts. 0 = Blinking starts with the display turned off. 1 = Blinking starts with the display turned on. ams AG Technical content still valid

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9 Application Information

9.1 Supply Bypassing and Wiring

In order to achieve optimal performance the AS1106/AS1107 should be placed very close to the LED display to minimize effects of electromagnetic interference and wiring inductance. Furthermore, it is recommended to connect a 10µF electrolytic and a 0.1µF ceramic capacitor between pins V DD and GND to avoid power supply ripple (see Figure 14 on page 16). Note: Both GND pins must be connected to ground.

9.2 Selecting R SET Resistor Value and Using External Drivers

Brightness of the display segments is controlled via RSET . The current that flows between VDD and ISET defines the current that flows through the LEDs. Segment current is about 200 times the current in ISET . Typical values for RSET for different segment currents, operating voltages, and LED voltage drop (VLED ) are given in Tables 19 Q 23. The maximum current the AS1106/AS1107 devices can drive is 40mA. If higher currents are needed, external drivers must be used, in which case it is no longer necessary that the devices drive high currents. In cases where the devices only drive a few digits, Table 16 specifies the maximum currents, and R SET must be set accordingly. Note: The display brightness can also be logically controlled (see Intensity Control Register (0xXA) on page 12). T able 19. RSET vs. Segment Current and LED Forward Voltage, V DD = 2.7V ISEG (mA) V LED (V) 1.5 2.0 40 5k Ω 4.4kΩ 30 6.9k Ω 5.9kΩ 20 10.7k Ω 9.6kΩ 10 22.2k Ω 20.7kΩ T able 20. RSET vs. Segment Current and LED Forward Voltage, V DD = 3.3V ISEG (mA) V LED (V) 1.5 2.0 2.5 40 6.7k Ω 6.4kΩ 5.7kΩ 30 9.1k Ω 8.8kΩ 8.1kΩ 20 13.9k Ω 13.3kΩ 12.6kΩ 10 28.8k Ω 27.7kΩ 26kΩ T able 21. RSET vs. Segment Current and LED Forward Voltage, V DD = 3.6V ISEG (mA) V LED (V) 1.5 2.0 2.5 3.0 40 7.5k Ω 7.2kΩ 6.6kΩ 5.5kΩ 30 10.18k Ω 9.8kΩ 9.2kΩ 7.5kΩ 20 15.6k Ω 15kΩ 14.3kΩ 13kΩ 10 31.9k Ω 31kΩ 29.5kΩ 27.3kΩ T able 22. RSET vs. Segment Current and LED Forward Voltage, V DD = 4.0V ISEG (mA) V LED (V) ams AG Technical content still valid

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9.3 Calculating the Power Dissipation

The upper limit for power dissipation (PD) for the AS1106/AS1107 is determined from the following equation: PD = (VDD x 1mA) + (VDD - VLED )(DUTY x I SEG x N) (EQ 1) Where: VDD is the supply voltage. DUTY is the duty cycle set by intensity register (page 12). N is the number of segments driven (worst case is 8) VLED is the LED forward voltage ISEG = segment current set by RSET Dissipation Example: ISEG = 40mA, N = 8, DUTY = 31/32, VLED = 1.8V at 40mA, VDD = 5.25V (EQ 2) Thus, for a PDIP package Θ JA = +75°C/W (from Table 24), the maximum allowed TAMB is given by: T J,MAX = TAMB + PD x Θ JA = 150°C = TAMB +1.07W x 75°C/W (EQ 4) Where: T AMB = +69.4°C. The TAMB limit for SO Packages in the dissipation example above is +58.6°C. T able 23. RSET vs. Segment Current and LED Forward Voltage, V DD = 5.0V ISEG (mA) V LED (V) T able 24. Package Thermal Data Package Thermal Resistance ( Θ JA)

24 Wide SOIC +85°C/W

Technical content still valid

The application example in Figure 14 shows the AS1106 as an 8x8 LED dot matrix driver. the 64 LEDs can be addressed separately. The columns are selected via the digits as listed in Table 7 on page 9. addressed as described in Table 12 on page 11, where bit D0 corresponds to segment G and bit D7 corresponds to segment DP. Note: For a multipleQdigit dot matrix, multiple AS1106 devices must be cascaded. Figure 14. Application Example as LED Dot Matrix Driver

9.5 Cascading Drivers

value so that one display will not appear brighter than the other. Note: Refer to NoQOp Register (0xX0) on page 13 for additional information.

Figure 15. AS1106, AS1107 Marking

Figure 16. SOIC 24-pin Package

www.austriamicrosystems.com/LEDQDriverQICs/AS1106_07 Revision 2.29 1 9 Q 20 AS1106, AS1107 Datasheet Q Ordering Information The AS1106 and AS1107 are available as the standard products shown in Table 26. Note: All products are RoHS compliant and austriamicrosystems green. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect Technical Support is found at http://www.austriamicrosystems.com/TechnicalQSupport For further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor T able 26. Ordering Information Ordering Code Marking Description Temperature Range Delivery Form Package AS1106WL AS1106WL 8QDigit LED Display Drivers 0 to +70°C Tubes SOIC 24Qpin AS1106WLQT AS1106WL 8QDigit LED Display Drivers 0 to +70°C Tape and Reel SOIC 24Qpin AS1106WE AS1106WE 8QDigit LED Display Drivers Q40 to +85°C Tubes SOIC 24Qpin AS1106WEQT AS1106WE 8QDigit LED Display Drivers Q40 to +85°C Tape and Reel SOIC 24Qpin AS1107WL AS1107WL 8QDigit LED Display Drivers Q40 to +85°C Tubes SOIC 24Qpin AS1107WLQT AS1107WL 8QDigit LED Display Drivers Q40 to +85°C Tape and Reel SOIC 24Qpin ams AG Technical content still valid

www.austriamicrosystems.com/LEDQDriverQICs/AS1106_07 Revision 2.29 2 0 Q 20 AS1106, AS1107 Datasheet Copyrights Copyright © 1997Q2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, AustriaQEurope. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical lifeQsupport or lifeQsustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 AQ8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact ams AG Technical content still valid