ARA2004 ANADIGICS | Alldatasheet

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Technical content

Reverse Amplifier with Step Attenuator Data Sheet - Rev 2.1

FEATURES

  • Low Cost Integrated Amplifier with Step Attenuator
  • Attenuation Range: 0-58 dB, adjustable in 1 dB increments via a 3 wire serial control
  • Meets DOCSIS distortion requirements at +60 dBmV output signal level
  • Low distortion and low noise
  • Frequency range: 5-100 MHz
  • 5 Volt operation
  • -40 to +85 oC temperature range
  • RoHS Compliant Package Option

APPLICATIONS

  • MCNS/DOCSIS Compliant Cable Modems
  • CATV Interactive Set-Top Box
  • Telephony over Cable Systems
  • OpenCable Set-Top Box
  • Residential Gateway PRODUCT DESCRIPTION The ARA2004 is designed to provide the reverse path amplification and output level control functions in a CATV Set-Top Box or Cable Modem. It incorporates a digitally controlled precision step attenuator that is preceded by an ultra low noise amplifier stage, and followed by an ultra-linear output driver amplifier. This device uses a balanced circuit design that exceeds the MCNS/DOCSIS requirement for harmonic Figure 1: Cable Modem or Set Top Box Application Diagram

28 Pin SSOP

44 MHz

performance at a +60 dBmV output level while only requiring a single polarity +5 V supply. Both the input and output are matched to 75 ohms with an appropriate transformer. The precision attenuator provides up to 58 dB of attenuation in 1 dB increments via a three-wire serial interface. With external passive components, this device meets IEC 1000-4-12 and ANSI/IEEE C62.41-1991 100KHz ringwave tests, as well as IEC1000-4-5 1.2/50 µS surge tests. The ARA2004 is offered in a 28-pin SSOP package featuring a heat slug on the bottom of the package.

Data Sheet - Rev 2.1 ARA2004 Table 1: Pin Description NIP EMAN NOITPIRCSED NIP EMAN NOITPIRCSED 1D NGd nuorG5 1C /Nn oitcennoCoN )1( 2V NTTA rotaunettArofylppuS6 1C /Nn oitcennoCoN )1( 3T TA NI )+(t upnI)+(rotaunettA )2( 71C /Nn oitcennocoN )1(

41 A TUO )+(t uptuO)+(1AreifilpmA8 1D NG SOMC

51 A NI )+(t upnI)+(1AreifilpmA )2( 91T TA TUO )-(t uptuO)-(rotaunettA )2(

61 gVl ortnoC)-/+(1AreifilpmA0 22 A NI )-(t upnI)-(2AreifilpmA )2( 7I 1TES tnerruC)-/+(1AreifilpmA tsujdA 122 A TUO )-(t uptuO)-(2AreifilpmA

81 A NI )-(t upnI)-(1AreifilpmA )2( 22I 2TES

)-/+(2AreifilpmA tsujdAtnerruC

91 A TUO )-(t uptuO)-(1AreifilpmA3 22 gVl ortnoC)-/+(2AreifilpmA

01T TA NI )-(t upnI)-(rotaunettA )2( 422 A TUO )+(t uptuO)+(2AreifilpmA 11V SOMC latigiDroFylppuS tiucriCSOMC 522 A NI )+(t upnI)+(2AreifilpmA )2( 21K LCk colC6 2T TA TUO )+(t uptuO)+(rotaunettA )2( 31T ADa taD7 2C /Nn oitcennoCoN )1( 41n Ee lbanE8 2D NGd nuorG Notes: (1) All N/C pins should be grounded. (2) Pins should be AC-coupled. No external DC bias should be applied.

4 Data Sheet - Rev 2.1 ARA2004

ELECTRICAL CHARACTERISTICS

)42,12,9,4,2snip(ylppuSgolanA0 9 C DV V:ylppuSlatigiD CMOS )11nip(0 6 C DV )32,6snip(2gV,1gVslortnoCreifilpmA5 -2 V FR stupnItarewoP snip( 8,5 ) -0 6+V mBd )41,31,21snip(ecafretnIlatigiD5 .0-V CMOS 5.0+V erutarepmeTegarotS5 5-0 02+ 0C erutarepmeTgniredloS- 0 62 0C emiTgniredloS- 5 c eS Table 2: Absolute Minimum and Maximum Ratings Table 3: Operating Ranges RETEMARAP NIM PYT XAM TINU V:ylppuSreifilpmA DD )42,12,9,4snip(5 .45 7 C DV V:ylppuSrotaunettA ATTN )2nip(V DD 5.0-57 C DV V:ylppuSlatigiD CMOS )11nip(0 .3-5 .5C DV ecafretnIlatigiD0 - V CMOS V )32,6snip(2gV,1gVslortnoCreifilpmA5 -1 2 V erutarepmeTesaC0 4-5 25 8 0C Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability. The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications. Notes: 1. Pins 3, 5, 8, 10, 19, 20, 25 and 26 should be AC-coupled. No external DC bias should be applied. 2. Pins 7 and 22 should be grounded or pulled to ground through a resistor. No external DC bias should be applied.

Data Sheet - Rev 2.1 ARA2004 RETEMARAP NIM PYT XAM TINU STNEMMOC )9,4snip(tnerruC1AreifilpmA - 4.2

6 Am delbanexT

)42,12snip(tnerruC2AreifilpmA - 7.3 021

9 Am delbanexT

)2nip(tnerruCrotaunettA- 9 5 1A m noitpmusnoCrewoPlatoT - 76.0 80.1 051 W Wm delbanexT delbasidxT Note: As measured in ANADIGICS test fixture Table 4: DC Electrical Specifications TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled) RETEMARAP NIM PYT XAM TINU STNEMMOC )zHM01(niaG5 .723 .925 .03B dg nittesnoitaunettaBd0 ssentalFniaG - 57.0 5.1 - Bd zHM24ot5 zHM56ot5 erutarepmeTrevonoitairaVniaG- 6 00.0-- C °/Bd Bd1spetSnoitaunettA Bd2 Bd4 Bd8 Bd61 Bd23 56.0 6.1 6.3 5.7 0.51 2.03 38.0 07.1 57.3 57.7 04.51 57.03 00.1 50.2 0.4 0.8 8.51 3.13 Bdc inotonoM noitaunettAmumixaM6 .853 .06- B d 2 dn leveLnoitrotsiDcinomraH )zHM01( -5 7-3 5-c Bds mhO57otniVmBd06+ 3 dr leveLnoitrotsiDcinomraH )zHM01( -0 6-3 5-c Bds mhO57otniVmBd06+ 3 dr tpecretnItuptuOredrO8 7- - V mBd tnioPnoisserpmoCniaGBd1- 5 .86- V mBd erugiFesioN- 0 .30 .4B ds solnulabtupnisedulcnI Table 5: AC Electrical Specifications TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)

6 Data Sheet - Rev 2.1 ARA2004 RETEMARAP NIM PYT XAM TINU STNEMMOC rewoPesioNtuptuO .teS.nettA.niM/langiSoN/evitcA .teS.nettA.xaM/langiSoN/evitcA 5.83- 8.35- VmBdh tdiwdnabzHk061ynA zHM24ot5morf edomelbasidxTni)zHM54(noitalosI- 5 6-B d tuptuoniecnereffiD xTneewteblangis elbasidxTdnaelbane ecnadepmItupnIlaitnereffiD- 0 03- s mhO 8dna5snipneewteb )delbanexT( ecnadepmItupnI- 5 7- s mhO remrofsnarthtiw )delbanexT( ssoLnruteRtupnI )ecnadepmicitsiretcarahcmhO57( 02- 21- - Bd delbanexT delbasidxT ecnadepmItuptuOlaitnereffiD- 0 03- s mhO4 2dna12snipneewteb ecnadepmItuptuO- 5 7- s mhOr emrofsnarthtiw ssoLnruteRtuptuO )ecnadepmicitsiretcarahcmhO57( 71- 51- 21- 01- Bd delbanexT delbasidxT tneisnarTegatloVtuptuO elbasidxT/elbanexT 001 7 p-pVm gnittesrotaunettaBd0 gnittesrotaunettaBd42 Note: As measured in ANADIGICS test fixture continued: AC Electrical Specifications TA=25°C; VDD, VATTN, VCMOS = +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)

Data Sheet - Rev 2.1 ARA2004 Figure 4: Test Circuit 22 7 GND ISET1 Vg1 A1IN (+) A1OUT (+) ATTIN (+) VATTN VCMOS CLK DAT En N/C A2OUT (-) ISET2 A2IN (-) Vg2 ATTOUT (-) GNDCMOS A2IN (+) A2OUT (+) N/C N/C N/C GND A1IN (-) A1OUT (-) ATTIN (-) ATTOUT (+) (75 Ohms) 470pF 470pF 1K Ohms 470pF 2K Ohms Turns Ratio 2:1 1500pF RF Output (75 Ohms) 0 / +3 V Control A2 +5 V 1uF 0.1uF

3.9 Ohms

+5 V 1000pF 1000pF1.2K Ohms RF Input 0 / +3 V Control A1 +5 V 1.2K Ohms 1000pF1000pF 1uF 0.1uF 1K Ohms 470pF 2K Ohms ARA2004 10uH 10uH 1uF 0.1uF +5 V 1uF 0.1uF Note: Tx Enable: Control A1 and Control A2 = +3V Tx Disable: Control A1 and Control A2 = 0V Toko Balun 616PT-1030 2K Ohms 2K Ohms Turns Ratio 1:2

12 Data Sheet - Rev 2.1 ARA2004 DATA CLOCK ENABLE ENABLE OR D7: MSB D 6 D4 D3 D1 D0: LSB Table 6: Programming Word TIBATAD D7 D6 D5 D4 D3 D2 D1 D0 eulaV 7P6 P5 P4 P3 P2 P1 P0 P LOGIC PROGRAMMING Table 7: Data Description Figure 17: Serial Data Input Timing EULAV NOITCNUF )ssapyb=0,no=1( 7PA /N 6PA /N 5Pt iBrotaunettABd23 4Pt iBrotaunettABd61 3Pt iBrotaunettABd8 2Pt iBrotaunettABd4 1Pt iBrotaunettABd2 0Pt iBrotaunettABd1 Programming Instructions The programming word is set through an 8 bit shift register via the data, clock and enable lines. The data is entered in order with the most significant bit (MSB) first and the least significant bit (LSB) last. The enable line must be low for the duration of the data entry, then set high to latch the shift register. The rising edge of the clock pulse shifts each data value into the register.

Data Sheet - Rev 2.1 ARA2004

APPLICATION INFORMATION

The ARA2004 includes two amplification stages that each can be shut down through external control pins Vg1 and Vg2 (pins 6 and 23, respectively.) By applying a slightly positive bias of typically +1.0 Volts, the amplifier is enabled. In order to disable the amplifier, the control pin needs to be pulled to ground. A practical way to implement the necessary control is to use bias resistor networks similar to those shown in the test circuit schematic (Figure 4.) Each network includes a resistor shunted to ground that serves as a pull-down to disable the amplifier when no control voltage is applied. When a positive voltage is applied, the network acts as a voltage divider that presents the required +1.0 Volts to enable the amplifier. By selecting different resistor values for the voltage divider, the network can accommodate different control voltage inputs. The Vg1 and Vg2 pins may be connected together directly, and controlled through a single resistor network from a common control voltage. Amplifier Bias Current The I SET pins (7 and 22) set the bias current for the amplification stages. Grounding these pins results in the maximum possible current. By placing a resistor from the pin to ground, the current can be reduced. The recommended bias conditions use the configuration shown in the test circuit schematic in Figure 4. Thermal Layout Considerations The device package for the ARA2004 features a heat slug on the bottom of the package body. Use of the heat slug is an integral part of the device design. Soldering this slug to the ground plane of the PC board will ensure the lowest possible thermal resistance for the device, and will result in the longest MTF (mean time to failure.) A PC board layout that optimizes the benefits of the heat slug is shown in Figure 18. The via holes located under the body of the device must be plated through to a ground plane layer of metal, in order to provide a sufficient heat sink. The recommended solder mask outline is shown in Figure 19. Figure 18: PC Board Layout

14 Data Sheet - Rev 2.1 ARA2004 Figure 19: Solder Mask Outline Output Transformer Matching the output of the ARA2004 to a 75 Ohm load is accomplished using a 2:1 turns ratio transformer. In addition to providing an impedance transformation, this transformer provides the bias to the output amplifier stage via the center tap. The transformer also cancels even mode distortion products and common mode signals, such as the voltage transients that occur while enabling and disabling the amplifiers. As a result, care must be taken when selecting the transformer to be used at the output. It must be capable of handling the RF and DC power requirements without saturating the core, and it must have adequate isolation and good phase and amplitude balance. It also must operate over the desired frequency and temperature range for the intended application. ESD Sensitivity Electrostatic discharges can cause permanent damage to this device. Electrostatic charges accumulate on test equipment and the human body, and can discharge without detection. Although the ARA2004 has some built-in ESD protection, proper precautions and handling are strongly recommended. Refer to the ANADIGICS application note on ESD precautions.

Data Sheet - Rev 2.1 ARA2004 Figure 20: S12 Package Outline - 28 Pin SSOP with Heat Slug PACKAGE OUTLINE

Data Sheet - Rev 2.1 ARA2004 NOTES

18 Data Sheet - Rev 2.1 ARA2004 NOTES

Data Sheet - Rev 2.1 ARA2004 NOTES

ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product in any such application without written consent is prohibited. IMPORTANT NOTICE ANADIGICS, Inc.

141 Mount Bethel Road

Warren, New Jersey 07059, U.S.A. Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com E-mail: Mktg@anadigics.com ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. Data Sheet - Rev 2.1 ARA2004

ORDERING INFORMATION

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