ARA05050 ANADIGICS | Alldatasheet

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Technical content

Reverse Amplifier with Step Attenuator Data Sheet - Rev 2.2

FEATURES

  • Low Cost Integrated Monolothic GaAs Amplifier With Step Attenuator
  • Attenuation Range: 0-30 dB, Adjustable In 2dB Increments Via a 4 Wire Parallel Control
  • Meets DOCSIS Distortion Requirements at +58dBmV Output Signal Level
  • Low Distortion and Low Noise
  • Low Signal toNoise Ratio at All Gain Levels
  • Frequency Range: 5-100 MHz
  • 5 Volt Operation
  • RoHS-Compliant Package Option

APPLICATIONS

  • MCNS/DOCSIS Compliant Cable Modems
  • CATV Interactive Set-Top Box
  • OpenCable Set-Top Box
  • Fiber Nodes
  • Cable Modem Termination Systems (CMTS) PRODUCT DESCRIPTION The ARA05050 is a GaAs IC designed to provide the reverse path amplification and output level control functions in a CATV Set-Top Box or Cable Modem. It incorporates a digitally controlled precision step attenuator that is preceded by an ultra low noise amplifier stage, and followed by an ultra-linear output driver amplifier. This device is capable of meeting the MCNS/DOCSIS requirements for harmonic

Figure 1. Cable Modem or Set Top Box Application Diagram

28 Pin SSOP with Heat Slug

44 MHz

and is available in a RoHS-compliant option.

Data Sheet - Rev 2.2 ARA05050 Table 1: Pin Description NIP EMAN NOITPIRCSED NIP EMAN NOITPIRCSED 1C /Nn oitcennoCoN )1( 51B d4t iBlortnoCnoitunettABd4 2s sapyBs sapyblanretnI6 1B d2t iBlortnoCnoitunettABd2 3T TA NI tupnIrotaunettA )2( 71D NGd nuorG 4F R 1TUO dnatuptuO1AreifilpmA ylppuS 81F R TUO dnatuptuO2AreifilpmA ylppuS 5V 1FER rofegatloVecnerefeR 1AreifilpmA 91V 2FER rofegatloVecnerefeR 2AreifilpmA 6T TA 1GCA 1dnuorGCArotaunettA )3( 02T TA 2GCA 2dnuorGCArotaunettA )3( 7T TA 1GCA 1dnuorGCArotaunettA )3( 12T TA 2GCA 2dnuorGCArotaunettA )3( 8T TA 1GCA 1dnuorGCArotaunettA )3( 22T TA 2GCA 2dnuorGCArotaunettA )3( 9T TA 1GCA 1dnuorGCArotaunettA )3( 32T TA 2GCA 2dnuorGCArotaunettA )3( 01F R NI tupnI1AreifilpmA )4( 42F R 2NI tupnI2AreifilpmA )4( 11I 1TES tsujdAtnerruC1AreifilpmA )4( 52I 2TES tsujdAtnerruC2AreifilpmA )4( 21V TTA ylppuSrotaunettA6 2T TA TUO tuptuOrotaunettA )2( 31B d61t iBlortnoCnoitunettABd617 2C /Nn oitcennoCoN )1( 41B d8t iBlortnoCnoitunettABd288 2C /Nn oitcennoCoN )1( Notes: (1) All N/C pins should be grounded. (2) Pins should be AC-coupled. No external DC bias should be applied. (3) Pins should be AC-grounded. No external DC bias should be applied. (4) Pins should be grounded or pulled to ground through a resistor. No external DC bias should be applied.

4 Data Sheet - Rev 2.2 ARA05050

ELECTRICAL CHARACTERISTICS

V:ylppuSgolanA SUP )81,21,4snip(0 9 C DV )91,5snip(segatloVecnerefeRreifilpmA5 .2- VSUP

2 CDV

FR stupnIreifilpmAtarewoP snip( 42,01 ) -0 6+V mBd )61,51,41,31snip(slortnoCrotaunettA0 6 V erutarepmeTegarotS5 5-0 02+ oC erutarepmeTgniredloS- 0 62 oC emiTgniredloS- 5 c eS Table 2: Absolute Minimum and Maximum Ratings Table 3: Operating Ranges RETEMARAP NIM PYT XAM TINU V:ylppuSreifilpmA DD )81,4snip(5 .45 7 C DV V:ylppuSrotaunettA ATTN )21nip(V DD 5.0-57 C DV )61,51,41,31snip(slortnoCrotaunettA0 - 5 .5V )91,5snip(segatloVecnerefeRreifilpmA- 5 7.1-C DV erutarepmeTesaC0 4-5 25 8 oC Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability. The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications. Notes: 1. Pins 3 and 26 should be AC-coupled. No external DC bias should be applied. 2. Pins 10, 11, 24 and 25 should be grounded or pulled to ground through a resistor. No external DC bias should be applied. 3. Pins 6, 7, 8, 9, 20, 21, 22 and 23 should be AC-grounded. No external DC bias should be applied.

Data Sheet - Rev 2.2 ARA05050 RETEMARAP NIM PYT XAM TINU )4nip(tnerruC1AreifilpmA- 5 75 9A m )81nip(tnerruC2AreifilpmA- 0 010 31A m )21nip(tnerruCrotaunettA- 8 - A m noitpmusnoCrewoPlatoT- 2 9.02 .1W Notes: (1) See Figures 5 and 6 for performance at higher frequencies. All specifications as measured in ANADIGICS test fixture. Table 4: DC Electrical Specifications TA=25°C; VDD, VATTN = +5.0 VDC Table 5: AC Electrical Specifications TA=25°C; VDD, VATTN = +5.0 VDC RETEMARAP NIM PYT XAM TINU STNEMMOC )zHM01(niaG 05050ARA R05050ARA

33 Bdg nittesnoitaunettaBd0

ssentalFniaG- 5 7.05 .1B dz HM001ot5 erutarepmeTrevonoitairaVniaG- 6 00.0--C °/Bd spetSnoitaunettA Bd2 Bd4 Bd8 Bd61 6.1 8.3 0.8 0.61 58.1 0.4 3.8 6.61 2.2 2.4 5.8 0.71 Bd zHM24ot5 )1( , cinotonoM 2 dn leveLnoitrotsiDcinomraH zHM5 zHM52 06- 36- 55- 55- cBds mhO57otniVmBd85+ 3 dr leveLnoitrotsiDcinomraH zHM5 zHM52 36- 36- 06- 06- cBds mhO57otniVmBd85+ 3 dr tpecretnItuptuOredrO8 7- - V mBd tnioPnoisserpmoCniaGBd1- 0 7- V mBd erugiFesioN- 7 .15 .2B d

6 Data Sheet - Rev 2.2 ARA05050 RETEMARAP NIM PYT XAM TINU STNEMMOC rewoPesioNtuptuO .teS.nettA.niM/langiSoN/evitcA .teS.nettA.xaM/langiSoN/evitcA 6.73- 6.45- VmBdh tdiwdnabzHk061ynA zHM24ot5morf ecnadepmItupnI- 5 7- s mhO ssoLnruteRtupnI- 0 2-5 1-B dm etsysmhO57 ecnadepmItuptuO- 5 7- s mhO ssoLnruteRtuptuO- 0 2-5 1-B dm etsysmhO57 Note: As measured in ANADIGICS test fixture continued: AC Electrical Specifications TA=25°C; VDD, VATTN = +5.0 VDC RETEMARAP NIM PYT XAM TINU STNEMMOC cigoLlortnoCrotaunettA )1( VIN,LOW VIN,HIGH 8.2 5.0 5.5 V egats.nettasessapyB egats.nettaselbanE ecnadepmIlortnoCrotaunettA- K 5- s mhO Table 6: Logic Interface Specifications TA=25°C; VDD, VATTN = +5.0 VDC (NOITAUNETTAd ) B 02468 0 12 14 16 18 10 22 24 26 28 20 3 )61nip(tupnIcigoLBd2 LHLHLHLHLHLHLHLH )51nip(tupnIcigoLBd4 LLHHLLHHLLHHLLHH )41nip(tupnIcigoLBd8 LLLL HHHHL L L LHHHH )31nip(tupnIcigoLBd61 LLLLLLLLH H HHHHHH Note: “L” = logic low, “H” = logic high Table 7: Attenuator Logic Note: (1) Specification applies when 470 Ohm resistor is connected from pin 2 to ground (see test circuit in Figure 4).

Data Sheet - Rev 2.2 ARA05050 Figure 4: Test Circuit 22 7 GND ISET1 ATTACG1 RFOUT1 ATTIN VATT 16 dB 8 dB 4 dB ISET2 RFIN2 2 dB RFIN N/C ATTOUT VREF1 RFOUT ATTACG1 ATTACG1 ATTACG1 VREF2 ATTACG2 ATTACG2 ATTACG2 ATTACG2 Bypass N/C N/C (75 Ohms) 0.1uF RF Output (75 Ohms)

3.9 Ohms

+5 V RF Input +5 V

620 Ohms

0.1uF 0.01uF 1uF 0.01uF ARA05050 10uH 0.01uF1uF

20 Ohms

0.1uF 0.1uF 1pF 3.3K Ohms 1.8K Ohms 1uF 5K Ohms 0.01uF 1uF 0.1uF 5K Ohms +5 V 1uF 0.01uF 10uH 3.3K Ohms 1.8K Ohms 1uF 0.1uF 0.1uF

470 Ohms

(see note) Note: The 470 Ohm resistor from pin 2 to ground is installed for 3V attenuator control logic levels. For 5V logic, the 470 Ohm resistor is removed.

10 Data Sheet - Rev 2.2 ARA05050

APPLICATION INFORMATION

Printed Circuit Board Layout Considerations The ARA05050 is a high-performance RF device. Special consideration must be given to certain features of the the printed circuit board layout, as they can affect the RF performance of the IC. Refer to the ANADIGICS application note “CATV Reverse Amp w/ Step Attenuator” for more details. Amplifier Enable / Disable The ARA05050 includes two amplification stages that each can be shut down through external control pins V REF1 and V REF2 (pins 5 and 19, respectively.) By applying a typical bias of 1.75 Volts to these pins, the amplifiers are enabled. In order to fully disable an amplifier, its control pin requires a negative bias of -1.5 to -2.0 Volts. Amplifier Bias Current The I SET pins (11 and 25) set the bias current for the amplification stages. Grounding these pins results in the maximum possible current. By placing a resistor from the pin to ground, the current can be reduced. The recommended bias conditions use the configuration shown in the test circuit schematic in Figure 4. Thermal Layout Considerations The device package for the ARA05050 features a heat slug on the bottom of the package body. Use of the heat slug is an integral part of the device design. Soldering it to the ground plane of the PC board will ensure the lowest possible thermal resistance for the device, and will result in the longest MTF (mean time to failure.) A PC board layout that optimizes the benefits of the heat slug is shown in Figure 13. The via holes located under the body of the device must be plated through to a ground plane layer of metal, in order to provide sufficient thermal conductivity. The recommended solder mask outline is shown in Figure 14. ESD Sensitivity Electrostatic discharges can cause permanent damage to this device. Electrostatic charges accumulate on test equipment and the human body, and can discharge without detection. Proper precautions and handling are strongly recommended. Refer to the ANADIGICS application note on ESD precautions. Figure 13: PC Board Layout

Data Sheet - Rev 2.2 ARA05050 Figure 14: Solder Mask Outline

12 Data Sheet - Rev 2.2 ARA05050 Figure 15: S12 Package Outline - 28 Pin SSOP with Heat Slug PACKAGE OUTLINE

14 Data Sheet - Rev 2.2 ARA05050 NOTES

Data Sheet - Rev 2.2 ARA05050 NOTES

ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product in any such application without written consent is prohibited. IMPORTANT NOTICE ANADIGICS, Inc.

141 Mount Bethel Road

Warren, New Jersey 07059, U.S.A. Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com E-mail: Mktg@anadigics.com ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. Data Sheet - Rev 2.2 ARA05050

ORDERING INFORMATION

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