APW8824CTI-TRG

APW8824 ANPEC | Alldatasheet

Document overview

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Technical content

Features

• 1A Output Current
• Wide 2.7V~5.5V Input Voltage
• Fixed 1.5MHz Switching Frequency
• Low Dropout Operating at 100% duty cycle
• Low 25mA Quiescent Current
• Integrate Synchronous Rectifier
• 0.6V Low Reference Voltage
• <0.5mA Input Current during Shutdown
• Current-Mode Operation with Internal Compen- sation - Stable with Ceramic Output Capacitors - Fast Line Transient Response
• Over-Voltage Protection
• Under Voltage Protection
• Over-Temperature Protection with Hysteresis
• Available in a TSOT-23-6A Package
• Halogen and Lead Free Available (RoHS Compliant)

Applications

• HD STB
• BT Mouse
• PND Instrument
• Portable Instrument Simplified Application Circuit VIN GND EN1 FB 6 APW8824 LX 3VIN 2.7~5.5V VOUT 0.6V~VIN 0~1A 2.2µH (option) 10µF (MLCC ) 10µF (MLCC ) IIN R1 < 1.5MΩ is recommended R2 < 200KΩ is recommended PG 100k

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw2 Ordering and Marking Information Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration Symbol Parameter Rating Unit VIN Input Bias Supply Voltage (VIN to GND) -0.3 ~ 7 V EN, FB, LX and PG to GND Voltage -0.3 ~ VIN+0.3 V <30ns pulse width -3 ~ 8 VLX LX Voltage (LX to GND) >30ns pulse width -0.3 ~ VIN +0.3 V Maximum Junction Temperature 150 oC TSTG Storage Temperature -65 ~ 150 oC TSDR Maximum Lead Soldering Temperature (10 Seconds) 260 oC Absolute Maximum Ratings (Note 1) Note 1: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. APW 8824 Handling Code Temperature Range Package Code Assembly Material APW 8824 CT: X - Date Code Package Code CT : TSOT -23-6A Operating Ambient Temperature Range I : -40 to 85oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device W 24X

4 VIN

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw3 Symbol Parameter Typical Value Unit θ JA Junction-to-Ambient Resistance in free air (Note 2) 220 oC/W Note 2: θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. Thermal Characteristics Recommended Operating Conditions (Note 3) Symbol Parameter Range Unit VIN Input Bias Supply Voltage (VIN to GND) 2.7 ~ 5.5 V VOUT Converter Output Voltage 0.6 ~ VIN V IOUT Converter Output Current 0 ~ 1 A L1 Converter Output Inductor 1.0 ~ 10 µH CIN Converter Input Capacitor 10 ~ 100 µF COUT Converter Output Capacitor 10 ~ 100 µF TA Ambient Temperature -40 ~ 85 oC TJ Junction Temperature -40 ~ 125 oC Note 3: Refer to the application circuit for further information

Electrical Characteristics

Symbol Parameter Test Conditions Min Typ Max Unit SUPPLY VOLTAGE AND CURRENT VIN Input Voltage Range 2.7 - 5.5 V IDD Quiescent Current VFB = 0.66V - 25 40 µA ISD Shutdown Input Current EN = GND - - 0.5 µA POWER-ON-RESET (POR) and LOCKOUT VOLTAGE THRESHOLDS UVLO Threshold 2.1 2.35 2.6 V UVLO Hysteresis - 0.1 - V REFERENCE VOLTAGE TA = 25 oC 0.594 0.6 0.606 V VREF Reference Voltage TA = -40~85 oC, TJ = -40~125 oC 0.591 - 0.609 V Output Voltage Accuracy 0A < IOUT < 1A, VIN > 3.6V, TJ =25 oC -1.5 - +1.5 % IFB FB Input Current -50 - 50 nA INTERNAL POWER MOSFETS FSW Switching Frequency VFB = 0.6V 1.2 1.5 1.8 MHz RP-FET Main Switch ON Resistance ILX=200mA - 0.28 0.35 Ω RN-FET Synchronous Switch ON Resistance ILX=200mA - 0.25 0.32 Ω N-FET Switch Leakage Current VRUN = GND, VLX = 5V -0.1 - 0.1 µA P-FET Switch Leakage Current VRUN = GND, VLX = 0V -0.1 - 0.1 µA Unless otherwise specified, these specifications apply over V IN=3.6V and TA= -40 ~ 85 oC. Typical values are at TA=25oC.

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw4 Note 4: Guaranteed by design, not production tested. Symbol Parameter Test Conditions Min Typ Max Unit INTERNAL POWER MOSFETS Dead-time (Note 4) - 5 - ns Duty Cycle 0 - 100 % PROTECTION ILIM Maximum Inductor Current Limit IP-FET, 2.7V≦VIN≦6V 2 2.5 3 A N-FET Negative Current Limit - 1 - A VOVP Over Voltage Protection Threshold 115 120 125 %VREF OVP Debounce Time - 20 - µs VUVP Under Voltage Protection Threshold 57 66 75 %VREF UVP Debounce Time - 15 - µs PG in from Lower (PG Goes High) 87 90 93 %VREF PG Low Hysteresis (PG Goes Low) - 3 - %VREF PG in from Higher (PG Goes High) 115 120 125 %VREF PG Threshold PG High Hysteresis (PG Goes Low) - 3 - %VREF PG High to Low debounce time (VOUT under shoot) - 60 - µs PG High to Low debounce time (VOUT over shoot) - 80 - µs TOTP Over-Temperature Protection TJ Rising - 150 - °C START-UP AND SHUTDOWN TSS Soft-start Duration (Note 4) - 0.7 - ms EN Input High Threshold VIN = 2.7V~5.5V - - 1.5 V EN Input Low Threshold VIN = 2.7V~5.5V 0.4 - - V EN Leakage Current VEN = 5V, VIN = 5V -1 - 1 µA Power Good Pull Low Resistance - 200 - Ω Unless otherwise specified, these specifications apply over V IN=3.6V and TA= -40 ~ 85 oC. Typical values are at TA=25oC.

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw5 Typical Operating Characteristics Output Voltage(V) Output Voltage vs. Temperature 1.475 1.485 1.495 1.505 1.515 1.525 Temperature(oC) -40 -20 0 20 40 60 80 100 120 140 160 Vout= 1.5V Switching Frequency vs Temperature Switching Frequency(MHz) Temperature(oC) -40 -20 0 20 40 60 80 100 120 140 1601.3 1.35 1.4 1.45 1.5 1.55 1.6 Efficiency (%) Output Current (A) VIN=3.3V VIN=4.2V VIN=5V 0 0.2 0.4 0.6 0.8 1 Efficiency vs. Load Current FSW=1.5MHz, VOUT=1.8V Efficiency vs. Load Current Efficiency (%) Output Current (A) VIN=3.3V VIN=4.2V VIN=5V 0 0.2 0.4 0.6 0.8 1 FSW=1.5MHz, VOUT=1.2V

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw6 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified. Enable CH1:VEN , 5V/Div CH2:VOUT , 1V/Div CH3:VPG , 5V/Div TIME : 1ms/Div VEN IL CH3:IL , 1A /Div VPG VOUT Shutdown VEN IL CH1: VEN, 5V/Div CH2: VOUT , 1V/Div CH3: VPG 5V/Div TIME : 20µs/Div CH4: IL, 1A /Div VOUT VPG Output Ripple IL VOUT CH1: VOUT , 20mV/Div,AC CH2: VLX , 5V/Div TIME : 20µs/Div CH3: IL , 1A /Div VLX Load Transient IOUT VOUT CH1: VOUT , 100mV/Div,AC CH2: VLX,5V/Div TIME : 100µs/Div CH3: IOUT ,1A /Div VLX

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw7 Operating Waveforms (Cont.) Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified. CH1: VOUT , 1V/Div CH 2: VLX, 5V/Div TIME : 20µs/Div Short Circuit Protection CH3: IL, 2A /Div VOUT VLX IL

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw8 Pin Description PIN NO. NAME Function 1 EN Enable Control Input. Forcing this pin above 1.5V enables the device. Forcing this pin below 0.4V shuts it down. In shutdown, all functions are disabled to decrease the supply current below 0.5µA. Do not leave EN pin floating. 2 GND Power and Signal Ground. 3 LX Switch Node Connected to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFETs switches. 4 VIN Device and Converter Supply Pin. Must be closely decoupled to GND with a 10µF or greater ceramic capacitor. 5 PG Power Good Output. This pin is open-drain logic output that is pulled to ground when the output voltage is not within 10%of regulation point. 6 FB Feedback Input Pin. The buck regulator senses feedback voltage via FB and regulates the FB voltage at 0.6V. Connecting FB with a resistor-divider from the output sets the output voltage of the buck converter. Block Diagram Oscillator Logic Control LX Over- Temperature Protection VREF 0.6V GMCOMP ICMP Soft- start Error Amplifier Zero- Crossing Comparator Current Limit Slope Compensatio n VIN Current Sense Amplifier Shutdown Control FB EN GND Gate Driver OVP UVP FB FB FB 120%VREF 66%VREF 90%VREF 120%VREF FB PG

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw9 Typical Application Circuits VIN GND EN1 FB 6 APW8824 LX 3VIN 2.7~5.5V VOUT 0.6V~VIN 0~1A 2.2µH (option) 10µF (MLCC ) 10µF (MLCC ) IIN R1 < 1.5MΩ is recommended R2 < 200KΩ is recommended C1 closed to IC . Less tan 2mm is recommended PG 100k

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw10 Function Description Main Control Loop The APW8824 is a constant frequency, synchronous rec- tifier and current-mode switching regulator. In normal operation, the internal P-channel power MOSFET is turned on each cycle. The peak inductor current which ICMP turn off the P-FET is controlled by the voltage on the COMP node, which is the output of the error amplifier (EAMP). An external resistive divider connected between VOUT and ground allows the EAMP to receive an output feedback voltage VFB at FB pin. When the load current increases, it causes a slightly decrease in VFB relative to the 0.6V reference, which in turn causes the COMP voltage to in- crease until the average inductor current matches the new load current. Under-Voltage Lockout An under-voltage lockout function prevents the device from operating if the input voltage on VIN is lower than approxi- mately 2.35V. The device automatically enters the shut- down mode if the voltage on VIN drops below approxi- mately 2.35V. This under-voltage lockout function is imple- mented in order to prevent the malfunctioning of the converter. Soft-start The APW8824 has a built-in soft-start to control the output voltage rise during start-up. During soft-start, an internal ramp voltage, connected to the one of the positive inputs of the error amplifier, raises up to replace the reference voltage (0.6V typical) until the ramp voltage reaches the reference voltage. Then the voltage on FB regulated at reference voltage. Enable/Shutdown Driving EN to ground places the APW8824 in shutdown mode. When in shutdown, the internal power MOSFETs turn off, all internal circuitry shuts down and the quiescent supply current reduces to 0.5µA maximum. Pulse Frequency Modulation Mode (PFM) The APW8824 is a fixed frequency PWM peak current mode control step-down converter. At light loads, the APW8824 will automatically enter in pulse frequency mode operation to reduce the dominant switching losses. In PFM operation, the inductor current may reach zero or reverse on each pulse. A zero current comparator turn off the N-FET, forcing DCM operation at light load. These controls get very low quiescent current, help to maintain high efficiency over the complete load range. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant fre- quency architectures by preventing sub-harmonic oscil- lations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current sig- nal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the APW8824 uses a special scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. Dropout Operation As the input supply voltage decreases to a value approach- ing the output voltage, the duty cycle increases toward the maximum on time. Further reduction of the supply volt- age forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will be determined by the input voltage minus the voltage drop across the P-FET and the inductor. An important detail to remember is that on resistance of P-FET switch will increase at low input supply voltage. Therefore, the user should calculate the power dissipa- tion when the APW8824 is used at 100% duty cycle with low input voltage.

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw11 Function Description Over-Temperature Protection (OTP) The over-temperature circuit limits the junction tempera- ture of the APW8824. When the junction temperature ex- ceeds 150oC, a thermal sensor turns off the both power MOSFETs. It is a latch protection. Over Voltage Protection The over-voltage function monitors the output voltage by FB pin. When the FB voltage increases over 120% of the reference voltage due to the high-side MOSFET failure or for other reasons, the over-voltage protection comparator will turn on low side N-MOSFET and shutdown the con- verter output. Output Under Voltage Protection In the operational process, if a short circuit occurs, the output voltage will drop quickly. Before the current-limit circuit responds, the output voltage will fall out of the re- quired regulation range. The under-voltage continually monitors the FB voltage after soft-start is completed. If a load step is strong enough to pull the output voltage lower than the under-voltage threshold. The under-voltage threshold is 66% of the nominal out- put voltage. The under-voltage comparator has a built-in 15µs noise filter to prevent the chips from wrong UVP shutdown being caused by noise. APW8824 will be latched after under-voltage protection. Power Good PG is actively held low in shutdown and soft-start status. In the soft-start process, the PG is an open-drain. When the soft-start is finished, the PG is released. In normal operation, the PG window is from 90% to 120% of the converter reference voltage. When the output voltage has to stay within this window, PG signal will become high. When the output voltage outruns 90% or 120% of the target voltage, PG signal will be pulled low immediately.

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw12

Application Information

To avoid saturation of the inductor, the inductor should be rated at least for the maximum output current of the con- verter plus the inductor ripple current. IL(MAX) = IOUT(MAX) + 1/2 x Δ IL Output Capacitor Selection When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage char- acteristics of all the ceramics for a given value and size. LSW IN OUT OUT IF V V1V L Δ⋅  − Because buck converters have a pulsating input current, a low ESR input capacitor is required. This results in the best input voltage filtering, minimizing the interference with other circuits caused by high input voltage spikes. Also, the input capacitor must be sufficiently large to sta- bilize the input voltage during heavy load transients. For good input voltage filtering, usually a 10µF input capacitor is sufficient. It can be increased without any limit for better input-voltage filtering. Ceramic capacitors show better performance because of the low ESR value, and they are less sensitive against voltage transients and spikes com- pared to tantalum capacitors. Place the input capacitor as close as possible to the input and GND pin of the device for better performance. The current-mode control scheme of the APW8824 al- lows the use of tiny ceramic capacitors. The higher ca- pacitor value provides the good load transients response. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. If required, tantalum capacitors may be used as well. The output ripple is the sum of the voltages across the ESR and the ideal output capacitor. Inductor Selection For high efficiencies, the inductor should have a low dc resistance to minimize conduction losses. Especially at high-switching frequencies the core material has a higher impact on efficiency. When using small chip inductors, the efficiency is reduced mainly due to higher inductor core losses. This needs to be considered when select- ing the appropriate inductor. The inductor value deter- mines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the lower the conduction losses of the converter. Conversely, larger inductor values cause a slower load transient response. A reasonable starting point for setting ripple current, Δ IL, is 40% of maximum output current. The recommended inductor value can be calculated as below: Output Voltage Setting The output voltage is set by a resistive divider. The exter- nal resistive divider is connected to the output, allowing remote voltage sensing as shown in “Typical Application Circuits”. A suggestion of maximum value of R2 is 200kΩ to keep the minimum current that provides enough noise rejection ability through the resistor divider. The output voltage can be calculated as below:  +⋅=  +⋅= 2R 1R16.02R 1R1VV REFOUT R2 ≤ 200KΩAPW8824 FB GND VOUT R1≤ 1.5MΩ ⋅⋅+⋅⋅  −⋅ OUTSWSW IN OUT OUT OUT CF8 1ESRLF V V1V V

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw13 Application Information (Cont.) Thermal Considerations In most applications the APW8824 does not dissipate much heat due to its high efficiency. But, in applications where the APW8824 is running at high ambient tempera- ture with low supply voltage and high duty cycles, the heat dissipated may exceed the maximum junction tempera- ture of the part. If the junction temperature reaches ap- proximately 150oC, both power switches will be turned off and the LX node will become high impedance. To avoid the APW8824 from exceeding the maximum junc- tion temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The power dissipated by the part is approximated: D))-(1 RD (R I P FET-NFET-P2OUTD ×+××≅ The temperature rise is given by: TR = (PD)(θ JA) Where PD is the power dissipated by the regulator, D is duty cycle of main switch D = VOUT/VIN The θ JA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TR Where TA is the ambient temperature. The maximum power dissipation on the device can be shown as follow figure: Junction Temperature(oC) Maximum Power Disspation(W) -50 -25 0 25 50 75 100 125 150 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 VIN VOUT IL N-FET LX IOUT CIN COUT IIN ILIM IL IPEAK IOUT IP-FET Δ IL ESR P-FET IP-FET

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw14 Layout Considerations For all switching power supplies, the layout is an impor- tant step in the design; especially at high peak currents and switching frequencies. If the layout is not carefully done, the regulator might show noise problems and duty cycle jitter. 1. The input capacitor should be placed close to the VIN and GND. Connecting the capacitor and VIN/GND with short and wide trace without any via holes for good input voltage filtering. The distance between VIN/GND to ca- pacitor less than 2mm respectively is recommended. 2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the LX pin to minimize the noise coupling into other circuits. 3. The output capacitor should be place closed to VOUT and GND. 4. Since the feedback pin and network is a high imped- ance circuit the feedback network should be routed away from the inductor. The feedback pin and feedback net- work should be shielded with a ground plane or trace to minimize noise coupling into this circuit. 5. A star ground connection or ground plane minimizes ground shifts and noise is recommended. Application Information (Cont.)

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw15

Package Information

c SEE VIEW A D e b E A A2A1 VIEW A L 0.25 SEATING PLANE GAUGE PLANE Note : 1. Followed from JEDEC TO-178 AB. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. 0.020 0.008 0.004 0.024 0.035 0.039 MAX. 0.30L 0 0o E e D c b 0.08 0.30 0.0120.60 8o 0o 8o

0.95 BSC

1.90 BSC

0.50 0.20

0.075 BSC

0.037 BSC

0.012 0.003 MILLIMETERS MIN. SYMBOL A 0.01 0.70 TSOT-23-6A MAX. 0.90 0.10 1.00 MIN. 0.000 0.028 INCHES 2.70 3.10 0.106 0.122 2.60 3.00 0.102 0.118 1.40 1.80 0.055 0.071 0.70 0.028

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw16 Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 TSOT-23-6A Carrier Tape & Reel Dimensions Devices Per Unit (mm) Package Type Unit Quantity TSOT-23-6A Tape & Reel 3000 H A d A AB W F T P0OD0 B SECTION B-B SECTION A-A OD1

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw17 Taping Direction Information TSOT-23-6A Classification Profile USER DIRECTION OF FEED AAAX AAAX AAAX AAAX AAAX AAAX AAAX

Copyright  ANPEC Electronics Corp. (Tsmax to TP) 3 °C/second max. 3°C/second max. Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. Time 25°C to peak temperature 6 minutes max. 8 minutes max.

• Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.

** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 2. Pb-free Process – Classification Temperatures (Tc) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

Copyright  ANPEC Electronics Corp. Rev. A.2 - May., 2013 APW8824 www.anpec.com.tw19 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838