APW8819 ANPEC | Alldatasheet

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Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw1 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. DDR TOTAL POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER WITH 1.5A LDO Features General Description Buck Controller (VDDQ)

  • High Input Voltages Range from 3V to 28V Input Power
  • Provide 1.8V (DDR2), 1.5V (DDR3) or Adjustable Output Voltage from 0.5V to 2V - ±1% Accuracy Over-Temperature
  • Build in VREF Voltage 1.8V ±1% Accuracy over Temperature
  • Integrated MOSFET Drivers
  • Integrated Bootstrap Forward P-CH MOSFET
  • Excellent Line and Load Transient Responses
  • PFM Mode for Increased Light Load Efficiency
  • Selectable 300kHz/400kHz/500kHz Switching Frequebcies
  • Integrated MOSFET Drivers and Bootstrap Diode
  • S3 and S5 Pins Control The Device in S0, S3, or S4/S5 State
  • Power Good Monitoring
  • 50% Under-Voltage Protection (UVP)
  • 125% Over-Voltage Protection (OVP)
  • Adjustable Current-Limit Protection - Using Sense Low-Side MOSFET RDS(ON)
  • QFN-20 3mmx3mm Package (QFN-20) and QFN-16 3mmx3mm Thin Package (TQFN-16)
  • Lead Free Available (RoHS Compliant) +1.5A LDO Section (VTT)
  • Souring or Sinking Current up to 1.5A
  • Fast Transient Response for Output Voltage
  • Output Ceramic Capacitors Support at Least 10mF MLCC
  • VTT and VTTREF Track at Half the VDDQSNS by Internal Divider
  • ±20mV Accuracy for VTT and VTTREF
  • Independent Over-Current-Limit (OCL)
  • Thermal Shutdown Protection

Applications

  • DDR2, and DDR3 Memory Power Supplies
  • SSTL-2 SSTL-18 and HSTL Termination The APW8819 integrates a synchronous buck PWM con- troller to generate VDDQ, a sourcing and sinking LDO linear regulator to generate VTT. It provides a complete power supply for DDR2 and DDR3 memory system. It offers the lowest total solution cost in system where space is at a premium. The APW8819 provides excellent transient response and accurate DC voltage output in PFM Mode. In Pulse Fre- quency Mode (PFM), the APW8819 provides very high ef- ficiency over light to heavy loads with loading-modulated switching frequencies. The APW8819 is equipped with accurate current-limit, output under-voltage, and output over-voltage protections. A Power-On- Reset function monitors the voltage on VCC prevents wrong operation during power on. The LDO is designed to provide a regulated voltage with bi-directional output current for DDR-SDRAM termination. The device integrates two power transistors to source or sink current up to 1.5A. It also incorporates current-limit and thermal shutdown protection. An internal resistor divider is used to provide a half volt- age of VDDQSNS for VTTREF and VTT Voltage. The VTT output voltage is only requiring 20 µF of ceramic output capacitance for stability and fast transient response. The S3 and S5 pins provide the sleep state for VTT (S3 state) and suspend state (S4/S5 state) for device, when S5 and S3 are both pulled low the device provides the soft-off for VTT and VTTREF.The APW8819 is available in 3mmx3mm 20-pin QFN and 3mmx3mm 16-pin TQFN packages.

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw2 Simplified Application Circuit Ordering and Marking Information Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). VTT VDDQ VIN +3V~28V PWM LOUT DDR LDO ROC VDDQ/2 S3 S5 VREF REFIN MODE RMODE RTOP RGND APW8819 Handling Code Temperature Range Package Code Package Code QA : QFN-20 QB : TQFN-16 Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel TY : Tray Assembly Material G : Halogen and Lead Free Device APW8819 QA : Assembly Material XXXXX - Date Code APW8819 QB : XXXXX - Date Code APW XXXXX 8819 APW XXXXX 8819

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw3 Absolute Maximum Ratings (Note 1, 2) Symbol Parameter Rating Unit VCC VCC Supply Voltage (VCC to GND) -0.3 ~ 7 V VBOOT BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 7 V VBOOT-GND BOOT Supply Voltage (BOOT to GND) <20ns Pulse Width >20ns Pulse Width -5 ~ 42 -0.3 ~ 35 V UGATE Voltage (UGATE to PHASE) <20ns Pulse Width >20ns Pulse Width -5 ~ VBOOT+0.3 -0.3 ~ VBOOT+0.3 V LGATE Voltage (LGATE to GND) <20ns Pulse Width >20ns Pulse Width -5 ~ VCC+0.3 -0.3 ~ VCC+0.3 V PHASE Voltage (PHASE to GND) <20ns Pulse Width >20ns Pulse Width -5 ~ 35 -0.3 ~ 28 V PGND and VTTGND to GND Voltage -0.3 ~ 0.3 V All Other Pins ( OC, MODE, S3, S5, VDDQSNS, VTTSNS, VLDOIN, VREF, POK, VTT, VTTREF and REFIN to GND Voltage) -0.3 ~ 7 V TJ Maximum Junction Temperature 150 oC TSTG Storage Temperature -65 ~ 150 oC TSDR Ma ximum Soldering Temperature, 10 Seconds 260 oC Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note 2: The device is ESD sensitive. Handling precautions are recommended. Pin Configuration = Thermal Pad (connected to GND plane for better heat dissipation ) S3 17 MODE 19 OC 18 POK 20

15 BOOT

14 UGATEVLDOIN 2

13 PHASE

11 LGATE

10 PGND

9 VDDQSNS

7 GND

8 REFIN

6 VREF

12 VCC

12 BOOT

11 UGATEVLDOIN 2

10 PHASE

8 LGATE

6 REFIN

7 VDDQSNS

5 VREF

9 VCC

(Top View ) TQFN 3x3-16 (Top View ) GND

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw4 Thermal Characteristics (Note 3) Symbol Parameter Typical Value Unit θ JA Thermal Resistance - Junction to Ambient QFN3x3-20 TQFN3x3-16 °C/W Note 3: θ JA is measured with the component mounted on a high effective the thermal conductivity test board in free air. The exposed pad of package is soldered directly on the PCB. Symbol Parameter Range Unit VCC VCC Supply Voltage 4.5 ~ 5.5 V VIN Converter Input Voltage 3 ~ 28 V VVDDQ Converter Output Voltage 0.5 ~2V/ DDR2 (1.8V)/ DDR3 (1.5V) V VVTT LDO Output Voltage 0.25~ 1 V IOUT Converter Output Current 0 ~ 20 A IVTT LDO Output Current -1.5 ~ +1.5 A CVCC VCC Capacitance 1~ µF CVTT VTT Output Capacitance 10~ µF CVTTREF VTTREF Output Capacitance 0.22 ~ 2.2 µF TA Ambient Temperature -40 ~ 85 o C TJ Junction Temperature -40 ~ 125 oC Recommended Operating Conditions (Note 4)

Electrical Characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit SUPPLY CURRENT IVCC VCC Supply Current TA = 25oC, VS3 = VS5 = 5V, no load - 1.2 1.5 mA IVCCSTB VCC Standby Current TA = 25oC, VS3 = 0V, VS5 = 5V, no load - 740 850 µA IVCCSDN VCC Shutdown Current TA =25oC, VS3 = VS5 = 0V, no load - 0.1 1 µA ILDOIN LDOIN Supply Current TA = 25oC, VS3 = VS5 = 5V, no load 0.3 0.6 1 mA ILDOINSTB LDOIN Standby Current TA = 25oC, VS3 = 0V, VS5 = 5V, no load - 0.1 10 ILDOINSDN LDOIN Shutdown Current TA = 25oC, VS3 = VS5 = 0V, no load - 0.1 1 µA POWER-ON-RESET VCC POR Threshold VCC Rising 4.15 4.3 4.45 V VCC POR Hysteresis - 100 - mV VTT OUTPUT IVREF=30µA, TA=25oC - 1.8 - V VVREF VREF Output Voltage 0uA＜IVREF＜300uA, TA= -40oC~85oC 1.782 - 1.8144 V Refer to the typical application circuits. These specifications apply over VVCC=VBOOT=5V, VIN=12V and TA= -40 ~ 85 °C, unless otherwise specified. Typical values are at TA=25°C.

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw5 Electrical Characteristics (Cont.) APW8819 Symbol Parameter Test Conditions Min. Typ. Max. Unit VTT OUTPUT VLDOIN = VVDDQSNS = 1.8V - 0.9 - VVTT VTT Output Voltage VLDOIN = VVDDQSNS = 1.5V - 0.75 - V VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2 - VVTT, IVTT = 0A -20 - 20 VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2 - VVTT, IVTT = 1.5A -30 - 30 VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2 - VVTT, IVTT = 0A -20 - 20 VVTT VTT Output Tolerance VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2 - VVTT, IVTT = 1.5A -30 - 30 mV Sourcing Current (VLDOIN = 1.8V) 2 2.2 3 Sinking Current (VLDOIN = 1.8V) -2 -2.2 -3 A Sourcing Current (VLDOIN = 1.5V) 2 2.2 3 ILIM Current-Limit Sinking Current (VLDOIN = 1.5V) -2 -2.2 -3 A IVTTLK VTT Leakage Current VVTT = 1.25V, VS3 = 0V, VS5 = 5V, TA = 25oC -1.0 - 1.0 µA IVTTSNSLK VTTSNS Leakage Current VVTT = 1.25V, TA = 25oC -1.00 0.01 1.00 µA IVTTDIS VTT Discharge Current VVTT = 0.5V, VS3 = VS5 = 0V, TA = 25oC, VVREF = 0V - 7.8 - mA VTTREF OUTPUT VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2 - 0.9 - VVTTREF VTTREF Output Voltage VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2 - 0.75 - V -10mA < IVTTREF < 10mA, VVDDQSNS/2 - VVTTREF VLDOIN = VVTTREF =1.8V -18 - +18 VTTREF Tolerance -10mA < IVTTREF < 10mA, VVDDQSNS/2 - VVTTREF VLDOIN = VVDDQSNS = 1.5V -15 - +15 mV IVTTREF VTTREF Source Current VVTTREF = 0V -10 -25 -40 mA IVTTREF VTTREF Sink Current VVTTREF = VVDDQSNS 10 25 40 mA IVTTREFDIS VTTREF Discharge Current TA = 25oC , S3=S5=0V, VVTTREF = 0.5V - 2.6 - mA VDDQ OUTPUT VVDDQ VDDQ Output Voltage VREFIN = 1.8V - 1.8 - V VDDQSNS Regulation Voltage Tolerance to REFIN TA = 25oC, VREFIN = 1.8V, No Load -15 - 15 mV IVDDQSNS VDDQSNS Input Current VVDDQSNS=1.8V - 12 - µA IREFIN REFIN Input Current VREFIN=1.8V -0.1 - 0.1 µA VDDQ Discharge Current VS3 = VS5 = 0V, VVDDQSNS = 0.5V, MODE Pin Pulled Down to GND Through 47kΩ (Non-Tracking) - 12 - mA LDOIN Discharge Current VS3 = VS5 = 0V, VVDDQSNS = 0.5V, MODE Pin Pulled Down to GND Through 100kΩ (Tracking) - 1000 - mA Refer to the typical application circuits. These specifications apply over VVCC=VBOOT=5V, VIN=12V and TA= -40 ~ 85 °C, unless otherwise specified. Typical values are at TA=25°C.

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw6 Electrical Characteristics (Cont.) APW8819 Symbol Parameter Test Conditions Min. Typ. Max. Unit PWM CONTROLLERS VIN=12V, VVDDQSNS=1.8V, RMODE=100 kΩ 270 300 330 kHz FSW Operating Frequency VIN=12V, VVDDQSNS=1.8V, RMODE=200 kΩ 360 400 440 kHz TSS Internal Soft Start Time S5 is High to VOUT Regulation 0.9 1.2 1.5 ms TOFF (MIN) Minimum off Time 350 450 550 ns TON(MIN) Minimum on Time 80 110 140 ns Zero-Crossing Threshold -9.5 0.5 10.5 mV VDDQ PROTECTIONS TA = 25oC 9 10 11 µA OC Pin Source Current Temperature Coefficient, On The Basis of 25 ο C - 4500 - ppm/ oC OCP Comparator Offset (VOC – VPGND) – (VPGND – VPHASE), VOC – VPGND = 60mV -10 0 +10 mV VDDQ Current Limit Setting Range VOC-VPGND 0.2 - 3 V VDDQ OVP Trip Threshold VVDDQ Rising 120 125 130 % VDDQ OVP Debounce Delay VVDDQ Rising, DV=10mV - 2 - µs VDDQ UVP Trip Threshold VVDDQ Falling 40 50 60 % VDDQ UVP Trip Hysteresis - 3 - % VDDQ UVP Debounce - 16 - µs VDDQ UVP Enable Delay 2 2.4 2.8 ms POK POK in from Lower (POK Goes High) 87 90 93 % VPOK POK Threshold POK Out from Normal (POK Goes Low) 120 125 130 % IPOK POK Leakage Current VPOK=5V - 0.1 1.0 µA POK Sink Current VPOK=0.5V 2.5 7.5 - mA POK Enable Delay Time S5 High to POK High 2 2.4 2.8 ms POK Delay Time Delay for POK In - 63 - µs GATE DRIVERS UGATE Pull-Up Resistance BOOT-UGATE=0.5V - 1.5 3 Ω UGATE Sink Resistance UGATE-PHASE=0.5V - 0.7 1.8 Ω LGATE Pull-Up Resistance VCC-LGATE=0.5V - 1 2.2 Ω LGATE Sink Resistance LGATE-PGND=0.5V - 0.5 1.2 Ω UGATE to LGATE Dead time UGATE falling to LGATE rising, no load - 20 - ns LGATE to UGATE Dead time LGATE falling to UGATE rising, no load - 20 - ns Refer to the typical application circuits. These specifications apply over VVCC=VBOOT=5V, VIN=12V and TA= -40 ~ 85 °C, unless otherwise specified. Typical values are at TA=25°C.

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw7 Electrical Characteristics (Cont.) APW8819 Symbol Parameter Test Conditions Min. Typ. Max. Unit BOOTSTRAP SWITCH VF RON VVCC - VBOOT, IF = 10mA, TA = 25oC - 0.5 0.8 V IF Reverse Leakage VBOOT = 30V, VPHASE = 25V, VVCC = 5V, TA = 25oC - - 0.5 µA LOGIC THRESHOLD VIH S3, S5 High Threshold Voltage S3, S5 Rising 1.6 - - V VIL S3, S5 Low Threshold Voltage S3, S5 Falling - - 0.9 V IILEAK Logic Input Leakage Current VS3 = VS5 = 5V, TA =25oC -1 - 1 µA IMODE MODE Source Current 14 15 16 µA MODE = 0 - - 0.829 MODE = 1 0.879 - 1.202 MODE = 2 1.262 - 1.76 MODE = 3 1.84 - 1.95 VTHMODE MODE Threshold Voltage MODE = 4 VCC-1 - - V THERMAL SHUTDOWN TSD Thermal Shutdown Temperature TJ Rising - 160 - oC Thermal Shutdown Hysteresis - 25 - oC Refer to the typical application circuits. These specifications apply over VVCC=VBOOT=5V, VIN=12V and TA= -40 ~ 85 °C, unless otherwise specified. Typical values are at TA=25°C.

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw8 Typical Operating Characteristics Junction Temperature, TJ (oC) VREFIN=1.5V, VDDQ=1.5V VDDQ Output Voltage (V) 1.48 1.52 1.51 1.49 1.50 -40 -20 0 20 40 60 80 100 120 Junction Temperature, TJ (°C) VDDQ Output Voltage (V) VREFIN=1.8V, VDDQ=1.8V 1.77 1.83 1.81 1.78 1.79 -40 -20 0 20 40 60 80 100 120 1.8 1.82 Frequency vs. Junction Temperature Switching Frequency,FSW (KHz) Junction Temperature, TJ (°C) 270 280 290 300 310 320 330 -40 -20 0 20 40 60 80 100 120 Frequency Setting : 300kHz Supply Current in S0 State vs. Junction Temperature Junction Temperature, TJ (°C) Supply Current, IVCC (mA) 1.6 1.2 0.4 0.8 2.0 -40 -20 0 20 40 60 80 100 120 S3=S5=5V Shutdown Current, IVCC (uA) Shutdown Current vs. Junction Temperature 1.0 0.8 0.6 0.2 0.4 Junction Temperature, TJ (°C) -40 -20 0 20 40 60 80 100 120 Supply Current in S3 State vs. Junction Temperature Supply Current, IVCC (mA) Junction Temperature, TJ (°C) 0.2 0.4 0.6 -40 -20 0 20 40 60 80 100 120 0.8 1.0 S3=0V, S5=5V

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw9 Typical Operating Characteristics Junction Temperature, TJ (°C) -40 -20 0 20 40 60 80 100 120 MODE Source Current (uA) MODE Source Current vs. Junction Temperature OC Pin Sink Current vs. Junction Temperature OC Sink Current (uA) Junction Temperature, TJ (°C) -40 -20 0 20 40 60 80 100 120

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw10 Operating Waveforms CH1: VS5 (5V/div) CH2: VVDDQ(1V/div) CH3: VVTT (500mV/div) CH4: VPOK (5V/div) Time: 500µs/div S5 Enable, No Load CH1: VS5 (5V/div) CH2: VVDDQ (1V/div) CH3: VUGATE (20V/div) CH4: VPOK (5V/div) Time: 500µs/div Non-Zero VDDQ S5 Enable S5 Shutdown- Tracking Discharge CH1: VS5 (5V/div) CH2: VVDDQ (1V/div) CH3: VVTT (500mV/div) CH4: VVTTREF (500mV/div) Time: 200µs/div S5 Shutdown- Non-Tracking Discharge CH1: VS5 (5V/div) CH2: VVDDQ (1V/div) CH3: VVTT (500mV/div) CH4: VVTTREF (500mV/div) Time: 5ms/div

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw11 Operating Waveforms S3 Enable-Shutdown CH1: VS3 (5V/div) CH2: VVDDQ (1V/div) CH3: VVTTREF (500mV/div) CH4: VVTT (500mV/div) Time: 10ms/div Load Transient, IVDDQ= 0A->12A->0A CH1: VVDDQ (100mV/div) CH2: VUGATE (20V/div) CH3: VLGATE (5V/div) CH4: IL (10A/div) Time: 20µs/div CH1: VVDDQ (100mV/div) CH2: VUGATE (20V/div) CH3: VLGATE (5V/div) CH4: IL (10A/div) Time: 20µs/div Load Transient, IVDDQ = 5A->17A->5A Current Limit then Occur UVP CH1: VVDDQ (1V/div) CH2: VVTT (500mV/div) CH3: VPHASE (20V/div) CH4: IL (10A/div) Time: 100µs/div

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw12 Operating Waveforms CH1: VVDDQ (1V/div) CH2: VVTT (500mV/div) CH3: VPHASE (20V/div) CH4: IL (10A/div) Time: 20µs/div Short Circuit Test : VDDQ Short to GND

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw13 Pin Description NO. QFN-20 TQFN-16 NAME FUNCTION 1 - VTTSNS Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output capacitor. 2 2 VLDOIN Supply voltage input for the VTT LDO. 3 3 VTT Power output for the VTT LDO. 4 - VTTGND Power ground output for the VTT LDO. 5 4 VTTREF VTTREF buffered reference output. 6 5 VREF 1.8V Reference Output. A recommended capacitor with a value of 0.1uF should be attached to the VREF terminal.

7 Thermal

Pad GND Signal ground for the PWM controller and VTT LDO. Connect to minus terminal of the VTT LDO output capacitor. 8 6 REFIN Reference input for VDDQ. Programmed by the resistor-divider connected between VREF and GND. 9 7 VDDQSNS VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge current sinking terminal for VDDQ non-tracking discharge. Output voltage feedback input for VDDQ output if VDDQSET pin is connected to VCC or GND. 10 - PGND Power ground of the LGATE low-side MOSFET driver. Connect the pin to the Source of the low-side MOSFET. Also it is current sense comparator positive input terminal and the ground of power good circuit. 11 8 LGATE Output of the low-side MOSFET driver for PWM. Connect this pin to Gate of the low-side MOSFET. Swings from PGND to VCC. 12 9 VCC Filtered 5V power supply input for internal control circuitry. 13 10 PHASE Junction point of the high-side MOSFET Source, output filter inductor and the low-side MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE serves as the lower supply rail for the UGATE high-side gate driver. 14 11 UGATE Output of the high-side MOSFET driver for PWM. Connect this pin to Gate of the high-side MOSFET. 15 12 BOOT Supply Input for the UGATE Gate Driver and an internal level-shift circuit. Connect to an external capacitor and diode to create a boosted voltage suitable to drive a logic-level N-channel MOSFET. 16 13 S5 S5 signal input. 17 14 S3 S3 signal input. 18 15 OC Over-current trip voltage setting input for RDS(ON) current sense scheme. Connect resistor to GND to set over-current threshold at VOC/8. 19 16 MODE Discharge mode and switching frequency setting pin. 20 1 POK Power-okay output pin. POK is an open drain output used to Indicate the status of the output voltage. When VDDQ output voltage is within the target range, it is in high state.

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw14 Block Diagram BOOT UGATE PHASE LGATE PGND PWM Signal Controller 50% x REFIN 125% x REFIN OV UV OC ZC PHASE TON Generator VDDQSNS VTT VTTREF VLDOIN VTTSNS REFIN REFIN x 90% REFIN x 125% Delay POR Error Comparator VCC 10uA MODE Discharge Mode Selection Current Limit S3,S5 Control Logic Thermal Shutdown Soft Start Current Limit 0.5 x VDDQ +5/10% 0.5 x VDDQ -5/10% VTTGND POK GND 0.5 x VDDQ Reference 1.8VVREF VCC 15uA

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw15 Typical Application Circuit DDR3, 400kHz Application Circuit VTTSNS VTTREF OC POK MODE LGATE VCC PHASE UGATE BOOTPGND VDDQSNS GND VREF VLDOIN VTT VTTGND REFIN APW 8819 QFN-20 VDDQ 1.5V/20A COUT LOUT CIN VIN 7V~25V 1µH 330uF(6mΩ )x 2 10uF x 2 (MLCC) CBOOT 0.1uF CVCC 1uF RVCC 2.2 100 K 10K, 1% RGND 49K, 1% CVREF 0.1uF 0.01uF CVTTREF 0.1 uF RPOK 100K 47K VTTREF VDDQ/2 CVTT 10uF (MLCC) VTT CVLDOIN 10uF (MLCC) VLDOIN APM4354 APM4354 RMODE ROC CREFIN RTOP

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw16 Function Description The APW8819 integrates a synchronous buck PWM con- troller to generate VDDQ, a sourcing and sinking LDO linear regulator to generate VTT. It provides a complete power supply for DDR2 and DDR3 memory system in 20-pin QFN and 16-pin TQFN packages. User defined output voltage is also possible and can be adjustable from 0.5V to 2V. Input voltage range of the PWM converter is 3V to 28V. The converter runs an adaptive on-time PWM operation at high-load condition and automatically re- duces frequency to keep excellent efficiency down to sev- eral mA. The VTT LDO can source and sink up to 1.5A peak cur- rent with only 10 µF ceramic output capacitor. VTTREF tracks VDDQ/2 within 1% of VDDQ. VTT output tracks VTTREF within 20 mV at no load condition while 40 mV at full load. The LDO input can be separated from VDDQ and optionally connected to a lower voltage by using VLDOIN pin. This helps reducing power dissipation in sourcing phase. The APW8819 is fully compatible to JEDEC DDR2/DDR3 specifications at S3/S5 sleep state (see Table 1). When both VTT and VDDQ are disabled, the part has two options of output discharge function. The tracking discharge mode discharges VDDQ and VTT outputs through the internal LDO transistors and then VTT output tracks half of VDDQ voltage during discharge. The non-tracking discharge mode discharges outputs using internal discharge MOSFETs that are connected to VDDQSNS and VTT. The current capability of these dis- charge MOSFETs are limited and discharge occurs more slowly than the tracking discharge. Selecting non-dis- charge mode can disable these discharge functions. Constant-On-Time PWM Controller with Input Feed-For- ward Power-On-Reset A Power-On-Reset (POR) function is designed to prevent wrong logic controls when the VCC voltage is low. The POR function continually monitors the bias supply volt- age on the VCC pin if at least one of the enable pins is set high. When the rising VCC voltage reaches the rising POR voltage threshold (4.3V typical), the POR signal goes high and the chip initiates soft-start operations. There is almost no hysteresis to POR voltage threshold (about 100mV typical). When VCC voltage drop lower than 4.2V (typical), the POR disables the chip. Soft-Start The APW8819 integrates digital soft-start circuits to ramp up the output voltage of the converter to the programmed regulation set point at a predictable slew rate. The slew rate of output voltage is internally controlled to limit the inrush current through the output capacitors during soft- start process. The figure 1 shows VDDQ soft-start sequence. When the S5 pin is pulled above the rising S5 threshold voltage, the switch regulator wait for 400µs and Mode status is read in this period. And then, the device initiates a soft-start process to ramp up the output voltage. The total soft-start interval is 1.2ms (typical) from S5 goes high to VDDQ ramps up to regulation and independent of the UGATE switching frequency. The constant on-time control architecture is a pseudo- fixed frequency with input voltage feed-forward. This ar- chitecture relies on the output filter capacitor’s effective series resistance (ESR) to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. In PFM operation, the high-side switch on-time controlled by the on-time generator is determined solely by a one- shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. In PWM operation, the high-side switch on-time is deter- mined by a switching frequency control circuit in the on- time generator block. The switching frequency control circuit senses the switching frequency of the high-side switch and keeps regulating it at a constant frequency in PWM mode. The design improves the frequency varia- tion and be more outstanding than a conventional con- stant on-time controller which has large switching fre- quency variation over input voltage, output current and temperature. Both in PFM and PWM, the on-time generator, which senses input voltage on PHASE pin, provides very fast on-time response to input line transients. Another one-shot sets a minimum off-time (typical: 450ns). The on-time one-shot is triggered if the error com- parator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time one- shot has timed out.

Copyright  ANPEC Electronics Corp. internal digital soft start voltage equal the VVDDQ voltage. does not indicate VTT power good externally. Figure 1. Soft-Start Sequence held low in shutdown, and standby. voltage), the internal UVP delay counter begins counting. bring the chip back to operation. tively pulls down the output voltage. pulled low. After 63µs debounce time, the POK goes high. get voltage, POK signal will be pulled low immediately.

Copyright  ANPEC Electronics Corp. sense resistance, inductor value, and input voltage. Where ROC is the resistor of current-limit setting threshold. RDS(ON) is the low side MOSFETs conducive resistance. rent-limit method is effective in almost every circumstance. Figure 2. Current-Limit Algorithm tions including fast load transient.

Copyright  ANPEC Electronics Corp. Table1: The Truth Table of S3 and S5 Pins. switching frequency and discharge mode configuration. Table 2. MODE Selection.

4 Open 500 Tracking

these MOSFETs is limited to discharge slowly. APW8819 does not discharge output charge at all. tending life time of the device.

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw20

Application Information

The Output VDDQSNS Voltage is defined by REFIN voltage. The APW8819 provides a 1.8V voltage reference from VREF. In normal application circuit, the VREF output voltage drive the REFIN input voltage through a voltage divider circuit. The VDDQ output range is between 0.75 V and 1.8V, programmed by the resister-divider connected between VREF and GND. For stability operation, connect- ing a few nano farads of capacitance from REFIN to GND is necessary. Where FSW is the switching frequency of the regulator. Although increase the inductor value and frequency reduce the ripple current and voltage, there is a tradeoff between the inductor’s ripple current and the regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (FSW) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the Output Inductor Selection The duty cycle of a buck converter is the function of the input voltage and output voltage. Once an output voltage is fixed, it can be written as: IN OUT V VD = IN OUT SW OUTIN RIPPLE V V LF V- VI ××= Output Capacitor Selection Output voltage ripple and the transient voltage deviation are factors that have to be taken into consideration when selecting an output capacitor. Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is in- tended for switching regulator applications. In addition to high frequency noise related MOSFET turn-on and turn- off, the output voltage ripple includes the capacitance volt- age drop and ESR voltage drop caused by the AC peak- to-peak current. These two voltages can be represented by: The inductor value determines the inductor ripple current and affects the load transient reponse. Higher inductor value reduces the inductor’s ripple current and induces lower output ripple voltage. The ripple current and ripple voltage can be approxminated by: ESRRIPPLEESR SWOUT RIPPLE OUTC RIV F8C IV ×=Δ These two components constitute a large portion of the total output voltage ripple . In some applications, multiple capacitors have to be paralleled to achieve the desired ESR value. If the output of the converter has to support another load with high pulsating current, more capaci- tors are needed in order to reduce th e equivalent ESR and s uppress the voltage ripple to a tolerable level. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors must also be considered. To support a load transient that is faster than the switching frequency, more capacitors have to be used to reduce the voltage excursion during load step change. Another aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the rated RMS current specified on the ca- pacitors to prevent the capacitor from over-heating. In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This will be result in a larger output ripple voltage. power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, selecting an inductor is capable of carrying the required peak cur- rent without going into saturation.

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw21 Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2, where IOUT is the load current. During power up, the input capaci- tors have to handle large amount of surge current. In low- duty notebook appliactions, ceramic capacitors are remmended. The capacitors must be connected between the drain of high-side MOSFET and the source of low- side MOSFET with very low-impeadance PCB layout. Application Information (Cont.) MOSFET Selection The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs should be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET: For the low-side MOSFET, before it is turned on, the body diode has been conducted. The low-side MOSFET driver will not charge the miller capacitor of this MOSFET. In the turning off process of the low-side MOSFET, the load current will shift to the body diode first. The high dv/dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driver sinking current path. This results in much less switching loss of the low-side MOSFETs. The duty cycle is often very small in high battery voltage applications, and the low-side MOSFET will con- duct most of the switching cycle; therefore, the RDS(ON) of the low-side MOSFET, the less the power loss. The gate charge for this MOSFET is usually a secondary consideration. The high-side MOSFET does not have this zero voltage switching condition, and because it conducts for less time compared to the low-side MOSFET, the switching loss tends to be dominant. Priority should be given to the MOSFETs with less gate charge, so that both the gate driver loss and switching loss will be minimized. The selection of the N-channel power MOSFETs are de- termined by the RDS(ON), reversing transfer capacitance (CRSS) and maximum output current requirement. The losses in the MOSFETs have two components: conduc- tion loss and transition loss. For the high-side and low- side MOSFETs, the losses are approximately given by the following equations : Phigh-side = IOUT 2 (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW Plow-side = IOUT 2 (1+ TC)(RDS(ON))(1-D) Where IOUT is the load current TC is the temperature dependency of R DS(ON) FSW is the switching frequency tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction losses while the high-side MOSFET include s an additional transi - tion loss. T he switching internal, t SW , is the function of the reverse transfer capacitance CRSS. The (1+TC) term is to factor in the temperature dependency of the R DS(ON) and can be extracted from the “R DS(ON) vs Temperature” curve of the power MOSFET.. Layout Consideration In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at higher frequency, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is freewheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed circuit traces should minimize interconnect- ing impedances and the magnitude of voltage spike. And signal and power grounds are to be kept separating and finally combined to use the ground plane construction or single point grounding. The best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not recommended. Below is a checklist for your layout:

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw22 Layout Consideration (Cont.) Application Information (Cont.) Keep the switching nodes (UGATE, LGATE, BOOT, and PHASE) away from sensitive small signal nodes (VREF, REFIN, VTTREF, OC, and MODE) since these nodes are fast mov ing signals. Therefore, keep traces to these nodes as short as possible and there should be no other weak signal traces in parallel with theses traces on any layer. The signals going through theses traces have both high dv/dt and high di/dt, with high peak charging and discharging current. The traces from the gate drivers to the MOSFETs (UGATE and LGATE) should be short and wide. Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Mini- mizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. Decoupling capacitor, the resistor dividers, boot capacitors, and current limit stetting resistor should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placednear the drain). And need to noted, con- necting capacitor with OC pin is forbidden. The input capacitor should be near the drain of the up per MOSFET; the high quality ceramic decoupling ca- pacitor can be put close to the VCC and GND pins; the VTTREF decoupling capacitor should be close to the VTTREF pin and GND; A capacitor with a value of 0.1µF or larger should be close to the VREF terminal; the REFIN decoupling capacitor should be close to the REFIN pin and GND; the VDDQ and VTT output capaci- tors should be located right across their output pin as clase as possible to the part to minimize parasitics. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND. The drain of the MOSFETs (PHASE node) should be a large plane for heat sinking. And PHASE pin traces are also the return path for UGATE. Connect this pin to the converter’s upper MOSFET source.

  • The PGND trace should be a separate trace, and inde pendently go to the source of the low-side MOSFETs for current limit accuracy. TQFN3X3-16 0.4mm 0.2mm 0.5mm 3mm * Just Recommend 0.5mm * 3mm 1.66 mm 1.66 mm 0.17 mm QFN3x3-20 0.5mm 0.24mm 0.508mm 0.162mm1.66mm 3mm * Just Recommend 3mm 1.66mm 0.5mm * Figure3. Recommended Minimum Footprint

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw23

Package Information

e SYMBOL MIN. MAX. 1.00 0.00 0.15 0.25 1.50 1.80 0.05 1.50 A b D E e L MILLIMETERS A3 0.20 REF QFN3x3-20 0.30 0.50 1.80

0.008 REF

MIN. MAX. INCHES 0.039 0.000 0.006 0.010 0.059 0.071 0.059 0.012 0.020 0.80 0.071 0.031 0.002 0.40 BSC 0.016 BSC K 0.20 0.008 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122 Note : 1. Followed from JEDEC MO-220 WEEE D Pin 1 E A b NX aaa c aaa 0.08 0.003

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw24 D E Pin 1 A b e Pin 1 Corner KL Note : Follow JEDEC MO-220 WEED-4. S Y M B O L MIN. MAX. 0.80 0.00 0.18 0.30 1.50 1.80 0.05 1.50 A b D E e L MILLIMETERS A3 0.20 REF TQFN3x3-16 0.30 0.50 1.80 MIN. MAX. INCHES 0.031 0.000 0.007 0.012 0.059 0.071 0.059 0.012 0.020 0.70 0.071 0.028 0.002 0.50 BSC 0.020 BSC K 0.20 0.008 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw25 Application A H T1 C d D W E1 F 330±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 QFN3X3-20 A H T1 C d D W E1 F 330±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 TQFN3x3-16 (mm) Devices Per Unit Carrier Tape & Reel Dimensions Package Type Unit Quantity QFN3x3-20 Tape & Reel 3000 TQFN3x3-16 Tape & Reel 3000 A AB W F T P0OD0 B SECTION B-B SECTION A-A OD1 H A d

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw26 Taping Direction Information Classification Profile QFN3x3-20 &TQFN3x3-16 USER DIRECTION OF FEED

Copyright  ANPEC Electronics Corp. (Tsmax to TP) 3 °C/second max. 3°C/second max. Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. Time 25°C to peak temperature 6 minutes max. 8 minutes max.

  • Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.

** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 2. Pb-free Process – Classification Temperatures (Tc) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

Copyright  ANPEC Electronics Corp. Rev. A.6 - May, 2013 APW8819 www.anpec.com.tw28 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838