APW8805AQBI-TRG

APW8805A ANPEC | Alldatasheet

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Technical content

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw1 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. 3A 5V 1MHz Synchronous Buck Converter Features General Description

• High Efficiency up to 95%
• Adjustable Output Voltage from 0.6V to VVIN
• Integrated 75m W High Side / 55m W Low Side MOSFETs
• Low Dropout Operation: 100% Duty Cycle
• Mode Selection - APW8805A : Force PWM
• Stable with Low ESR Ceramic Capacitors
• Power-On-Reset Detection on VCC and VIN
• Integrated Soft-Start and Soft-Stop
• Over-Temperature Protection
• Over-Voltage Protection
• Under-Voltage Protection
• High/ Low Side Current Limit
• Power Good Indication
• Enable/Shutdown Function
• Current-Mode Operation with Internal Compensation
• Small TDFN3x3-10 Packages
• Lead Free and Green Devices Available (RoHS Compliant)

Applications

• Notebook Computer & UMPC
• LCD Monitor/TV
• Set-Top Box
• DSL, Switch HUB
• Portable Instrument APW8805A is a 3A synchronous buck converter with inte- grated 75m Ω high side and 55m Ω low side power MOSFETs. The APW8805A, design with a current-mode control scheme, can convert wide input voltage of 2.6V to 6V to the output voltage adjustable from 0.6V to 6V to provide excellent output voltage regulation. The APW8805A is equipped with force PWM mode opeation. The APW8805A is also equipped with Power-on-reset, soft-start, soft-stop, and whole protections (under-voltage, over-voltage, over-temperature and current-limit) into a single package. This device, available TDFN3x3-10, provides a very com- pact system solution external components and PCB area. Simplified Application Circuit VIN VCC POK ENOFF ON VIN SW FB GND APW8805A VOUT (option)

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw2 Ordering and Marking Information Pin Configuration Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol Parameter Rating Unit VVIN, VVCC Input Supply Voltage -0.3 ~ 6.5 V VSW SW to GND Voltage -1 ~VVCC+0.3 V POK, FB, EN to GND Voltage -0.3 ~ 6.5 V PD Power Dissipation Internally Limited W TJ Junction Temperature 150 oC TSTG Storage Temperature -65 ~ 150 oC TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. APW8805A Handling Code Temperature Range Package Code Package Code QB : TDFN3x3-10 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device Assembly Material APW 8805A XXXXX APW8805A QB : XXXXX - Date Code FB 1 VIN 3 10 EN VCC 2 GND 5

9 POK

(Top View) GNDGND 4 6 SW APW8805A Exposed pad11 GND

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw3 Thermal Characteristics Symbol Parameter Typical Value Unit θ JA Junction-to-Ambient Resistance in Free Air (Note 2) TDFN3x3-10 oC/W θ JC Junction-to-Case Resistance in Free Air (Note 3) TDFN3x3-10 oC/W Note 2: θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8P or TDFN3x3-10 is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P or TDFN3x3-10 package. Symbol Parameter Range Unit VVCC Control and Driver Supply Voltage 2.6~ 6 V VVIN Input Supply Voltage 2~6 V VOUT Converter Output Voltage 0.6~6 V L Inductance 1~2.2 µH IOUT Converter Output Current 0~3 A TA Ambient Temperature -40 ~ 85 oC TJ Junction Temperature -40 ~ 125 oC Recommended Operating Conditions (Note 4)

Electrical Characteristics

Symbo Parameter Test Conditions Min. Typ. Max. Unit SUPPLY CURRENT IVCC VCC Supply Current VFB=0.7V - 460 - µA IVCC_SDH VCC Shutdown Supply Current EN=GND - - 1 µA POWER-ON-RESET (POR) VCC POR Voltage Threshold VVCC Rising 2.3 2.4 2.5 V VCC POR Hysteresis - 0.2 - V VIN POR Voltage Threshold 1.5 1.7 1.9 V VIN POR Hysteresis - 0.2 - V REFERENCE VOLTAGE - 0.8 - V VREF Reference Voltage All temperature -1 - +1 % Output Accuracy IOUT=10mA~3A, VVCC=2.6~5V -1.5 - +1.5 % Unless otherwise specified, these specifications apply over V VCC=VVIN=5V, VOUT=3.3V, TA=25oC. Note 4: Refer to the typical application circuit.

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw4 Electrical Characteristics (Cont.) APW8805A Symbo Parameter Test Conditions Min. Typ. Max. Unit OSCILLATOR AND DUTY CYCLE FOSC Oscillator Frequency 0.85 1 1.15 MHz Maximum Converter’s Duty VFB=0.7V - 100 - % Minimum on Time - 100 - ns POWER MOSFET High Side P-MOSFET Resistance VVCC=5V, ISW=0.5A, TA=25oC - 75 90 mΩ Low Side N-MOSFET Resistance VVCC=5V, ISW=0.5A, TA=25 oC - 55 75 mΩ High/Low Side MOSFET Leakage Current - - 10 µA CURRENT-MODE PWM CONVERTER Gm Error Amplifier Transconductance - 550 - µA/V Error Amplifier DC Gain COMP=NC - 80 - dB Current Sense Transresistance - 400 - mΩ TD Dead Time - 20 - ns PROTECTIONS ILIM High Side MOSFET Current-Limit Peak Current 4 5 6 A TOTP Over-Temperature Trip Point - 160 - °C Over-Temperature Hysteresis - 50 - °C Over-Voltage Protection Threshold 120 - 135 %VREF Under-Voltage Protection Threshold 45 50 55 %VREF SOFT-START, ENABLE, AND INPUT CURRENTS Soft-Start Time - 1 - ms EN Enable Threshold - - 1.4 V EN Shutdown Threshold 0.5 - - V POK in from Lower (POK Goes High) 87 90 93 %VOUT POK Low Hysteresis (POK Goes Low) - 5 - %VOUT POK in from Higher (POK Goes High) 122 125 128 %VOUT POK Threshold POK High Hysteresis (POK Goes Low) - 5 - %VOUT Power Good Pull Low Resistance - 100 - Ω Unless otherwise specified, these specifications apply over V VCC=VVIN=5V, VOUT=3.3V, TA=25oC.

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw5 Typical Operating Characteristics Refer to the “Typical Application Circuit”. The test condition is VVCC=VVIN=5V, TA= 25oC unless otherwise specified. Output Voltage vs. Load Current Load Current, IOUT(A) Output Voltage, VOUT(V) 1.7 1.72 1.74 1.76 1.78 1.8 1.82 1.84 1.86 1.88 1.9 0 0.5 1 1.5 2 2.5 3 Efficiency vs. Load Current Load Current, IOUT(A) Efficiency (%) 100 0 1 2 3 VOUT=3.3V VVCC=5V 100 0 1 2 3 VOUT=1.8V VVIN=3.3VVVIN=5V Efficiency vs . Load Current Efficiency (%) Load Current , IOUT(A) Load Current, IOUT(A) Efficiency (%) Efficiency vs. Load Current VVIN=3.3VVVIN=5V VOUT=1.05V 100 0 1 2 3 Supply Voltage vs. P-FET Current Limit 2 3 4 5 6 Supply Voltage, VVIN(V) P-FET Current Limit, ILIM(A) 100 2 3 4 5 6 Supply Voltage, VVIN(V) MOSFET On Resistance, RON(mΩ ) N-FET P-FET Supply Voltage vs. MOSFET On Resistance

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw6 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified. TIME: 200µs/Div Enable without Loading VPOK , 5V/Div VEN IL , 1A/Div VOUT , 1V/Div, DC TIME: 200µs/Div Shutdown VPOK , 5V/Div VEN IL , 1A/Div VOUT , 1V/Div, DC Enable with 1.8A Loading TIME: 200µs/Div VPOK , 5V/Div VEN IL , 1A/Div VOUT , 1V/Div, DC Shutdown TIME: 200µs/Div VPOK , 5V/Div VEN IL , 1A/Div VOUT , 1V/Div, DC

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw7 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified. TIME: 20µs/Div Load Transient Response IOUT , 1A/Div VOUT , 100mV/Div, AC 2.5A TIME: 50µs/Div Load Transient Response IOUT , 1A/Div VOUT , 100mV/Div, AC 1.5A 10mA Over Voltage Protection TIME: 20µs/Div VPOK , 5V/Div IL , 1A/Div VOUT , 1V/Div, DC Normal Operating Waveform TIME: 1µs/Div VSW , 5V/Div IL , 1A/Div VOUT , 20mV/Div, DC

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw8 Pin Description NO. NAME FUNCTION 1 FB Output Feedback Input. The APW8805A senses the feedback voltage via FB and regulates the voltage at 0.8V. Connecting FB with a resistor-divider from the converter’s output sets the output voltage.

2 VCC

Signal Input. V CC supplies t he control circuitry, gate drivers. Connecting a ceramic bypass capacitor from VCC to GND to eliminate switching noise and voltage ripple on the input to the IC.

3 VIN

Power Input. VIN supplies the step -down converter switches. Connecting a ceramic bypass capacitor from VIN to GND to eliminate switching noise and voltage ripple on the input to the IC. 4,5 GND Ground. Power and signal ground. 6,7 SW Power Switching Output. SW is the Junction of the high-side and low-side Power MOSFETs to supply power to the output LC filter. 8 NC No connection. 9 POK Power Good Output. This pin is open-drain logic output that is pulled to the ground when the output voltage is out of regulation point. 10 EN Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off.

11 GND

(Exposed Pad) Ground and Exposed pad. Connect the exposed pad to the system ground plan with large copper area for dissipating heat into the ambient air.

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw9 Block Diagram SWGate Control Fault Logics Error Amplifier FB Inhibit POR Power- On- Reset Current Sense Amplifier Oscillator Slope Compensation Current Compartor Over Temperature Protection Current Limit Gat e Gm VIN OTP Current Sense Amplifier LOC LOC VCC EN 50%VREF Soft-start Shutdown POK GND Gate Driver UVP V REF OVP 125%VREF 90%VREF 0.8V Zero Crossing Comparator 125%VREF POK

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw10 Typical Application Circuit VIN VCC POK EN OFF ON VIN SW FB GND APW8805A VOUT 1.05V/3A COUT 22µFx2 CIN 22µF 1.5µH 4.7k 15k (option)R3 100k

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw11 Function Description VCC and VIN Power-On-Reset (POR) The APW8805A keeps monitoring the voltage on VCC and VIN pins to prevent wrong logic operations which may occur when VCC or VIN voltage is not high enough for internal control circuitry to operate. The VCC POR ris- ing threshold is 2.4V (typical) with 0.2V hysteresis and VIN POR rising threshold is 1.7V with 0.2V hysteresis. During start-up, the VCC and VIN voltage must exceed the enable voltage threshold. Then, the IC starts a start- up process and ramps up the output voltage to the volt- age target. Output Under-Voltage Protection (UVP) In the operational process, if a short-circuit occurs, the output voltage will drop quickly. Before the current-limit circuit responds, the output voltage will fall out of the re- quired regulation range. The under-voltage continually monitors the FB voltage after soft-start is completed. If a load step is strong enough to pull the output voltage lower than the under-voltage threshold, the IC starts soft-stop function and shuts down converter’s output. The under-voltage threshold is 50% of the nominal out- put voltage. The under-voltage comparator has a built-in 3µs noise filter to prevent the chips from wrong UVP shut- down being caused by noise. APW8805A will be latched after under-voltage protection. Over-Voltage Protection (OVP) The over-voltage function monitors the output voltage by FB pin. When the FB voltage increases over 125% of the reference voltage due to the high-side MOSFET failure or for other reasons, the over-voltage protection comparator will trigger soft-stop function and shutdown the converter output. Over-Temperature Protection (OTP) The over-temperature circuit limits the junction tempera- ture of the APW8805A. When the junction temperature exceeds TJ=+160oC, a thermal sensor turns off the both power MOSFETs, allowing the devices to cool. The ther- mal sensor allows the converters to start a start-up pro- cess and to regulate the output voltage again after the junction temperature cools by 50oC. The OTP is designed Current-Limit Protection The APW8805A monitors the output current, flows through the high-side and low-side power MOSFETs, and limits the current peak at current-limit level to prevent the IC from damaging during overload, short-circuit and over- voltage conditions. Typical high side power MOSFET cur- rent limit is 5A. Soft-Start The APW8805A has a built-in soft-start to control the rise rate of the output voltage and limit the input current surge during start-up. During soft-start, an internal voltage ramp connected to one of the positive inputs of the error amplifier, rises up to replace the reference voltage (0.8V) until the voltage ramp reaches the reference voltage. Dur- ing soft-start without output over-voltage, the APW8805A converter’s sinking capability is disabled until the output voltage reaches the voltage target. Soft-Stop At the moment of shutdown controlled by EN signal, un- der-voltage event or over-voltage event , the APW8805A initiates a soft-stop process to discharge the output volt- age in the output capacitors. Certainly, the load current also discharges the output voltage. During soft-stop, the internal voltage ramp (VRAMP) falls down to replace the reference voltage. Therefore, the output voltage falls down slowly at the light load. After the soft-stop interval elapses, the soft-stop process ends and the IC turns. with a 50 oC hysteresis to lower the average T J during continuous thermal overload conditions, increasing life- time of the APW8805A. Enable and Shutdown Driving EN to ground places the APW8805A in shutdown. In shutdown mode, the internal N-Channel power MOSFET turns off, all internal circuitry shuts down and the quiescent supply current reduces to less than 1 µA.

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw12 Function Description (Cont.) Powr Good Indicator POK is actively held low in shutdown and soft-start status. In the soft-start process, the POK is an open-drain. When the soft-start is finished, the POK is released. In normal operation, the POK window is from 90% to 125% of the converter reference voltage. When the output voltage has to stay within this window, POK signal will become high. When the output voltage outruns 90% or 125% of the target voltage, POK signal will be pulled low immediately. In order to prevent false POK drop, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient.

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw13

Application Information

Because buck converters have a pulsating input current, a low ESR input capacitor is required. This results in the best input voltage filtering, minimizing the interference with other circuits caused by high input voltage spikes. Also, the input capacitor must be sufficiently large to sta- bilize the input voltage during heavy load transients. For good input voltage filtering, usually a 22µF input capacitor is sufficient. It can be increased without any limit for better input-voltage filtering. Ceramic capacitors show better performance because of the low ESR value, and they are less sensitive against voltage transients and spikes com- pared to tantalum capacitors. Place the input capacitor as close as possible to the input and GND pin of the device for better performance. Inductor Selection For high efficiencies, the inductor should have a low DC resistance to minimize conduction losses. Especially at high-switching frequencies, the core material has a higher impact on efficiency. When using small chip inductors, the efficiency is reduced mainly due to higher inductor core losses. This needs to be considered when selecting the appropriate inductor. The inductor value de- termines the inductor ripple current. The larger the induc- tor value, the smaller the inductor ripple current and the lower the conduction losses of the converter. Conversely, larger inductor values cause a slower load transient response. A reasonable starting point for setting ripple current, Δ IL, is 40% of maximum output current. The rec- ommended inductor value can be calculated as below: LSW IN OUT OUT IF V V1V L Δ⋅  − IL(MAX) = IOUT(MAX) + 1/2 x Δ IL To avoid the saturation of the inductor, the inductor should be rated at least for the maximum output current of the converter plus the inductor ripple current. Output Voltage Setting In the adjustable version, the output voltage is set by a resistive divider. The external resistive divider is con- nected to the output, allowing remote voltage sensing as  +⋅=  +⋅= 2R 1R18.02R 1R1VV REFOUT shown in “Typical Application Circuits”. A suggestion of maximum value of R2 is 20kΩ to keep the minimum cur- rent that provides enough noise rejection ability through the resistor divider. The output voltage can be calculated as below: Output Capacitor Selection The current-mode control scheme of the APW8805A al- lows the use of tiny ceramic capacitors. The higher ca- pacitor value provides the good load transients response. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. If required, tantalum capacitors may be used as well. The output ripple is the sum of the voltages across the ESR and the ideal output capacitor. ⋅⋅+⋅⋅  −⋅ OUTSWSW IN OUT OUT OUT CF8 1ESRLF V V1V V When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage char- acteristics of all the ceramics for a given value and size. R2 ≤ 20kΩAPW8805A FB GND VOUT R1≤ 80Ω VIN VOUT IL N-FET SW IOUT CIN COUT IIN ESR P-FET IP-FET

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw14 Application Information (Cont.) Output Capacitor Selection (Cont.) ILIM IL IPEAK IOUT IP-FET Δ IL Layout Consideration For all switching power supplies, the layout is an impor- tant step in the design; especially at high peak currents and switching frequencies. If the layout is not carefully done, the regulator might show noise problems and duty cycle jitter. 1. The input capacitor should be placed close to the VIN and GND. Connecting the capacitor and VIN/GND with short and wide trace without any via holes for good input voltage filtering. The distance between VIN/GND to capacitor less than 2mm respectively is recommended. 2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed as close as possible to the SW pin to minimize the noise coupling into other circuits. 3. The output capacitor should be place closed to SW and GND. 4. Since the feedback pin and network is a high imped- ance circuit the feedback network should be routed away from the inductor. The feedback pin and feed- back network should be shielded with a ground plane or trace to minimize noise coupling into this circuit. 5. A star ground connection or ground plane minimizes ground shifts and noise is recommended. APW8805A Recommended Footprint Ground plane for ThermalPAD ThermalVia diameter 12mil X 5 0.75 0.5 TDFN3x3-10 2.70 0.275 1.75 0.3 Unit: mm SW VOUT VCC APW8805A Layout Consideration CIN L1COUT GND R2 Via To VOUT

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw15

Package Information

D E Pin 1 A b Pin 1 Corner E2L e 0.70 0.069 0.028 0.002 0.50 BSC 0.020 BSC 0.20 0.008K 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122 SYMBOL MIN. MAX. 0.80 0.00 0.18 0.30 2.20 2.70 0.05 1.40 A b D E e L MILLIMETERS A3 0.20 REF TDFN3x3-10 0.30 0.50 1.75

0.008 REF

MIN. MAX. INCHES 0.031 0.000 0.007 0.012 0.087 0.106 0.055 0.012 0.020 Note : 1. Followed from JEDEC MO-229 VEED-5.

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw16 Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 TDFN3x3-10 (mm) Carrier Tape & Reel Dimensions A AB W F T P0OD0 B SECTION B-B SECTION A-A OD1 H A d Devices Per Unit Package Type Unit Quantity TDFN3x3-10 Tape & Reel 3000

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw17 Taping Direction Information TDFN3x3-10 USER DIRECTION OF FEED

Copyright  ANPEC Electronics Corp. Rev. A.2 - Aug., 2013 APW8805A www.anpec.com.tw18 Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds Average ramp-up rate (Tsmax to TP) 3 °C/second max. 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 183 °C 60-150 seconds 217 °C 60-150 seconds Peak package body Temperature (Tp)* See Classification Temp in table 1 See Classification Temp in table 2 Time (tP) within 5°C of the specified classification temperature (Tc) 20 seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. Time 25°C to peak temperature 6 minutes max. 8 minutes max. * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.

Copyright  ANPEC Electronics Corp. Table 2. Pb-free Process – Classification Temperatures (Tc) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)