APW8724 ANPEC | Alldatasheet

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Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw1 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Common single PWM Controller with Multiform supply Voltage APW8724 Features General Description

  • Adjustable Output Voltage from +0.6V to +5.0V - 0.6V Reference Voltage - +0.6% Accuracy
  • Operates from An Input Battery Voltage Range of +3V to +25V
  • Multiform Purpose Input Voltage Collocation - VCC=5V / VIN=8~19V For NB application - VCC=5~12V / VIN=5~12V For table PC application
  • Remote Feedback Sense for Excellent Output Voltage Regulation
  • Power-On-Reset Monitoring on VCC pin
  • Excellent line and load transient responses
  • Ultrasonic Operation Eliminated Audio Noise
  • PFM mode for increased light load efficiency
  • 300kHz Constant PWM Switching Frequency
  • Integrated MOSFET Drivers
  • Integrated Bootstrap Forward P-CH MOSFET
  • Adjustable Integrated Soft-Start
  • Power Good Monitoring
  • 70% Under-Voltage Protection
  • 125% Over-Voltage Protection
  • Adjustable Current-limit protection - Using Sense Low-Side MOSFET’s RDS(ON)
  • Over-Temperature Protection
  • TDFN3x3-10 Package
  • Lead Free and Green Devices Available (RoHS Compliant)

Applications

  • Notebook
  • Table PC
  • Hand-Held Portable
  • AIO PC
  • Wide input DC/DC Regulators The APW8724 is a single-phase, constant on-time, syn- chronous PWM controller, which drives N-channel MOSFETs. The APW8724 steps down high voltage to generate low-voltage chipset, RAM supplies in notebook computers or mother board applications. The APW8724 provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode. In Pulse Frequency Mode (PFM), the APW8724 provides very high efficiency over light to heavy loads with loading- modulated switching frequencies. In PWM Mode, the con- verter works nearly at constant frequency for low-noise requirements. The unique ultrasonic mode maintains the switching frequency above 37kHz, which eliminates noise in audio application. APW8724 is built in remote sense function for applications that require remote sense. The APW8724 is equipped with accurate positive current limit, output under-voltage, and output over-voltage protections, perfect for multiform applications. The Power- On-Reset function monitors the voltage on VCC to pre- vent wrong operation during power-on. The APW8724 has an internal 4ms digital soft start that ramps up the output voltage with programmable slew rate to reduce the start- up current. The enable function can let user easy to apply APW8724. The APW8724 is available in 10pin TDFN 3x3 package respectively. VOUTL EN APW8724 VIN FBRTN POK 5~12V PHASE UGATE LGATE/ OCSET RPOK VCC Simplified Application Circuit

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw2 APW8724 Ordering and Marking Information Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration = GND and Thermal Pad (connected to GND plane for better heat dissipation) LGATE/OCSET 5 6 VCC

7 FBRTN

10 PHASE

(top view) BOOT 1 UGATE 2 POK 3 GND 4 Absolute Maximum Ratings (Note 1) Symbol Parameter Rating Unit VCC VCC Supply Voltage (VCC to GND) -0.3 ~ 16 V VBOOT-GND BOOT Supply Voltage (BOOT to GND) -0.3 ~ 44 V VBOOT BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 16 V VEN EN to GND -0.3 ~ VCC+0.3 V All Other Pins (POK, FBRTN and FB to GND) -0.3~7 V UGATE Voltage (UGATE to PHASE) <20ns pulse width > 20ns pulse width -5 ~ VBOOT+0.3 -0.3 ~ VBOOT+0.3 V LGATE Voltage (LGATE to GND) < 20ns pulse width > 20ns pulse width -5 ~ VCC+0.3 -0.3 ~ VCC+0.3 V VPHASE PHASE Voltage (PHASE to GND) < 20ns pulse width > 20ns pulse width -5 ~ 35 -0.3~ 28 V APW8724 Handling Code Temperature Range Package Code APW8724QB: Assembly Meterial Package Code Temperature Range I : -40 to 85 oC Handling Code Assembly Meterial G : Halogen and Lead Free Device : QB TDFN3x3-10 TR : Tape & Reel L : Lead Free Device APW 8724 XXXXX XXXXX - Date Code

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw3 APW8724 Thermal Characteristics Symbol Parameter Typical Value Unit θ JA Thermal Resistance -Junction to Ambient (Note 2) TDFN3x3-10 55 °C/W Note 2: θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of package is soldered directly on the PCB. Symbol Parameter Range Unit VIN Converter Input Voltage 3 ~ 25 V VCC VCC Supply Voltage 4.5 ~ 13.2 V VOUT Converter Output Voltage 0.6~5 V IOUT Converter Output Current 0~25 A TA Ambient Temperature -40 ~ 85 oC TJ Junction Temperature -40 ~ 125 oC Recommended Operating Conditions (Note 3) Note 3: Refer to the application circuit for further information. Absolute Maximum Ratings (Cont.) (Note 1) Symbol Parameter Rating Unit TJ Maximum Junction Temperature 150 oC TSTG Storage Temperature -65 ~ 150 oC TSDR Maximum Soldering Temperature, 10 Seconds 260 oC Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Electrical Characteristics

Symbal Parameter Test Condition Min. Typ. Max. Unit Reference VOLTAGE Reference Voltage - 0.6 - V TA = 25 oC -0.6 - +0.6 % VREF Regulation Accuracy TA = -40 oC ~ 85 oC, Line / Load Transient -1.0 - +1.0 % IFB FB Input Bias Current FB=0.5V - - 1 µA IFBRTN FBRTN Leakage Current - - 1 µA These specifications apply for TA = -40oC to +85oC, unless otherwise stated. All typical specifications TA= +25 oC, VCC = 12V

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw4 APW8724 These specifications apply for TA = -40oC to +85oC, unless otherwise stated. All typical specifications TA= +25 oC, VCC = 12V APW8724 Symbal Parameter Test Condition Min. Typ. Max. Unit SUPPLY CURRENT IVCC VCC Input Bias Current VCC Current, EN=5V, VFB=0.7V, PHASE=0.5V - 2 3 mA IVCC_SHD N VCC Shutdown Current EN=GND, VCC=5V - - 10 µA SWITCHING FREQUENCY AND DUTY TON PWM On Time Vin=12V, VOUT=1V 222 278 333 ns TON(MIN) Minimum on time - 100 - ns TOFF(MIN) Minimum off time VFB=0.45V, VPHASE=-0.1V 300 400 500 ns Minimum Ultrasonic Skip Operating Frequency 25 37 - kHz Power On Timing Maximum Current Limit Setting Time ROCSET is open - - 500 µs IOCSET Early Sourcing Timing From POR_R to Internal sample clock start - 150 - µs D1 only The First Pulse Delay by EA Offset Positive Offset 60mV(Typ.), When TSS is about 4ms, the first pulse delays from sample & hold completed - 350 - µs TSS Internal Soft Start Time VOUT=0% to VOUT Regulation(95%) - 4 - ms GATE DRIVER 5V UG Pull-Up Resistance VCC=5V, BOOT-UG=1V - 5 - Ω 12V UG Pull-Up Resistance VCC=12V, BOOT-UG=1V - 3 - Ω 5V UG Sink Resistance VCC=5V, UG-PHASE=1V - 2 - Ω 12V UG Sink Resistance VCC=12V, UG-PHASE=1V - 1.3 - Ω 5V LG Pull-Up Resistance VCC=5V, VCC-LG=1V - 5 - Ω 12V LG Pull-Up Resistance VCC=12V, VCC-LG=1V - 3 - Ω 5V LG Sink Resistance VCC=5V, LG-GND=1V - 2 - Ω 12V LG Sink Resistance VCC=12V, LG-GND=1V - 1.3 - Ω UG to LG Dead time UG falling to LG rising at VCC=5V - 40 - ns UG falling to LG rising at VCC=12V - 20 - ns LG to UG Dead time LG falling to UG rising at VCC=5V - 40 - ns LG falling to UG rising at VCC=12V - 20 - ns BOOTSTRAP SWITCH VF Ron VVCC – VBOOT-GND, IF = 10mA - 0.2 0.4 V IR Reverse Leakage VBOOT-GND = 30V, VPHASE = 25V, VVCC = 5V - - 0.5 µA

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw5 APW8724 These specifications apply for TA = -40oC to +85oC, unless otherwise stated. All typical specifications TA= +25 oC, VCC = 12V APW8724 Symbal Parameter Test Condition Min. Typ. Max. Unit VCC POR THRESHOLD VVCC_THR Rising VCC POR Threshold Voltage 4.25 4.35 4.45 V VCC POR Hysteresis - 300 - mV CONTROL INPUTS Shutdown - - 0.4 EN Threshold Enable 0.83 - - V EN Leakage EN=0V - 0.1 1.0 µA POWER-OK INDICATOR POK in from Lower (POK Goes High) 87 90 93 % POK out from normal falling (POK Goes Low) 65 70 75 % VPOK POK Threshold POK out from normal rising (POK Goes Low) 120 125 130 % IPOK POK Leakage Current VPOK=5V - 0.1 1 µA POK Sink Current VPOK=0.5V 5 15 - mA POK Enable Delay Time VOUT from 0% to POK High - 5.5 - ms CURRENT SENSE IOCSET IOCSET OCP Threshold IOCSET Sourcing 22.5 25 27.5 µA TCIOCSET IOCSET Temperature Coefficient On The Basis of 25°C - 2780 - ppm/ oC VROCSET Maximum Current Limit Threshold ROCSET open 360 400 440 mV Zero Crossing Comparator Offset VGND-PHASE Voltage -3 0 3 mV PROTECTION VUV UVP Threshold 65 70 75 % UVP Debounce Interval - 30 - µs UVP Enable Delay VOUT from 0% to UVP enable - 5.5 ms VOVR OVP Rising Threshold VFB rising, LG fully turn on 120 125 130 % OVP Falling Threshold VFB falling, Driver both off - 105 - % OVP Propagation Delay VFB Rising - 2 - µs TOTR OTP Rising Threshold (Note 4) - 150 - oC OTP Hysteresis (Note 4) - 25 - oC

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw6 APW8724 Pin Description PIN No. Name FUNCTION 1 BOOT Supply Input for The UGATE Driver and An Internal Level-shift Circuit. Connect to an external capacitor to create a boosted voltage suitable to drive a logic -level N-channel MOSFET. 2 UGATE Output of The High-side MOSFET Driver. Connect this pin to Gate of the high -side MOSFET. 3 POK Power Good Output. POK is an open drain output used to indicate the status of the output voltage. Connect the POK in to +5V through a pull -high resistor.

4 GND Signal Ground for The IC

5 LGATE/OCSET

Output of The Low-side MOSFET Driver And Current-Limit Setting Input. Connect this pin to Gate of the low-side MOSFET. There is an internal source current 25µA through a resistor from LGATE/OCSET pin to GND before power on. This action is used to m onitor the voltage drop across the Drain and Source of the low -side MOSFET for current limit. 6 VCC Supply Voltage Input Pin for Control Circuitry. Connect +5V~+12V from the VCC pin to the GND. Decoupling at least 1µF of a MLCC capacitor from the VCC pin to the GND. 7 FBRTN This pin is the negative node of the differential remote voltage sensing. The RTN pin should be connected to the remote GND sense point directly. 8 FB Output Voltage Feedback Pin. This pin is connected to the resistive divider in remote side that set the desired output voltage. The P OK, UVP, and OVP circuits detect this signal to report output voltage status. 9 EN Enable/Shutdown Pin. When EN=1, enable the PWM controller, EN=0, shutdown t he PWM controller. Junction Point of The High-side MOSFET Source, Output Filter Inductor and The Low-side MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE serves as the lower supply rail for the U G high-side gate driver. Exposed pad GND Signal Ground for The IC

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw7 APW8724 Typical Operating Characteristics 0.59 0.595 0.6 0.605 0.61 -20 0 20 40 60 80 100 Reference Voltage (V) Junction Temperature (oC) Reference Voltage vs. Junction Temperature VCC = 12V 120 0.1 1 100 Efficiency vs. Load Current FSW=300KHz, VOUT=1.05V Efficiency (%) H-Side: SM4370NSKP*1 L-Side: SM4373NSKP*1 VIN=19V VIN=8V 10.0 Switching Frequency (kHz) 250 260 270 280 290 300 310 320 330 340 350 Switching Frequency vs. Junction Temperature -20 0 20 40 60 80 100 120 Junction Temperature (oC) 3 5 7 9 11 13 15 17 19 21 Input Voltage(V) Switching Frequency (kHz)(%) Input Voltage vs Switching Frequency 150 200 250 300 350 400 23 25 Vout=1.05V ,Iout=5A(PWM) 0 5 10 15 20 25 1.050 1.060 1.070 1.040 Input Voltage vs Output Voltage Input Voltage(V) Output Voltage (V) 1.030 -20 0 20 40 60 80 100 120 OCSET Current Source (uA) IOCSET vs. Junction Temperature Junction Temperature (oC)

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw8 APW8724 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified. CH 1: VIN , 10V/Div CH 2: Vout , 500mV/Div TIME : 2ms/Div Power On CH 3: VPHASE , 10V/Div VIN VOUT VPHASE CH 2: Vout , 500mV/Div CH 3: VPHASE , 10V/Div TIME : 50ms/Div CH 1: VIN , 10V/Div Power Off VIN VOUT VPHASE Enable CH 1: VEN , 5V/Div CH 2: Vout , 500mV/Div TIME : 1ms/Div CH 3: VPHASE , 10V/Div VEN VOUT VPHASE Shutdown CH 1: VEN , 5V/Div CH 2: Vout , 500mV/Div TIME : 5ms/Div CH 3: VPHASE , 10V/Div VEN VOUT VPHASE RLOAD = 12Ω

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw9 APW8724 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=19V, TA= 25oC unless otherwise specified. Over-Current Protection CH 1: VOUT , 10V/Div CH 2: VLGATE , 10V/Div TIME : 20ms/Div ROCSET = 5.1k ,RDS (low Side)= 8.4mΩ VOUT IL VLGATE CH 3: VUGATE , 20V/Div CH 4: IL , 10A /Div VUGATE Under-Voltage Protection CH 1: VFB , 500mV/Div CH 2: VLGATE , 10V/Div CH 3: VUGATE , 20V/Div TIME : 10us/Div VFB VLAGTE VUAGTE CH 1: VOUT , 500mV/Div CH 2: VPOK , 5V/Div TIME : 1ms/Div Power OK VOUT POK CH 1: VOUT , 50mV/Div CH 2: IOUT , 5A /Div TIME : 200us/Div Load Transient VOUT IOUT

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw10 APW8724 Block Diagram FB Error Comparator OV UV 70% VREF 125% VREF VREF POR VCC EN Digital Soft Start PWM Signal Controller VCC BOOT UGATE PHASE LGATE Thermal Shutdown GND POK Fault Latch Logic On-Time Generator VREF x 70% VREF x 125% ZC PHASE VCC Sample and Hold VROCSET To LGATE 25µA Current Limit VROCSET Sense Low-Side FBRTN Vcompare VREF Vcompare

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw11 APW8724 Typical Application Circuit PHASE FBRTN GND VCC LGATE/ OCSET APW8724 (TDFN3*3-10) CIN 560µF 1µH VIN UGATE VCC Supply 5V to 12V BOOT6 7 5 RVCC 2R2CVCC 1µF APM4350 APM435 CBOOT 0.1µF ROCSETFB POK3 RPOK 100kΩ EN Enable signal 15kΩ VOUT COUT 820µF 10kΩ COUT MLCC 22µFx 4 L O A D V+_near V-_remote V+_remote ON V-_near OFF 5V Pull-High Source

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw12 APW8724 Function Description Constant-On-Time PWM Controller with Input Feed-For- ward The constant-on-time control architecture is a pseudo- fixed frequency with input voltage feed-forward. This ar- chitecture relies on the output filter capacitor’s effective series resistance (ESR) to act as a current-sense resis- tor so the output ripple voltage provides the PWM ramp signal. In PFM operation, the high-side switch on-time is controlled by the on-time generator is determined solely by a one-shot whose pulse width is inversely propor- tional to the input voltage and directly proportional to the output voltage. In PWM operation, the high-side switch on-time is determined by a switching frequency control circuit in the on-time generator block. The switching frequency control circuit senses the switch- ing frequency of the high-side switch and keeps regulat- ing it at a constant frequency in PWM mode. The design improves the frequency variation and is more outstand- ing than a conventional constant-on-time controller, which has large switching frequency variation over input voltage, output current, and temperature. Both in PFM and PWM, the on-time generator, which senses input voltage on PHASE pin, provides very fast on-time response to input line transients. Another one-shot sets a minimum off-time (typical: 400ns). The on-time one-shot is triggered if the error com- parator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time one- shot has timed out. Pulse-Frequency Modulation (PFM) In PFM mode, an automatic switchover to pulse-frequency modulation (PFM) takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current zero crossing. This mechanism causes the threshold between PFM and PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). The on-time of PFM is given by: IN OUT SW PFMON V V F 1T ×=− Ultrasonic Mode Where FSW is the nominal switching frequency of the con- verter in PWM mode. The load current at handoff from PFM to PWM mode is given by: In this case, APW8724 operates in ultrasonic mode with PFM when the load is zero. The ultrasonic mode is illus- trated as below description. The ultrasonic mode activates an unique PFM mode with a minimum switching frequency of 25kHz. The minimum frequency 25kHz of ultrasonic mode eliminates audio- frequency interference in light load condition. It will transit to unique PFM mode when output loading makes the frequency bigger than ultrasonic frequency. In ultrasonic mode, the controller automatically transits to fixed-frequency PWM operation when the load reaches the same critical conduction point (I LOAD(PFM to PWM)). When the controller detects that no switching has oc- curred within about 40 µs (Typical), an ultrasonic pulse will be occurred. The ultrasonic controller turns on the low-side MOSFET firstly to reduce the output voltage. Af- ter feedback voltage drops below the internal reference voltage, the controller turns off the low-side MOSFET and triggers a constant-on-time. When the constant-on-time has expired, the controller turns on the low-side MOSFET again until the inductor current is below the zero-cross- ing threshold. The behavior is the same as PFM mode. IN OUT SW OUTIN PFMON OUTIN )PFMtoPWM(LOAD V V F L VV TL VV ××−= ×−×= − Power-On-Reset (POR) A Power-On-Reset (POR) function is designed to prevent wrong logic controls when the VCC voltage is low. The POR function continually monitors the bias supply volt- age on the VCC pin if at least one of the enable pins is set high. When the rising VCC voltage reaches the rising POR voltage threshold (4.35V, typical), the POR signal goes high and the chip initiates soft-start operations. When this voltage drops lower than 4.25V (typical), the POR disables the chip.

Copyright  ANPEC Electronics Corp. threshold, the PWM is not allowed to initiate a new cycle. threshold by an amount equal to the inductor ripple current. resistance, inductor value, and input voltage. Figure 1. Current-Limit Algorithm will clear the latch and bring the chip back to operation. rent-limit method is effective in almost every circumstance.

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw14 APW8724 Function Description (Cont.) EN Pin Control When V EN is above the EN high threshold (0.83V, minimum). th converter is enabled in automatic PFM/ PWM operation mode. When V EN is below the EN low threshold (0.4V, maximum), the chip is in the shutdown and only low leakage current is taken from VCC. Adaptive Shoot-Through Protection of the PWM Con- verter Remote Sense APW8724 has a FBRTN pin for applications that require remote sense. In some applications where high current, low voltage and accurate output voltage regulation are needed, FBRTN can sense the negative terminal of re- mote load capacitor directly, and improve output voltage drop which is due to the board interconnection loss. The gate drivers incorporate an adaptive shoot-through protection to prevent high-side and low-side MOSFETs from conducting simultaneously and shorting the input supply. This is accomplished by ensuring the falling gate has turned off one MOSFET before the other is allowed to rise. During turn-off the low-side MOSFET, the LGATE voltage is monitored until it is below 1.5V threshold, at which time the UGATE is released to rise after a constant delay. During turn-off of the high-side MOSFET, the UGATE-to- PHASE voltage is also monitored until it is below 1.5V threshold, at which time the LGATE is released to rise after a constant delay. Power OK Indicator The APW8724 features an open-drain POK output pin to indicate one of the IC's working statuses including soft- start, under-voltage fault, over-current fault. In normal operation, when the output voltage rises 90% of its target value, the POK goes high. When the output voltage outruns 50% or 125% of the target voltage, POK signal will be pulled low immediately.

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw15 APW8724 Output Voltage Selection The output voltage can be programmed with a resistive divider. Use 1% or better resistors for the resistive divider is recommended. The FB pin is the inverter input of the error amplifier, and the reference voltage is 0.6V. The output voltage is determined by: Where R1 is the resistor connected from VOUT to FB and R2 is the resistor connected from FB to the GND.  +×= OUT R R10.6V

Application Information

The duty cycle (D) of a buck converter is the function of the input voltage and output voltage. Once an output voltage is fixed, it can be written as: IN OUT V VD = IN OUT SW OUTIN RIPPLE V V LF V- VI ××= Output Capacitor Selection The inductor value (L) determines the inductor ripple current, I RIPPLE , and affects the load transient reponse. Higher inductor value reduces the inductor’s ripple cur- rent and induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by: ESRRIPPLEESR SWOUT RIPPLE OUTC RIV F8C IV ×=Δ Where FSW is the switching frequency of the regulator. Although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff exists between the inductor’s ripple current and the regu- lator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (F SW) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the power dissipa- tion of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, selecting an inductor which is capable of carrying the required peak current without going into saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This results in a larger output ripple voltage. Besides, the inductor needs to have low DCR to reduce the loss of efficiency. Output voltage ripple and the transient volta ge devia- tion are factors which have to be taken into con sider- ation when selecting an output capacitor. Higher capaci- tor value and lower ESR reduce the out put ripple and the load transient drop. Therefore, selecting high per- formance low ESR capacitors is recommended for switching regulator applications. In addition to h igh frequency noise related to MOSFET turn-on and turn - off, the output voltage ripple includes the capaci tance voltage drop Δ VCOUT and ESR voltage drop Δ VESR caused by the AC peak-to-peak inductor’s current. These two voltages can be represented by: These two components constitute a large portion of the total output voltage ripple. In some applications, multiple capacitors have to be paralleled to achieve the desired ESR value. If the output of the converter has to support another load with high pulsating current, more capaci- tors are needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. A small decoupling capacitor (1 µF) in parallel for bypass- ing the noise is also recommended, and the voltage rat- ing of the output capacitors are also must be considered. To support a load transient that is faster than the switch- ing frequency, more capacitors are needed for reducing the voltage excursion during load step change. Another aspect of the capacitor selection is that the total AC cur- rent going through the capacitors has to be less than the rated RMS current specified on the capacitors in order to prevent the capacitor from over-heating. Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select- ing the capacitor voltage rating to be at least 1.3 times

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw16 APW8724 Application Information (Cont.) Input Capacitor Selection (Cont.) MOSFET Selection The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs should be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET: The selection of the N-channel power MOSFETs are determined by the RDS(ON) , reversing transfer capaci- tance (CRSS) and maximum output current requirement. The losses in the MOSFETs have two components: conduction loss and transition loss. For the high-side and low-side MOSFETs, the losses are approximately given by the following equations: Phigh-side = IOUT 2 (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW Plow-side = IOUT 2 (1+ TC)(RDS(ON))(1-D) Layout Consideration In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at higher frequency, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed circuit traces should minimize interconnect- ing impedances and the magnitude of voltage spike. Besides, signal and power grounds are to be kept sepa- rating and finally combined using ground plane construc- tion or single point grounding. The best tie-point between the signal ground and the power ground is at the nega- tive side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not recommended. Below is a checklist for your layout: For the low-side MOSFET, before it is turned on, the body diode has been conducting. The low-side MOSFET driver will not charge the miller capacitor of this MOSFET. In the turning off process of the low-side MOSFET, the load current will shift to the body diode first. The high dv/ dt of the phase node voltage will charge the miller capaci- tor through the low-side MOSFET driver sinking current path. This results in much less switching loss of the low- side MOSFETs. The duty cycle is often very small in high battery voltage applications, and the low-side MOSFET will conduct most of the switching cycle; therefore, when using smaller R DS(ON) of the low-side MOSFET, the con- verter can reduce power loss. The gate charge for this MOSFET is usually the secondary consideration. The high-side MOSFET does not have this zero voltage switch- ing condition; in addition, it conducts for less time com- pared to the low-side MOSFET, so the switching loss tends to be dominant. Priority should be given to the MOSFETs with less gate charge, so that both the gate driver loss and switching loss will be minimized. Where IOUT is the load current TC is the temperature dependency of R DS(ON) FSW is the switching frequency tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction losses while the high-side MOSFET includes an additional transition loss. The switching interval, tSW, is the function of the reverse transfer capacitance C RSS. The (1+TC) term is a factor in the temperature dependency of the R DS(ON) and can be extracted from the “R DS(ON) vs. Temperature” curve of the power MOSFET. higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2, where IOUT is the load current. During power-up, the input capacitors have to handle great amount of surge current. For low-duty notebook appliactions, ceramic capacitor is recommended. The capacitors must be connected be- tween the drain of high-side MOSFET and the source of low-side MOSFET with very low-impeadance PCB layout.

  • Keep the switching nodes (UGATE, LGATE, BOOT, and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw17 APW8724

  • Locate the resistor-divider close to the FB pin to mini- mize the high impedance trace. In addition, FB pin traces can’t be close to the switching signal traces (UGATE, LGATE, BOOT, and PHASE). Application Information (Cont.) Layout Consideration (Cont.)
  • The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and discharging current. The traces from the gate drivers to the MOSFETs (UGATE and LGATE) should be short and wide.
  • Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane be- tween the two pads reduces the voltage bounce of the node. In addition, the large layout plane between the drain of the MOSFETs (VIN and PHASE nodes) can get better heat sinking.
  • The PGND is the current sensing circuit reference ground and also the power ground of the LGATE low- side MOSFET. On the other hand, the PGND trace should be a separate trace and independently go to the source of the low-side MOSFET. Besides, the cur- rent sense resistor should be close to OCSET pin to avoid parasitic capacitor effect and noise coupling.
  • Decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. (For example, place the decoupling ceramic capacitor close to the drain of the high-side MOSFET as close as possible.)
  • The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output bulk capaci- tors should be close to the loads. The input capaci- tor’s ground should be close to the grounds of the output capacitors and low-side MOSFET. possible and there should be no other weak signal traces in parallel with theses traces on any layer. Recommended Minimum Footprint 0.30mm 1.75mm Ground plane for ThermalPAD ThermalVia diameter 12mil X 5 0.275mm0.75mm 0.50mm TDFN3X3 -10 L and Pattern R ecommendation 2.70mm

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw18 APW8724

Package Information

Note : 1. Followed from JEDEC MO-229 VEED-5. aaa C NX b A KL e E2Pin 1 Corner Pin 1 E D SYMBOL MIN. MAX. 0.80 0.00 0.18 0.30 2.20 2.70 0.05 1.40 A b D E e L MILLIMETERS A3 0.20 REF TDFN3x3-10 0.30 0.50 1.75

0.008 REF

MIN. MAX. INCHES 0.031 0.000 0.007 0.012 0.087 0.106 0.055 0.012 0.020 0.70 0.069 0.028 0.002 0.50 BSC 0.016 BSC 0.20 0.008K 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122 0.08 0.003aaa

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw19 APW8724 Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 TDFN3x3-10 (mm) Carrier Tape & Reel Dimensions A AB W F T P0OD0 B SECTION B-B SECTION A-A OD1 H A d Devices Per Unit Package Type Unit Quantity TDFN3x3-10 Tape & Reel 3000

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw20 APW8724 Taping Direction Information TDFN3x3-10 USER DIRECTION OF FEED Classification Profile

Copyright  ANPEC Electronics Corp. (Tsmax to TP) 3 °C/second max. 3 °C/second max. Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. Time 25°C to peak temperature 6 minutes max. 8 minutes max.

  • Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.

** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 2. Pb-free Process – Classification Temperatures (Tc) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

Copyright  ANPEC Electronics Corp. Rev. A.1 - Jan., 2013 www.anpec.com.tw22 APW8724 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838