APW8700 ANPEC | Alldatasheet
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Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw1 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Dual-Phase Synchronous-Rectifier Buck Controller Features General Description
- Voltage-Mode Operation with Current Sharing
- Operate with 4.5V~13.2V Supply Voltage
- Support Single and Two-Phase Operations
- +2% Reference Voltage Accuracy Over Temperature
- Loss-Less Inductor DCR Current Sensing
- Adjustable Over Current Protection use DCR Current Sensing
- Programmable PWM Switching Frequency from 100kHz to 800kHz
- Dynamic Output Voltage Adjustment
- Adjustable Soft-start
- QFN4x4-24 Package
- Halogen and Lead Free Available (RoHS Compliant)
Applications
- VGA
- Mother Board The APW8700, two-phase PWM control IC, provides a precision voltage regulation system for advanced graphic card and motherboard applications. The integration of power MOSFET drivers into the controller IC and reduces the number of external parts for a cost and space saving power management solution. The APW8700 uses a voltage-mode PWM architecture, operating with adjust frequency from 100kHz to 800kHz. The device uses the voltage across the DCRs of the in- ductors for current sensing achieves high efficiency. The device integrates adjustable load line voltage position- ing (droop) and adopts low side RDS_ON for channel-cur- rent balance. The automatic phase reduction and over-current protec- tion are accomplished through continuous inductor DCRs current sensing. The APW8700 also implement a one-bit VID control op- eration in which the feedback voltage is regulated and tracks external input reference voltage. This controller protection features include over- temperature(OTP), over-voltage(OVP), under-voltage (UVP) and over-current protections (OCP). The device also provides a power-on-reset function and a programmable soft-start to prevent wrong operation and limit the input surge current during power-on or start-up. The APW8700 is available in QFN4x4-24 packages. Simplified Application Circuit FB REFIN RT/EN COMP PSI SS VIN VOUT UGATE1 UGATE2 LGATE2 LGATE1 VREF ON OFF
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw2 Ordering and Marking Information Pin Configuration Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol Parameter Rating Unit VVCC Input Supply Voltage (VVCC to GND) -0.3 ~ 16 V VPVCC Gate Driver Supply Voltage (VPVCC to GND) -0.3 ~ VVCC+1 V BOOT1/2 to PHASE1/2 Voltage -0.3 ~ 16 V BOOT1/2 to GND Voltage -0.3 ~ 30 V > 200ns -0.3 ~ VBOOT1/2+0.3 V UGATE1/2 to PHASE1/2 Voltage < 200ns -5 ~ VBOOT1/2+5 V > 200ns -0.3 ~ VVCC+0.3 V VLGATE1/2 LGATE1/2 to GND Voltage < 200ns -5 ~ VVCC+5 V > 200ns -0.3 ~ 16 V VPHASE1/2 PHASE1/2 to GND Voltage < 200ns -10 ~ 30 V REFIN, VREF, RT/EN, IOFS, COMP, FB, EAP, SS, CSP, CSN, PSI, VID, RSET to AGND Voltage -0.3 ~ 7 V AGND to GND -0.3 +0.3 V PD Power Dissipation 2.5 W APW8700 Handling Code Temperature Range Package Code Package Code QA : QFN4x4-24 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW8700 QA : Assembly Material XXXXX - Date CodeAPW8700 XXXXX REFIN VREF RT/EN IOFS COMP AGND EAP CSP VCC PVCC LGATE1 PHASE1 UGATE1 FB BOOT1 (Exposed Pad) GND 23 22 21 20 1924 8 9 10 11 127 QFN4x4-24 Top View SS CSN PSI LGATE2 PHASE2 RSET VID BOOT2 UGATE2 APW8700
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw3 Absolute Maximum Ratings (Cont.) (Note 1) Symbol Parameter Rating Unit TJ Maximum Junction Temperature 150 oC TSTG Storage Temperature -65 ~ 150 oC TSDR Maximum Lead Soldering Temperature (10 Seconds) 260 oC Thermal Characteristics Symbol Parameter Typical Value Unit θ JA Junction-to-Ambient Resistance in free air (Note 2) QFN4x4-24 41 oC/W θ JC Junction-to-Case Resistance QFN4x4-24 9 oC/W Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note 2: θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. Symbol Parameter Range Unit VVCC VCC Supply Voltage (VVCC to GND) 4.5 ~ 13.2 V VOUT VOUT to GND 0.6 ~ 5.5 V VIN Converter Input Voltage 2 ~ 13.2 V FOSC Oscillator Frequency 100 ~ 800 kHz IOUT Converter Output Current 0 ~ 60 A TA Ambient Temperature -40 ~ 85 oC TJ Junction Temperature -40 ~ 125 oC Recommended Operating Conditions (Note 3) Note 3: Refer to the application circuit for further information.
Electrical Characteristics
Symbol Parameter Test Conditions Min. Typ. Max. Unit SUPPLY CURRENT VCC Supply Voltage Range 4.5 - 13.2 V IDD_SD No switching, RT/EN=GND - 4 5 mA IDD Input DC Bias Current UGATE1/2, LGATE1/2 open, switching - 5 7 mA VPVCC Regulated Supply Voltage RT/EN=GND, IPVCC=0mA 8 9 10 V POR Threshold of VCC 3.8 4.1 4.4 V POR Hysteresis 0.3 0.5 0.6 V POR Threshold of PVCC 3.8 4.1 4.4 V POR Hysteresis 0.3 0.5 0.6 V Refer to figure 1 in the “Typical Application Circuits”. These specifications apply over V VCC = 12V, TA= 25oC, unless otherwise noted.
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw4 Electrical Characteristics (Cont.) APW8700 Symbol Parameter Test Conditions Min. Typ. Max. Unit CHIP ENABLE/FREQUENCY SETTING IRT/EN RT/EN Source Current RT/EN=GND - - 120 µA RT/EN Shutdown Threshold 0.45 0.5 0.55 V Enable Debounce time RT/EN high debounce - 200 - µs VRT/EN RT/EN Voltage RRT/ENB=33kΩ - 1 - V Switching Frequency Setting Range 100 - 800 kHz FOSC Free Run Switching Frequency RRT/EN=33kΩ 255 300 345 kHz ΔFOSC Switching Frequency Accuracy FOSC=200kHz~500kHz -15 - 15 % SOFT-START ISS Soft-start Current During Soft-start - 20 - µA SS Source/Sink Current Capability After Soft-start - 200 - µA OSCILLATOR Maximum Duty Cycle - 85 - % Minmum Duty Cycle - 0 - % ΔVOSC Ramp Amplitude VVCC=12V - 1.5 - V POWER SAVING MODE VPSI Threshold Voltage to Enter Dual Phase VPSI Rising 0.55 0.6 0.65 V ΔVPSI Hysteresis to Enter Single Phase VPSI Falling - 0.2 - V 2 Phase to single phase debounce Continuously - 0.2 - ms REFERENCE VOLTAGE VREF Reference Voltage Accuracy IREF=100µA, TJ= -20oC ~ 70oC 1.98 2.00 2.02 V VREF Maximum Output Current VREF=GND 20 - - mA ΔVREF Reference Voltage Load Regulation IREF=0~2mA -5 - 5 mV VREFIN-VFB, VREFIN=0.8V~2V, RDRP=0Ω -5 - 5 mV VFB Output Voltage Accuracy VFB operating range 0.2 - VREF V ERROR AMPLIFIER Open-Loop DC Gain (Note 4) RL = 10kΩ , CL =10pF - 80 - V/V Open-Loop Bandwidth (Note 4) RL = 10kΩ , CL =10pF - 20 - MHz Slew Rate (Note 4) RL = 10kΩ , CL =10pF - 8 - V/µs FB Input Leakage Current VFB=1V - 0.1 0.5 µA COMP High Voltage RL = 10kΩ , CL =10pF - 4.8 - V/µs VCOMP COMP Low Voltage RL = 10kΩ , CL =10pF - 0.2 - µA Maximum COMP Source Current VCOMP=2V - 2 - mA ICOMP Maximum COMP Sink Current VCOMP=2V - 2 - mA Refer to figure 1 in the “Typical Application Circuits”. These specifications apply over V VCC = 12V, TA= 25oC, unless otherwise noted.
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw5 Electrical Characteristics (Cont.) APW8700 Symbol Parameter Test Conditions Min. Typ. Max. Unit TOTAL CURRENT SENSE ICSN_MAX Maximum Sourcing Current 100 - - µA GM Amplifier Offset -5 - 5 mV ICSN_OCP Over-Current Protection Threshold Level 55 60 65 µA Droop Accuracy IDRP/ICSN 90 100 110 % PSI Accuracy IPSI/ICSN 90 100 110 % PHASE CURRENT SENSE gm Trans-conductance - 1.0 - mA/V 100kΩ from IOFS to VREF 1.425 1.5 1.575 V VIOFS IOFS Voltage 100kΩ from IOFS to GND 0.475 0.5 0.525 V VID CONTROL INPUT VIH Logic High Threshold Level 1.2 - - V VIL Logic Low Threshold Level - - 0.4 V RRSET On Resistance of RSET MOSFET VID=High - 20 - Ω IRSET Leakage Current of RSET Pin VRSET=2V, VID=GND - - 0.1 µA Gate Driver RUG_SRC Upper Side Gate Sourcing IUGATE=100mA Sourcing - 2 4 Ω RUG_SNK Upper Side Gate Sinking IUGATE=100mA Sinking - 1.5 3 Ω RLG_SRC Low Side Gate Sourcing ILGATE=100mA Sourcing - 2 4 Ω RLG_SNK Low Side Gate Sinking ILGATE=100mA Sinking - 1 2 Ω TDT Dead-time - 30 - ns PROTECTION Over Voltage Protection (OVP) VFB/VEAP 125 130 135 % Over Voltage Hysteresis - 20 - % Under Voltage Protection (UVP) VFB/VEAP 45 50 55 % Over Current Protection (OCP) ICSN 55 60 65 µA Over Temperature Protection (OTP) - 150 - ο C Over Temperature Hysteresis - 20 - ο C Refer to figure 1 in the “Typical Application Circuits”. These specifications apply over V VCC = 12V, TA= 25oC, unless otherwise noted. Note 4: Guarantee by design, not production test
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw6 Pin Description PIN NAME FUNCTION 1 REFIN External Reference Input. This is input pin of external reference voltage. Connect a voltage divider from VREF to REFIN to AGND to set the reference voltage. 2 VREF Reference Voltage Output. This is the output pin of high precision 2V reference voltage. Bypass this pin with a 1µF ceramic capacitor to AGND. 3 RT/EN Operation Frequency Setting. Connecting a resistor between this pin and AGND to set the operation frequency. Pull this pin to ground to shut down the APW8700. 4 IOFS Current Balance Adjustment. Connect a resistor from this pin to VREF or GND to adjust the current sharing. 5 COMP Error Amplifier Output. Use this pin in combination with the FB pin to compensate the voltage-control feedback loop of the converter. 6 FB Feedback Voltage. This pin is the inverting input to the error amplifier. Use this pin in combination with the COMP pin to compensate the voltage control feedback loop of the converter. 7 AGND Analog Ground. Connect this pin to the GND pin where the output voltage is to be regulated. 8 EAP Non-Inverting Input of Error Amplifier. Connect a resistor to SS pin to set the droop slope. 9 SS Soft Start Output. Connect a capacitor to GND to set the soft start interval. 10 CSN Inverting Input of Current Sensing Amplifier. 11 CSP Non-Inverting Input of Current Sensing Amplifier.
12 PSI
Power Saving Indicator. Connect a resistor from PSI to AGND to set the power saving mode threshold current level. Connect this pin to VREF for always two phases operation. Short this pin to ground for always single-phase operation. Don’t left this pin floating.
13 BOOT1
Bootstrap Supply for the floating high-side gate driver of channel 1. Connect the Bootstrap capacitor between the BOOT1 pin and the PHASE1 pin to form a bootstrap circuit. The bootstrap capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT range from 0.1µF to 1µF. Ensure that CBOOT is placed near the IC.
14 UGATE1
Upper Gate Driver Output for channel 1. Connect this pin to the gate of high-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off.
15 PHASE1
Switch Node for Channel 1. Connect this pin to the source of high-side MOSFET and the drain of the low-side MOSFET. This pin is used as sink for UGATE1 driver. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off.
16 LGATE1
Low-side Gate Driver Output for Channel 1. Connect this pin to the gate of low-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the low-side MOSFET has turned off.
17 PVCC
Supply Voltage for Gate Driver. This pin is the output of internal 9V LDO. It provides current for gate drives. Bypass this pin with a minimum 1µF ceramic capacitor. If VCC below 7V, connect this pin to VCC is recommended. 18 VCC Supply Voltage. This pin provides current for internal control circuit and 9V LDO. Bypass this pin with a minimum 1µF ceramic capacitor next to the IC.
19 LGATE2
Low-side Gate Driver Output for Channel 2. Connect this pin to the gate of low-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the low-side MOSFET has turned off.
20 PHASE2
Switch Node for Channel 2. Connect this pin to the source of high-side MOSFET and the drain of the low-side MOSFET. This pin is used as sink for UGATE2 driver. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off.
21 UGATE2
Upper Gate Driver Output for channel 2. Connect this pin to the gate of high-side MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET has turned off.
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw7 Pin Description(Cont.) PIN NAME FUNCTION
22 BOOT2
Bootstrap Supply for the floating high-side gate driver of channel 2. Connect the Bootstrap capacitor between the BOOT2 pin and the PHASE2 pin to form a bootstrap circuit. The bootstrap capacitor provides the charge to turn on the high-side MOSFET. Typical values for CBOOT range from 0.1µF to 1µF. Ensure that CBOOT is placed near the IC. 23 VID VID Input. This pin is used to adjust reference voltage. Logic high turns on the internal MOSFET connected to RSET pin. 24 RSET Reference Voltage Setting. This pin is an open drain output that is pulled low when VID = high. Connect a resistor from this pin to REFIN pin to set the reference voltage. Exposed Pad GND Power Ground. Tie this pad to the ground island/plane through the lowest impedance connection available.
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw8 Typical Operating Characteristics Reference Voltage vs. Junction Temperature UGATE Driver On Resistance vs. PVCC Voltage LGATE Driver On Resistance vs. Supply Voltage PVCC Voltage vs. Supply Voltage Refer to the “Typical Application Circuits”, VIN=12V, VOUT=1.05V, TA=25oC unless otherwise specified Reference Voltage vs. Supply Voltage Junction Temperature, TJ(oC) 1.980 1.985 1.990 1.995 2.000 2.005 2.010 2.015 2.020 -40 -20 0 20 40 60 80 100 120 140 160 Reference Voltage, VREF(V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 4 5 6 7 8 9 PVCC Voltage, VPVCC (V) U G A TE Driver On Resistance (Ω ) UGATE Source UGATE Sink LG A TE Driver On Resistance (Ω ) Supply Voltage, VVCC (V) 4 5 6 7 8 9 10 11 12 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LGATE Sink LGATE Source PVCC Voltage, VPVCC(V) Supply Voltage, VVCC (V) 4 5 6 7 8 9 10 11 12 13 14 IPVCC = 10mA 4 5 6 7 8 9 10 11 12 13 14 1.95 1.96 1.97 1.98 1.99 2.01 2.02 2.03 2.04 2.05 Reference Voltage, VREF(V) Supply Voltage, VVCC (V)
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw9 Operating Waveforms Enable Shutdown Power ON Power OFF Time: 500µs/Div Time: 500µs/Div Time: 500µs/Div Time: 50µs/Div VRT, 1V/Div, DC VPHASE1, 5V/Div, DC VSS , 0.5V/Div, DC VOUT, 0.5V/Div, DC VRT, 1V/Div, DC VPHASE1, 10V/Div, DC VSS, 0.5V/Div, DC VOUT, 0.5V/Div, DC VRT, 1V/Div, DC VPHASE1, 5V/Div, DC VSS, 0.5V/Div, DC VOUT, 0.5V/Div, DC VRT , 1V/Div, DC VPHASE1, 10V/Div, DC VSS , 0.5V/Div, DC VOUT, 0.5V/Div, DC
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw10 Operating Waveforms PSI OVP OCP Time: 50µs/Div Time: 10µs/Div Time: 20µs/Div VPSI, 1V/Div, DC VPHASE1, 10V/Div, DC VPHASE2, 10V/Div, DC VFB, 1V/Div, DC VUGATE1, 10V/Div, DC VLGATE1, 10V/Div, DC VSS, 1V/Div, DC VOUT, 1V/Div, DC IL1, 10A/Div, DC IL2, 10A/Div, DC IL1+IL2, 20A/Div, DC 3+4
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw11 Block Diagram EAP PVCC PHASE1 BOOT1 UGATE1 LGATE1 VCC PVCC PHASE2 BOOT2 UGATE2 LGATE2 VCC Logic Control FB VOSC1 VOSC2 COMP SS REFIN Logic Control PSI CSN CSP RSET VREF VID Internal Regulator VCC PVCC Power Saving Setting Power On Reset GND RT/EN 0.5V Enable Internal Regulator Error Amplifier Current Limit Buffer IOFS Over Current Protection Gm Amplifier Current Balance AGND IDRP Oscillator
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw12 Typical Application Circuit FB REFIN RT /EN COMP PSI SS VIN = 12V VOUT UGATE 1 UGATE 2 LGATE 2 LGATE 1 VREF CSP AGND CSN PHASE 1 PHASE 2 BOOT 1 BOOT 2 (option) PHASE 2 PHASE 1 EAP RSET VID VCC GND IOFS ON OFF 1k 1µF (option) 0.8µH 1k 8.1k 47nF 40k33k 680 0.27k220nF 10nF 100nF 12R APM 3106 APM 3109 APM 3106 APM 3109 0.1µF 0.1µF 0.1µF NC 1µF 0.8µH 820µFx3 10µFx2 10µFx2 10µFx2 270µFx2 10k 2N7002 PVCC 1µF VOUT VREF (option)
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw15 Function Description (Cont.) Over Current Protection (OCP) The APW8700 feature an over current protection adopt current sensing. When ICSN exceed 60µA at operation, the over current occurs. In over-current protection, the IC shuts off the converter. The ICSN can be describe as: The equations of the sensing network are: )1DCR1sL()s(I)s(V 1L1L +×= In some high current applications, a requirement on pre- cisely controlled output impedance is imposed. This de- pendence of output voltage on load current is often termed droop regulation. As shown in figure 4, the droop control block generates a voltage through external resistor R DRP and then set the droop voltage. The droop voltage, V DRP, is proportional to the total current in two channels. As shown in the following equation: Droop Setting SS SS 1LC CsR1 )1DCR1sL()s(I CsR1 1)s(V)s(V + +×=+×= Take 1DCR 1LCR SS = If the above is true, the voltage across the capacitor C S equal to voltage drop across the inductor DCR1, and the voltage VC is proportional to the inductor current I L1. 1LC I1DCRV ×= CSN CSN C CSN R 1DCRI R VI ×== where IL1 is the inductor current of phase 1 DCR1 is the inductor resistance of phase 1 Due to the APW8700 implement current balance circuit. At two phase operation, the IL1 equal half of output current, IOUT. CSN OUT CSN 1DCRII × CSN OUT CSN C CSN 1DCRI R VI × ×== The APW8700 initial a soft-start process until recycle POR or EN/RT. The APW8700 implements automatic phase reduction that turns off phase 2 at light load condition and reduces both switching and conduction losses. The automatic phase reduction maintains high power conversion effi- ciency over the output current range. The output current is sensed and mirrored to PSI pin as: Automatic Phase Reduction CSN OUT CSNPSI 1DCRIII × ×== The IPSI creates a voltage VPSI as: CSN PSIOUT PSIPSIPSI R1DCRIIRV × ××=×= The APW8700 operates at dual phase if V PSI exceeds 0.6V and at single phase at V PSI below 0.4V. There is a 200mV hystersis at the phase change threshold. There is a 0.2ms delay when entering single phase operation and no time delay when entering dual phase operation. When operating single phase, both UGATE2 and LGATE2 are turned off. DRPDRPSSFB RIVV ×−= where IDRP is the droop current that mirrored from I CSN. The output voltage also can be describe as: CSN DRPOUT SSDRPDRPSSFB R1DCRIVRIVV ×
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw16 Function Description (Cont.) The APW8700 integrated IOFS allows the offset current to adjust phase current. The IOFS pin voltage is nominal 0.5V when connecting a resistor to GND and 1.5V when connecting a resistor to VREF. Connecting a resistor from IOFS pin to GND generate a current source as: IOFS= 0.5V/RIOFS This current is add to phase 1 current signal ISEN1 for cur- rent balance. Consequently, phase 2 will share more percentage of output current. Connecting a resistor from IOFS pin to VREF generates a current source as: IOFS= (2V-1.5V) /RIOFS This current is add to phase 2 current signal ISEN2 for cur- rent balance. Consequently, phase 1 will share more percentage of output current. Offset Current Adjust The over-temperature circuit limits the junction tempera- ture of the APW8700. When the junction temperature ex- ceeds 150o C, a thermal sensor pulls UGTAEx and LGATEx low, allowing the devices to cool. The thermal sensor allows the converters to start a soft-start process and regulates the output voltage again after the junction tem- perature cools by 20o C. The OTP is designed with a 20o C hysteresis to lower the average Junction Temperature (TJ) during continuous thermal overload conditions in- creasing the lifetime of the device. Over-Temperature Protection (OTP) The over-voltage protection (OVP) circuit monitors the FB (VFB) voltage to prevent the output from over-voltage. When the VFB rises to 130% of the EAP voltage (VEAP), the APW8700 turns off high-side and turn on low-side MOSFETs to sink output voltage (VOUT). As soon as the VFB falls below 110% of VEAP , the OVP comparator is disengaged. The chip will restore its normal operation. OVP The under-voltage protection circuit monitors the voltage on FB (VFB) by Under-Voltage (UV) comparator to protect the PWM converter against short-circuit conditions. When the VFB falls below the falling UVP threshold (50% VEAP), a fault signal is generated and the device turns off high- side and low-side MOSFETs. The converter shuts down and the output is latched to be floating. The APW8700 will initials a soft-start process until re-cycle RT/EN or VCC UVP
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw19 Application Information (Cont.) Output Inductor Selection (Cont.) IN OUT V VD = Where FSW is the switching frequency of the regulator. Although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff exists between the inductor’s ripple current and the regu- lator load transient response time. A smaller inductor will give the regulator a faster load tran- sient response at the expense of higher ripple current. Increasing the switching frequency (FSW) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the power dissipa- tion of the converter. The maximum ripple current oc- curs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This results in a larger out- put ripple voltage. For two-phase converter, the inductor value (L) determines the sum of the two inductor ripple currents, Δ IP-P, and af- fects the load transient reponse. Higher inductor value reduces the output capacitors’ ripple current and induces lower output ripple voltage. The ripple current can be approxminated by: Output Capacitor Selection Output voltage ripple and the transient volt age de- viation are factors that have to be taken into con- sideration when selecting output capacitor s. Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore , selecting high performance low ESR capacitors is recommended for switching regulator applications. In addition to high fre- quency noise related to MOSFET turn-on and turn-off, the output voltage ripple includes the capacitance voltage drop Δ VCOUT and ESR voltage drop Δ VESR caused by the AC peak-to-peak sum of the inductor’s current. The ripple voltage of output capacitors can be represented by: These two components constitute a large portion of the total output voltage ripple. In some applications, multiple capacitors have to be paralleled to achieve the desired ESR value. If the output of the converter has to support another load with high pulsating current, more capaci- tors are needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors are also must be considered. To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing the voltage excursion during load step change. For getting same load transient response, the output capacitance of two-phase converter only needs around half of output capacitance of single-phase converter. Another aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the rated RMS current specified on the ca- pacitors in order to prevent the capacitor from over- heating. Input Capacitor Selection Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge cur- rent needed each time high-side MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of high-side MOSFET and the source of low-side MOSFET. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and cur- rent ratings above the maximum input voltage and larg- est RMS current required by the circuit. The capacitor volt- age rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. For two-phase converter, the IN OUT SW OUTIN P-P V V LF 2V-VI ××=Δ ESR PPESR SWOUT PP COUT RIV FC8 IV Δ=Δ Δ=Δ
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw20 Application Information (Cont.) For a through hole design, several electrolytic capacitors may be needed. For surface mount design, solid tan- talum capacitors can be used, but caution must be exer- cised with regard to the capacitor surge current rating. Input Capacitor Selection (Cont.) RMS current of the bulk input capacitor is roughly calcu- lated as the following equation : MOSFET Selection The APW8700 requires two N-Channel power MOSFETs on each phase. These should be selected based upon RDS(ON), gate supply requirements, and thermal manage- ment requirements. In high-current applications, the MOSFET power dissipation, package selection, and heatsink are the domi- nant design factors. The power dissipation includes two loss components, conduction loss, and switching loss. The conduction losses are the largest component of power dissipation for both the high-side and the low- side MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equa- tions below). Only the high-side MOSFET has switching losses since the low-side MOSFETs body diode or an external Schottky rectifier across the lower MOSFET clamps the switching node before the synchronous rec- tifier turns on. These equations assume linear voltage- current transitions and do not adequately model power loss due the reverse-recovery of the low-side MOSFET body diode. The gate-charge losses are dissipated by the APW8700 and don’t heat the MOSFETs. However, large gate-charge increases the switching interval, t SW which increases the high-side MOSFET switching losses. Ensure that all MOSFETs are within their maxi- mum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. For the high-side and low-side MOSFETs, the losses are approximately given by the following equations: Phigh-side = IOUT 2 (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW Plow-side = IOUT 2 (1+ TC)(RDS(ON))(1-D) where IOUT is the load current TC is the temperature dependency of R DS(ON) FSW is the switching frequency tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction losses while the high-side MOSFET include s an additional transi - tion loss. T he switching interval, t SW, is the function of Layout Consideration In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at higher frequency, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed circuit traces should minimize interconnect- ing impedances and the magnitude of voltage spike. Besides, signal and power grounds are to be kept sepa- rating and finally combined using ground plane construc- tion or single point grounding. The best tie-point between the signal ground and the power ground is at the nega- tive side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not recommended. Figure 11. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: the reverse transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the R DS(ON) and can be extracted from the “R DS(ON) vs. Temperature” curve of the power MOSFET. 2D)-(12D2 I I OUT RMS ⋅×=
Copyright ANPEC Electronics Corp. drain of the low-side MOSFET as close as possible. can get better heat sinking. from the noisy switching nodes. drain of the high-side MOSFET as close as possible). output capacitors and low-side MOSFET. (UGATEx, LGATEx, BOOTx, and PHASEx). lel with theses traces on any layer. Figure 11. Layout Guidelines
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw22 QFN4x4-24 AD E Pin 1 Corner E2L b e SYMBOL MIN. MAX. 1.00 0.00 0.18 0.30 2.50 2.80 0.05 2.50 A b D E e L MILLIMETERS A3 0.20 REF QFN4x4-24 0.35 0.45 2.80
0.008 REF
MIN. MAX. INCHES 0.039 0.000 0.008 0.012 0.098 0.110 0.098 0.014 0.018 0.80 0.110 0.031 0.002 4.00 BSC 0.157 BSC 4.00 BSC 0.157 BSC 0.50 BSC 0.020 BSC
Package Information
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw23 Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 QFN4x4-24 (mm) Carrier Tape & Reel Dimensions Devices Per Unit Package Type Unit Quantity QFN4x4-24 Tape & Reel 3000 H A d A AB W F T P0OD0 B SECTION B-B SECTION A-A OD1
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw24 Taping Direction Information QFN4x4-24 USER DIRECTION OF FEED Classification Profile
Copyright ANPEC Electronics Corp. (Tsmax to TP) 3 °C/second max. 3°C/second max. Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. Time 25°C to peak temperature 6 minutes max. 8 minutes max.
- Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 2. Pb-free Process – Classification Temperatures (Tc) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2011 APW8700 www.anpec.com.tw26 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838