APW7046 ANPEC | Alldatasheet
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/G43/G6F/G70/G79/G72/G69/G67/G68/G74/G20 /G41/G4E/G50/G45/G43/G20/G45/G6C/G65/G63/G74/G72/G6F/G6E/G69/G63/G73/G20/G43/G6F/G72/G70/G2E /G52/G65/G76/G2E/G41/G2E/G32/G20/G2D/G20/G4D/G61/G72/G2E/G2C/G20/G32/G30/G30/G32 /G41/G50/G57/G37/G30/G34/G36 /G77/G77/G77/G2E/G61/G6E/G70/G65/G63/G2E/G63/G6F/G6D/G2E/G74/G77/G31 /G41/G4E/G50/G45/G43/G20/G72/G65/G73/G65/G72/G76/G65/G73/G20/G74/G68/G65/G20/G72/G69/G67/G68/G74/G20/G74/G6F/G20/G6D/G61/G6B/G65/G20/G63/G68/G61/G6E/G67/G65/G73/G20/G74/G6F/G20/G69/G6D/G70/G72/G6F/G76/G65/G20/G72/G65/G6C/G69/G61/G62/G69/G6C/G69/G74/G79/G20/G6F/G72/G20/G6D/G61/G6E/G75/G66/G61/G63/G74/G75/G72/G61/G62/G69/G6C/G69/G74/G79/G20/G77/G69/G74/G68/G6F/G75/G74/G20/G6E/G6F/G74/G69/G63/G65/G2C/G20/G61/G6E/G64/G20/G61/G64/G76/G69/G73/G65 /G63/G75/G73/G74/G6F/G6D/G65/G72/G73/G20/G74/G6F/G20/G6F/G62/G74/G61/G69/G6E/G20/G74/G68/G65/G20/G6C/G61/G74/G65/G73/G74/G20/G76/G65/G72/G73/G69/G6F/G6E/G20/G6F/G66/G20/G72/G65/G6C/G65/G76/G61/G6E/G74/G20/G69/G6E/G66/G6F/G72/G6D/G61/G74/G69/G6F/G6E/G20/G74/G6F/G20/G76/G65/G72/G69/G66/G79/G20/G62/G65/G66/G6F/G72/G65/G20/G70/G6C/G61/G63/G69/G6E/G67/G20/G6F/G72/G64/G65/G72/G73/G2E /G46/G65/G61/G74/G75/G72/G65/G73
- •••• 3 Regulated Voltages are provided − Standard Buck Converter for VCORE (1.15~1.50V) − Standard Buck Converter for VMEM (2.40~3.15V) −Linear Controller with SOURCE-SINK Regul- ation for VTT(1.25V)
- •••• Simple Single-Loop Control Design − Voltage-Mode PWM Control
- •••• Excellent Output Voltage Regulation − VCORE Output : ±1% Over Temperature − VMEM Output : ±1.5% Over Temperature − VTT Output : 1/2 VIN ±25mV Over Tempera- ture Min. VIN = 1.7V
- •••• Fast Transient Response − Built-in Feedback Compensation − Full 0% to 100% Duty Ratio
- •••• Over-Voltage and Over-Current Fault Monitor
- •••• Constant Frequency Operation(200kHz)
- •••• 24 pins, SOIC Package /G41/G70/G70/G6C/G69/G63/G61/G74/G69/G6F/G6E/G73
- •••• M/B DDR Power Regulation
- •••• AGP/PCI Graphics Power Regulation /G47/G65/G6E/G65/G72/G61/G6C/G20/G44/G65/G73/G63/G72/G69/G70/G74/G69/G6F/G6E The APW7046 provides the power controls and protec- tions for three output voltages on AGP/PCI Graphic Card applications. It integrates two PWM controllers , one SOURCE-SINK linear controller, as well as the monitor and protection functions into a single package. One PWM converter (PWM1) supplies the VCORE(1.5V) for the GPU with a standard buck converter. The other standard buck converter (PWM2) regulates the VMEM(2.5V) for the pow- er of DDR memory. The SOURCE-SINK linear controller control two external MOSFETs to be a linear regulator with the capability of sourcing and sinking current. It reg- ulates the VTT (1.25V) power for DDR Termination voltage. Additional built-in over-voltage protection (OVP) will be started when the VCORE or VMEM output is above 115% of each DAC setting (VCORE and VMEM ). OVP function will shutdown the all output voltages until re-powering on the IC. For each PWM converter, the over-current function monitors the output current by sensing the voltage drop across the MOSFET‘s r DS(ON) , eliminating the need for a current sensing resistor. Dual Advanced PWM and Source-Sink Linear Controller /G50/G69/G6E/G20/G44/G65/G73/G63/G72/G69/G70/G74/G69/G6F/G6E VCC UGATE1 PHASE1 SS SD SOURCE SINK FB VIN OCSET1 VSEN1 GND BOOT UGATE2 PHASE2 PGND MEM2 MEM1 MEM0 CORE2 CORE1 CORE0 OCSET2 VSEN2
Copyright ANPEC Electronics Corp. Rev. A. /G52/G65/G76/G2E/G41/G2E/G32 - Mar., 2002 /G41/G50/G57/G37/G30/G34/G36 /G77/G77/G77/G2E/G61/G6E/G70/G65/G63/G2E/G63/G6F/G6D/G2E/G74/G77/G32 APW 7046 Voltage Code A : VCORE(1.15~1.50V) VMEM(2.40~2.75V) B : VCORE(1.15~1.50V) VMEM(2.80~3.15V) Package Code K : SOP-24 Temp. Range C : 0 to 70 ° C Handling Code TU : Tube TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device Handling Code Temp. Range Package Code Voltage Code APW 7046K : APW7046 XXXXX XXXXX - Date Code Lead Free Code /G4F/G72/G64/G65/G72/G69/G6E/G67/G20/G20/G61/G6E/G64/G20/G4D/G61/G72/G6B/G69/G6E/G67/G20/G49/G6E/G66/G6F/G72/G6D/G61/G74/G69/G6F/G6E /G42/G6C/G6F/G63/G6B/G20/G44/G69/G61/G67/G72/G61/G6D /G41/G62/G73/G6F/G6C/G75/G74/G65/G20/G4D/G61/G78/G69/G6D/G75/G6D/G20/G52/G61/G74/G69/G6E/G67/G73 Symbol Parameter Rating Unit VCC Supply Voltage 15 V VI , VO Input , Output or I/O Voltage GND -0.3 V to V CC +0.3 V TA Operating Ambient Temperature Range 0 to 70 °C TJ Junction Temperature Range 0 to 125 °C TSTG Storage Temperature Range -65 to +150 °C TS Soldering Temperature 300 ,10 seconds °C VCC Power On Reset Ther mal Protecti on S oft- S tart and Faul t Logi c Osci l l ator Gat e Control Gat e Control TTL D/ A Conver t er TTL D/ A Conver t er SD SOURCE FB SI NK VCC SS OCSET1 BOOT UGATE1 PHASE1 VSEN1 CORE0 CORE1 CORE2 VSEN2 MEM0 MEM1 MEM2 UGATE2 PGND PHASE2 GND OCSET2VI N 28 µ A 4. 5V I NHI BI T OC2 PW M2 I NHI BI T EA2 EA1 PW M1 I NHI BI T 200 µ A OC1 BOOT OVP2 115% V MEM 115% Vcor eOVP1 50% 200uA B uffer Resi stor Di vi der V CORE V MEM
Copyright ANPEC Electronics Corp. Rev. A. /G52/G65/G76/G2E/G41/G2E/G32 - Mar., 2002 /G41/G50/G57/G37/G30/G34/G36 /G77/G77/G77/G2E/G61/G6E/G70/G65/G63/G2E/G63/G6F/G6D/G2E/G74/G77/G33 /G45/G6C/G65/G63/G74/G72/G69/G63/G61/G6C/G20/G43/G68/G61/G72/G61/G63/G74/G65/G72/G69/G73/G74/G69/G63/G73 /G54/G68/G65/G72/G6D/G61/G6C/G20/G43/G68/G61/G72/G61/G63/G74/G65/G72/G69/G73/G74/G69/G63/G73 Symbol Parameter Value Unit R JA Thermal Resistance in Free Air SOIC SOIC (with 3in 2 of Copper) °C/W Unless otherwise specified, these specifications apply over VCC =VBOOT =12V and TA=0~70°C. Typical values refer to TA=25°C. APW7046 Symbol Parameter Test Conditions Min. Typ. Max. Unit Supply Current ICC Nominal Supply Current SD=0V, UGATE1,UGATE2 , SOURCE, and SINK Open 8 ICCSD Shutdown Supply Current SD=5V 2.7 mA Power-on Reset Rising VCC Threshold Vocset=3V 4.2 4.6 V Falling VCC Threshold Vocset=3V 3.6 V SD Input High Voltage 2.0 V SD Input Low Voltage 0.8 V Oscillator FOSC Free Running Frequency 185 200 215 kHz ∆ V OSC Ramp Amplitude 1.9 V PWM Controller Reference Voltage V CORE PWM1 Reference Voltage Accuracy -1 +1 % CORE0-CORE2 Input High Voltage 2.0 V CORE0-CORE2 Input Low Voltage 0.8 V V MEM PWM2 Reference Voltage Accuracy -1.5 +1.5 % MEM0-MEM2 Input High Voltage 2.0 V MEM0-MEM2 Input Low Voltage 0.8 V SOURCE-SINK Linear Controller V FB FB Regulation Voltage Regulator Sourcing or Sinking Current 0.5VIN V V FB accuracy -25 +25 mV Max. SOURCE Pin Drive Current /GA1/GD30.8 mA Max. SINK Pin Drive Current /GA1/GD30.8 mA
Copyright ANPEC Electronics Corp. Rev. A. /G52/G65/G76/G2E/G41/G2E/G32 - Mar., 2002 /G41/G50/G57/G37/G30/G34/G36 /G77/G77/G77/G2E/G61/G6E/G70/G65/G63/G2E/G63/G6F/G6D/G2E/G74/G77/G34 /G46/G75/G6E/G63/G74/G69/G6F/G6E/G61/G6C/G20/G50/G69/G6E/G20/G44/G65/G73/G63/G72/G69/G70/G74/G69/G6F/G6E VCC (Pin 1) Provide a +12V bias supply for the IC to this pin. This pin also provides the gate bias charge for the MOSFETs of the SOURCE-SINK regulator. The volt- age at this pin is monitored for Power-On Reset (POR) purposes. UGATE1 (Pin 2) Connect this pin to the MOSFET gate of the PWM1 converter. This pin provides the gate drive for the MOSFET. PHASE1 (Pin 3) Connect this pin to the PWM1 converter’s MOSFET source.This pin is used to monitor the voltage drop across the MOSFET for over-current protection. SS (Pin 4) Connect a capacitor from this pin to ground.This capacitor, along with an internal 28uA current source, APW7046 Symbol Parameter Test Conditions Min. Typ. Max. Unit IVIN VIN Input Bias Current VIN=2.5V 2 uA PWM Controllers Gate Drivers IUGATE UGATE1,2 Source VCC =V BOOT =12V, VUGATE1,2 =6V 0.74 A R GATE UGATE Sink V CC =12V,VUGATE1,2 =6V 3 4 Ω Protection VSEN1,2 OVP trip point (VSEN1/V CORE and VSEN2/V MEM ) VSEN Rising 115 120 VSEN1,2 O.V. Hysteresis 2 IOCSET Ocset Current Source Vocset=3V 170 200 230 ISS Soft start Current 28 uA sets the soft-start interval of all power controls and preventing the outputs from overshoot as well as limit- ing the input current . SD (Pin 5) The pin shuts down all power outputs. A TTL compat- ible , logic level high signal applied at this pin immedi- ately discharges the soft-start capacitor,disabling all power outputs. When re-enabled, the IC undergoes a new soft-start cycle. Left open, this pin is pulled low by an internal pull-down resistor, enabling operation. SOURCE (Pin 6) Connect this pin to the upper MOSFET gate drive of the SOURCE-SINK regulator. This pin drives the up- per external MOSFET as a sourcing regulator. SINK (Pin 7) Connect this pin to the lower MOSFET gate drive of /G45/G6C/G65/G63/G74/G72/G69/G63/G61/G6C/G20/G43/G68/G61/G72/G61/G63/G74/G65/G72/G69/G73/G74/G69/G63/G73/G20/G28/G43/G6F/G6E/G74/G2E/G29 Unless otherwise specified, these specifications apply over VCC =VBOOT =12V and TA=0~70°C. Typical values refer to TA=25°C.
Copyright ANPEC Electronics Corp. Rev. A. /G52/G65/G76/G2E/G41/G2E/G32 - Mar., 2002 /G41/G50/G57/G37/G30/G34/G36 /G77/G77/G77/G2E/G61/G6E/G70/G65/G63/G2E/G63/G6F/G6D/G2E/G74/G77/G35 /G46/G75/G6E/G63/G74/G69/G6F/G6E/G61/G6C/G20/G50/G69/G6E/G20/G44/G65/G73/G63/G72/G69/G70/G74/G69/G6F/G6E/G20/G28/G43/G6F/G6E/G74/G2E/G29 the SOURCE-SINK regulator. This pin drives the lower external MOSFET as a sinking regulator. FB (Pin 8) Connect this pin to output of the SOURCE-SINK regulator. This pin provides the voltage feedback path for the sourcing and sinking regulators. This pin is in- ternally connected to the negative input of the SOURCE controller, and also connected to the positive input of the SINK controller. VIN (Pin 9) Connect this pin to VMEM or a fixed voltage source. Two voltages, about 0.5VIN, are generated by an inter- nal resistor divider as the reference voltages of the sourc- ing and sinking regulators. The sinking regulation volt- age is higher than the sourcing one to prevent a direct current path through the upper and lower MOSFETs. OCSET1 (Pin 10) Connect a resistor (R OCSET ) from this pin to the drain of the PWM1 converter’s MOSFET. R OCSET , an internal 200uA current source (IOCSET ), and the MOSFET’s on- resistance(rDS(ON) ) set the converter’s over-current (OC) trip point according to the following equation: IPEAK = IOCSET x ROC SET rDS( ON) An over-current trip cycles the soft-start function. The voltage at this pin is monitored for Power-On Reset (POR) purposes. VSEN1 (Pin 11) This pin is connected to the PWM1 converter’s output voltage to provide the voltage feedback path. The over- voltage protection(OVP) comparator uses this pin to monitor the output voltage for over- voltage protection GND (Pin 12) Signal ground for the IC. All voltage levels are mea- sured with respect to this pin. VSEN2 (Pin 13) This pin is connected to the PWM2 converter’s output voltage to provide the voltage feedback path. The over- voltage protection(OVP) comparator uses this pin to monitor the output voltage for over- voltage protection. OCSET2 (Pin 14) Connect a resistor (ROCSET ) from this pin to the drain of the PWM2 converter’s MOSFET. The function of this pin is similar to OCSET1(pin 10) for OC detection and POR purposes. CORE0-2 (Pin 15-17) CORE0-2 are TTL-compatible logic level input pins to the 3-bit DAC. The states of the three pins set the internal reference voltage (VCORE ) for the PWM1 con- verter and also set the OVP threshold voltage for PWM1 converter. MEM0-2 (Pin 18-20) MEM0-2 are TTL-compatible logic level input pins to the other 3-bit DAC. The states of the three pins set the internal reference voltage (V MEM ) for the PWM2 converter and also set the OVP threshold voltage for PWM2 converter. PGND (Pin 21) Connect this pin to the anode of the flywheel diodes of the two PWM converters. PHASE2 (Pin 22) Connect this pin to the PWM2 converter’s MOSFET source.This pin is used to monitor the voltage drop across the MOSFET for over-current protection.
Copyright ANPEC Electronics Corp. Rev. A. /G52/G65/G76/G2E/G41/G2E/G32 - Mar., 2002 /G41/G50/G57/G37/G30/G34/G36 /G77/G77/G77/G2E/G61/G6E/G70/G65/G63/G2E/G63/G6F/G6D/G2E/G74/G77/G36 Table 1 DAC Table APW7046 - A Pin Name CORE2 CORE1 CORE0 V CORE Voltage 0 0 0 1.15 0 0 1 1.20 0 1 0 1.25 0 1 1 1.30 1 0 0 1.35 1 0 1 1.40 1 1 0 1.45 1 1 1 1.50 Pin Name MEM2 MEM1 MEM0 V MEM Voltage 0 0 0 2.80 0 0 1 2.85 0 1 0 2.90 0 1 1 2.95 1 0 0 3.00 1 0 1 3.05 1 1 0 3.10 1 1 1 3.15 Pin Name CORE2 CORE1 CORE0 V CORE Voltage 0 0 0 1.15 0 0 1 1.20 0 1 0 1.25 0 1 1 1.30 1 0 0 1.35 1 0 1 1.40 1 1 0 1.45 1 1 1 1.50 Pin Name MEM2 MEM1 MEM0 V MEM Voltage 0 0 0 2.40 0 0 1 2.45 0 1 0 2.50 0 1 1 2.55 1 0 0 2.60 1 0 1 2.65 1 1 0 2.70 1 1 1 2.75 UGATE2 (Pin 23) Connect this pin to the MOSFET gate of the PWM2 converter. This pin provides the gate drive for the MOSFET. BOOT (Pin 24) Connect this pin to +12V. This pin provides bias volt- age to the MOSFET drivers. /G46/G75/G6E/G63/G74/G69/G6F/G6E/G61/G6C/G20/G50/G69/G6E/G20/G44/G65/G73/G63/G72/G69/G70/G74/G69/G6F/G6E APW7046 - B
Copyright ANPEC Electronics Corp. Rev. A. /G52/G65/G76/G2E/G41/G2E/G32 - Mar., 2002 /G41/G50/G57/G37/G30/G34/G36 /G77/G77/G77/G2E/G61/G6E/G70/G65/G63/G2E/G63/G6F/G6D/G2E/G74/G77/G37 /G54/G79/G70/G69/G63/G61/G6C/G20/G41/G70/G70/G6C/G69/G63/G61/G74/G69/G6F/G6E/G20/G43/G69/G72/G63/G75/G69/G74 OCSET2 UGATE2 23 PHASE2 BOOT PGND 21 VSEN2 13 MEM0 18 MEM2 SS 4 MEM1 19 EN 5SINK7 SOURCE6 FB8 CORE2 17 CORE1 16 CORE0 15 GND12 UGATE1 VIN9 VCC 1 OCSET1 PHASE1 VSEN111 +3.3V VCORE +5V VMEM VTT VMEM MEM2 MEM1 MEM0 CORE2 CORE1 CORE0 +12V 1uF 1uF 5.1 C12 10uF C13 330uF C14 10uF C15 330uF C11 200pF 1.5K 200pF 1.5K 5.1 10uF 330uF 10uF 1uH 7.8uH R10 R11 NC MBRD835L AP M 9410 AP M 9410 MBRD835L 4.7uH 330uF 330uF 330uF C10 330uF 10K 0.1uF NC AP M 3055 AP M 3055 C16 0.68uF 1uH C4, C6, C7, C8 , C10, C13, C15 : 330uF/6.3V SMD Low ESR tantalum Capacitor Standard Buck Converter (PWM1) Standard Buck Converter (PWM2) SOURCE-SINK Linear Converter APW7046 VCORE +3.3VVMEM +5V VTT /G53/G69/G6D/G70/G6C/G69/G66/G69/G65/G64/G20/G50/G6F/G77/G65/G72/G20/G53/G79/G73/G74/G65/G6D/G20/G44/G69/G61/G67/G72/G61/G6D
Copyright ANPEC Electronics Corp. Rev. A. /G52/G65/G76/G2E/G41/G2E/G32 - Mar., 2002 /G41/G50/G57/G37/G30/G34/G36 /G77/G77/G77/G2E/G61/G6E/G70/G65/G63/G2E/G63/G6F/G6D/G2E/G74/G77/G38 /G54/G79/G70/G69/G63/G61/G6C/G20/G50/G65/G72/G66/G6F/G72/G6D/G61/G6E/G63/G65 1. SOURCE-SINK Linear Regulator Transient Response - The output capacitor is 330uF (Low ESR tantalum capacitor) - Define the output cerrent (IVTT) sourcing from the regulator to be positive. - The interval of current transitions in figures 1 and 2 are all smaller than 1uS. - In figure 1, the IVTT transition is from -0.2A to 4A. - In figure 2, the IVTT transition is from 0.2A to -4A. Figure 1 Figure 2
Copyright ANPEC Electronics Corp. Rev. A. /G52/G65/G76/G2E/G41/G2E/G32 - Mar., 2002 /G41/G50/G57/G37/G30/G34/G36 /G77/G77/G77/G2E/G61/G6E/G70/G65/G63/G2E/G63/G6F/G6D/G2E/G74/G77/G39 /G50/G61/G63/G6B/G61/G67/G69/G6E/G67/G20/G49/G6E/G66/G6F/G72/G6D/G61/G74/G69/G6F/G6E SO – 300mil ( Reference JEDEC Registration MS-013) N 12 3 EH D L GAUGE PLANE e B A1 A Millimeters Variations- D Inches Variations- D D See variations SO-24 15.20 15.60 D See variations SO-24 0.599 0.614 H 10 10.65 H0 . 3 9 4 0 . 4 1 9 L 0.40 1.27 L0 . 0 1 6 0 . 0 5 0 N See variations N See variations φ 10 ° 8°φ 10 ° 8°
Copyright ANPEC Electronics Corp. Rev. A. /G52/G65/G76/G2E/G41/G2E/G32 - Mar., 2002 /G41/G50/G57/G37/G30/G34/G36 /G77/G77/G77/G2E/G61/G6E/G70/G65/G63/G2E/G63/G6F/G6D/G2E/G74/G77/G31/G30 t 25 C to Peak tp Ramp-up tL Ramp-down ts Preheat Tsmax Tsmin T L T P Temperature Time Critical Zone T L to TP °/G20 /G50/G68/G79/G73/G69/G63/G61/G6C/G20/G20/G53/G70/G65/G63/G69/G66/G69/G63/G61/G74/G69/G6F/G6E/G73 Sn-Pb Eutectic Assembly Pb-Free Assembly Profile Feature Large Body Small Body Large Body Small Body Average ramp-up rate (TL to TP) 3°C/second max. 3 °C/second max. Preheat /G2D/G20Temperature Min (Tsmin) /G2D/G20Temperature Mix (Tsmax) /G2D/G20Time (min to max)(ts) 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds Tsmax to TL - Ramp-up Rate 3°C/second max Tsmax to TL /G2D/G20Temperature(TL) /G2D/G20Time (tL) 183°C 60-150 seconds 217°C 60-150 seconds Peak Temperature(Tp) 225 +0/-5°C 240 +0/-5 °C 245 +0/-5 °C 250 +0/-5 °C Time within 5°C of actual Peak Temperature(tp) 10-30 seconds 10-30 seconds 10-30 seconds 20-40 seconds Ramp-down Rate 6°C/second max. 6 °C/second max. Time 25°C to Peak Temperature 6 minutes max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. /G52/G65/G66/G6C/G6F/G77/G20/G43/G6F/G6E/G64/G69/G74/G69/G6F/G6E/G20(IR/Convection or VPR Reflow) /G43/G6C/G61/G73/G73/G69/G66/G69/G63/G61/G74/G69/G6E/G20/G52/G65/G66/G6C/G6F/G77/G20/G50/G72/G6F/G66/G69/G6C/G65/G73 Terminal Material Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Lead Solderability Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Packaging 1000 devices per reel for SO-16 , 2500 devices per reel for SSOP-16. /G20
Copyright ANPEC Electronics Corp. Rev. A. /G52/G65/G76/G2E/G41/G2E/G32 - Mar., 2002 /G41/G50/G57/G37/G30/G34/G36 /G77/G77/G77/G2E/G61/G6E/G70/G65/G63/G2E/G63/G6F/G6D/G2E/G74/G77/G31/G31 /G52/G65/G6C/G69/G61/G62/G69/G6C/G69/G74/G79/G20/G74/G65/G73/G74/G20/G70/G72/G6F/G67/G72/G61/G6D Test item Method Description SOLDERABILITY MIL-STD-883D-2003 245°C , 5 SEC HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @ 125 °C PCT JESD-22-B, A102 168 Hrs, 100 % RH , 121°C TST MIL-STD-883D-1011.9 -65°C ~ 150°C, 200 Cycles ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V Latch-Up JESD 78 10ms , I tr > 100mA /G43/G61/G72/G72/G69/G65/G72/G20/G54/G61/G70/G65/G20/G26/G20/G52/G65/G65/G6C/G20/G44/G69/G6D/G65/G6E/G73/G69/G6F/G6E/G73 t Ao E W Po P Ko Bo D F A J B C Application A B C J T1 T2 W P E 330±16 2 ±1.5 12.75 ± F D D1 Po P1 Ao Bo Ko tSOP- 24 (mm)
Copyright ANPEC Electronics Corp. Rev. A. /G52/G65/G76/G2E/G41/G2E/G32 - Mar., 2002 /G41/G50/G57/G37/G30/G34/G36 /G77/G77/G77/G2E/G61/G6E/G70/G65/G63/G2E/G63/G6F/G6D/G2E/G74/G77/G31/G32 /G43/G6F/G76/G65/G72/G20/G54/G61/G70/G65/G20/G44/G69/G6D/G65/G6E/G73/G69/G6F/G6E/G73 Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 /G43/G75/G73/G74/G6F/G6D/G65/G72/G20/G53/G65/G72/G76/G69/G63/G65 Application Carrier Width Cover Tape Width Devices Per Reel SOP- 16 / 20 / 24 / 28 24 21.3 1000