APW3007 ANPEC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 12
Technical content
Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2003 APW3007 www.anpec.com.tw1 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Advanced Dual PWM and Dual Linear Power Controller
- •••• Provides 4 Regulated Voltages − Microprocessor Core , I/O , Clock Chip and GTL Bus
- •••• Simple Single-Loop Control Design − Voltage-Mode PWM Control
- •••• Fast Transient Response − High-Bandwidth Error Amplifier − Full 0% to 100% Duty Ratio
- •••• Excellent Output Voltage Regulation − Core PWM Output : ±1% Over Temperature − I/O PWM Output : ±2% Over Temperature − Other Output : ±2.5% Over Temperature
- •••• Power-Good Output Voltage Monitor
- •••• Microprocessor Core Voltage Protection Against Shorted MOSFET
- •••• Over-Voltage and Over-Current Fault Monitors
- •••• Small Converter Size − Constant Frequency Operation − 200kHz Free-Running Oscillator ; Programmagle from 50kHz to 800kHz Features General Description The APW3007 provides the power control and pro- tection for four output voltage in high-performance mi- croprocessor and computer applications. The APW3007 is designed to provide termination voltage VTT(1.25V) with ±1% accuracy. It integrates two PWM controllers , a linear regulator and a liear controller as well as the monitoring and protection function into a single package. One PWM controller regulates the microprocessor core voltage with a synchronous-rectified buck converter , while the second PWM controller supplies the I/O 3.3V power with a standard buck converter. The linear controller regulates power for GTL bus and the intermal 200mA regulator for clock driver circuits. The APW3007 can provide in excess of 14A of out- put current for an on-board DC/DC converter via in- ternal reference voltage. It can monitor all the output voltage , and a single Power Good signal is issued when the core is within 10% of the internal reference voltage and the other levels are above their under- voltage levels. Additional built-in over-voltage protec- tion for the core output uses the lower MOSFET to prevent output voltage above 115% of the reference voltage. The PWM controller’s over-current function monitor the output current by sensing the voltage drop across the upper MOSFET’s R DS(ON) , eliminating the need for a current sensing resistor.
Applications
- •••• Motherboard Power Regulation for Computers
- •••• Low-Voltage Distributed Power Supplies
- •••• VGA Card Power Regulation
- •••• Termination Voltage
Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2003 APW3007 www.anpec.com.tw2 Ordering and Marking Information Pin Description PHASE2 NC NC NC LGATE1 OCSET1 VSEN1 NC NC PGOOD PGND FB1 FB3 VSEN2 GND NC GATE3 PHASE1 FB2 SS FAULT NC UGATE2 UGATE1 V12 OCSET2 NC PHASE2 NC NC NC LGATE1 OCSET1 VSEN1 NC NC PGOOD PGND FB1 FB3 VSEN2 GND NC GATE3 PHASE1 FB2 SS FAULT FB4 UGATE2 UGATE1 V12 OCSET2 Vout4 APW3007-12 APW3007-13 APW3007 Voltage Code 12 : 1.25V 13 : 1.30V Package Code K : SOP - 28 Temp. Range C : 0 to 70 C Handling Code TU : Tube TR : Tape & Reel Handling Code Temp. Range Package Code Voltage Code APW 3007 K : APW 3007 XXXXX XXXXX - Date Code Absolute Maximum Ratings Symbol Parameter Rating Unit V12 Supply Voltage 15 V VI , VO Input , Output or I/O Voltage GND -0.3 V to V12 +0.3 V TA Operating Ambient Temperature Range 0 to 70 °C TJ Junction Temperature Range 0 to 125 °C TSTG Storage Temperature Range -65 to +150 °C TS Soldering Temperature 300 ,10 seconds °C
Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2003 APW3007 www.anpec.com.tw3 Thermal Characteristics Symbol Parameter Value Unit R θJA Thermal Resistance in Free Air SOIC SOIC (with 3in 2 of Copper) °C/W Block Diagram GATE CONTROL SOFT-START AND FAULT LOGIC THERMAL PROTECTION GATE CONTROL POWER-ON RESET FB3 GATE3 OCSET2 UGATE2 PHASE2 FB2 VSEN2 GND PGND LGATE1 PHASE1 UGATE1 PGOOD V12OCSET1 FB1SSFAULT 0.3V1.26V 200uA VCC DRIVE2 OC2 INHIBIT PWM2 2.0V ERROR AMP2 2.5V 4.3V VREF OSCILLATOR 3.3K 4.6V ERROR AMP1 0VFAULT OC1 PWM1 VCC LOWER DRIVE VCC DRIVE1 INHIBIT 115% 90% 110% 200uA LUV VSEN1 V5 VOUT4 FB4 0.3V
Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2003 APW3007 www.anpec.com.tw4
Electrical Characteristics
(Recommended operating conditions , Unless otherwise noted) Refer to Block and Simplified Power System Diagrams , and Typical Application Schematic. APW3007 Symbol Parameter Test Conditions Min Typ Max Unit Supply UVLO Section UVLO Threshold-12V Supply ramping up 9.5 V UVLO Hysterises-12V 0.5 V UVLO Threshold-5V Supply ramping up 4.3 V UVLO Hysterises-5V 0.3 V Supply Current I12 V12 6 Nominal Supply Current V5 2 mA Oscillator FOCS Free Running Frequency RT= Open 185 200 215 kHz ∆ VOSC Ramp Amplitude RT= Open 1.9 V P-P Switching Controller Reference Voltage 1.25 VREF Reference Voltage APW3007-12 APW3007-13 1.30 V Reference Voltage accuracy −1.0 +1.0 % VFB2 Output Voltage 2 V VFB2 Voltage Accuracy -2 +2 % 2.5V Regulator (Vout4) Vo4 Reference Voltage T A=25 , Vout4=FB4 1.26 V Dropout Voltage Io=200mA 0.6 V Load Regulation 1mA<Io<200mA 0.5 % Line Regulation 3.1V<VIO<4V , Vo=2.5V 0.2 % Input bias Current 2 µA Output Current 200 mA Current Limit 300 420 mA Thermal Shutdown 150 °C 1.5V Regulator (Vout3) Vo3 Reference Voltage T A=25 , GATE=FB3 1.26 V Reference Voltage Accaracy -2.5 +2.5 % Input bias current 2 µA Output Drive Current 50 mA
Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2003 APW3007 www.anpec.com.tw5 Electrical Characteristics Cont. APW3007 Symbol Parameter Test Conditions Min Typ Max Unit Synchronous PWM Controller Error Amplifier DC Gain 88 dB GBWP Gain-Bandwidth Product 15 MHz SR Slew Rate COMP1 = 10pF 6 V/ µS PWM Controller Gate Drive IUGATE UGATE Source V12 = 12V , V UGATE = 6V 1 A RUGATE UGATE Sink V UGATE-PHASE =1V 3.5 Ω ILGATE LGATE Source V12 = 12V , V LGATE = 1V 1 A RLGATE LGATE Sink V LGATE = 1V 3 Ω Protection VSEN1 O.V. Upper trip point VSEN1 ramping up 117 % VSEN1 O.V. lower trip point VSEN1 ramping down 115 % IOVP FAULT Souring Current V FAULT/RT=2.0V 8.5 mA IOCSET OCSET Current Source V OCSET=4.5VDC 170 200 230 µA RSS Pull up resistor to 5V OCSET=0V , Phase=5V 23 K Ω Power Good VSEN1 Upper Threshold VSEN1 Rising 110 % VSEN1 Under Voltage VSEN1 Rising 94 % VSEN1 Hysteresis Upper /Lower Threshold 2 % VPGOOD-L PGOOD Voltage Low RL = 3mA 0.4 V VPGOOD-H PGOOD Voltage High RL = 5k Ω Pull up to 5V 4.8 V
Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2003 APW3007 www.anpec.com.tw6 UGATE2 (Pin1) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the regulator’s pass tran- sistor . PHASE1 , PHASE2 (Pin26 and 2) Connect the PHASE pins to the respective PWM converter’s upper MOSFET source. These pins are used to monitor the voltage drop across the upper MOSFETs for over-current protection . No connection. PGOOD (Pin8) PGOOD is an open collector output used to indicate the status of the output voltages. This pin is pulled low when the synchronous regulator output is not within ±10% of the DACOUT reference voltage or when any of the other outputs are below their under-voltage thresholds . OCSET1 , OCSET2 (Pin23 and Pin9) Connect a resistor (R OCSET) from this pin to the drain of the respective upper MOSFET. ROCSET , an internal 200 µA current source (I OCSET ) , and the upper MOSFET’s on-resistance (rDS(ON)) set the converter over-current (OC) trip point according to the following equation : I PEAK = DS(ON) OCSET OCSET r RI x FB2 (Pin10) This pin provides the feedback for the non-synchro- nous switching regulator. A resistor driver is con- nected from this pin to vout2 and GND that sets the output voltage. The value of the resistor connected from Vout2 to FB2 must be less than 100Ω . V5 (Pin11) 5V supply voltage. A high frequency capacitor (0.1 to 1uF) must be placed close to this pin and con- nected from this pin to the GND plane for noise free operation. SS (Pin12) This pin provides the soft start for the 2 switching regulators. An internal resistor charges an external capacitor that is connected from 5V supply to this pin which ramps up the outputs of the switching regula- tors , preventing the outputs from overshooting as well as limiting the input current. The second function of the Soft Start cap is to provides long off time for the synchronoud MOSFET during current limiting . FAULT (Pin13) This pin has dual function. It acts as an output of the OVP cicuitry or it can be used to program the fre- quency using an extermal resistor. When used as a fault detector , if any of the switcher outputs exceed the OVP trip point , the FAULT pin switches to 12V and the soft start cap is discharged. If the FAULT pin is to be connected to any external circuity , it needs to be buffered as shown in the application circuit . FB4 (Pin14) APW3007-12 : NC This pin provides the feedback for the internal LDO regular that its ourpur is Vout4. VSEN2 (Pin15) This pin is connected to the output of the I/O switch- ing regulator. It is an input that provides sensing for the Under/Over voltage circuitry for the I/O supply as well as the power for the internal LDO regulator . VOUT4 (Pin16) Functional Pin Description APW3007-12 : NC This pin is the output of the internal LDO regulator.
Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2003 APW3007 www.anpec.com.tw7 PGND (Pin 24) This is the power ground connection . Tie the syn- chronous PWM converter’s lower MOSFET source to this pin . LGATE (Pin 25) Connect LGATE to the PWM converter’s lower MOSFET gate . This pin provides the gate drive for the lower MOSFET . UGATE (Pin 27) Connect UGATE pin to the PWM converter’s upper MOSFET gate . This pin provides the gate drive for the upper MOSFET . V12 (Pin28) Provide a 12V bias supply for the IC to this pin . This pin also provides the gate bias charge for all the MOSFETs controlled by the IC . The voltage at this pin is monitored for Power-On Reset purposes . Simplified Power System Diagram GND (Pin 17) Signal ground for the IC. All voltage levels are measured with respect to this pin. GATE3 (Pin 18) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the 1.5V regulator’s pass transistor. FB3 (Pin 19) Connect this pin to the output of the 1.5V linear regulator. This pin is monitored for under-voltage events. FB1 (Pin21) This pin provides the feedback for the synchronous switching regulator . Typically this pin can be con- nected directly to the output of the switching regula- tor . However , a resistor driver is recommended to be connected from this pin to vout1 and GND to ad- just the output voltage for any drop in the output volt- age that is caused by the trace resistance . The value of the resistor connected from Vou1 to FB1 must be less than 100Ω . PWM2 Controller Linear Controller PWM1 Controller CIN COUT CIN COUT L2L1 NVVDD VTT 3.3V CIN COUT 3.3V FBVDDQ Linear Regulator VOUT4 Functional Pin Description (Cont.) VSEN1 (Pin 22). This pin is connected to the PWM converter’s output voltage . The PGOOD and OVP comparator circuits use this signal to report output voltage status and for over-voltage protection .
Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2003 APW3007 www.anpec.com.tw8 Typical Application Circuit UGATE2 NC NC NC NC PHASE2 FB2 PGOOD NC OCSET2 NC FAULT SS VSEN2 NC OCSET1 VSEN1 FB1 FB3 GATE3 GND NC PHASE1 LGATE1 PGND UGATE1 V121 NVVDD 2.05V/4A VTT 1.25V/3.5A AGP 3.3V 12V AGP 3.3V FBVDDQ 2.5V/1.5A C807 330uF C808 1000uF R812 1.5k C809 220pF R813 5.1R Q802 APM9410 D800 FM5820 C811 330uF R814 100RF C810 330uF R816 4.02KF C800 10uF C804 1uF C805 1uF R810 97.6RF C817 330uF Q800 APM3055 C802 330uF R821 100R R820 5.1R Q803B APM7313 C815 330uF C816 330uF C814 10uF C813 330uF L802 2uH L803 7.8uH Q803A APM7313 C812 220pF R817 1.2K R819 5.1R C801 1uF RX1 10R L801 7.8uH L800 2uH APW3007-12 R811 100RF UGATE2 NC NC NC NC PHASE2 FB2 PGOOD NC OCSET2 FB4 FAULT SS VSEN2 NC OCSET1 VSEN1 FB1 FB3 GATE3 GND Vout4 PHASE1 LGATE1 PGND UGATE1 V121 NVVDD 2.05V/4A VTT 1.25V/3.5A AGP 3.3V 12V AGP 3.3V FBVDDQ 2.5V/1.5A C807 330uF C808 1000uF R812 1.5k C809 220pF R813 5.1R Q802 APM9410 D800 FM5820 C811 330uF R814 100RF C810 330uF R816 4.02KF C800 10uF C804 1uF C805 1uF R810 97.6RF C817 330uF Q800 APM3055 C802 330uF R821 100R R820 5.1R Q803B APM7313 C815 330uF C816 330uF C814 10uF C813 330uF L802 2uH L803 7.8uH Q803A APM7313 C812 220pF R817 1.2K R819 5.1R C801 1uF RX1 10R L801 7.8uH L800 2uH APW3007-13 R811 100RF APW3007-12 APW3007-13
Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2003 APW3007 www.anpec.com.tw9
Package Information
SO – 300mil ( Reference JEDEC Registration MS-013) Millimeters Variations- D Inches Variations- D D See variations SO-24 15.20 15.60 D See variations SO-24 0.599 0.614 H 10 10.65 H 0.394 0.419 L 0.40 1.27 L 0.016 0.050 N See variations N See variations φ 10 ° 8°φ 10 ° 8° N 12 3 E D L GAU PLA e B A1 A
Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2003 APW3007 www.anpec.com.tw10 Classification Reflow Profiles Package Reflow Conditions Refolw Condition (IR/ Convection or VPR Reflow) Physical Specifications Terminal Material Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb) Lead Solderability Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Packaging 1000 devices per reel Convection or IR/ Convection VPR Average ramp-up rate(183°C to Peak) 3 °C/second max. 10 °C /second max. Preheat temperature 125 ± 25°C) 120 seconds max. Temperature maintained above 183°C 60 ~ 150 seconds Time within 5°C of actual peak temperature 10 ~ 20 seconds 60 seconds Peak temperature range 220 +5/-0°C or 235 +5/-0°C 215~ 219 °C or 235 +5/-0°C Ramp-down rate 6 °C /second max. 10 °C /second max. Time 25°C to peak temperature 6 minutes max. pkg. thickness ≥≥≥≥ 2.5mm and all bags pkg. thickness < 2.5mm and pkg. volume ≥≥≥≥ 350 mm³ pkg. thickness < 2.5mm and pkg. volume < 350mm³ Convection 220 +5/-0 °C Convection 235 +5/-0 °C VPR 215-219 °C VPR 235 +5/-0 °C IR/Convection 220 +5/-0 °C IR/Convection 235 +5/-0 °C Reference JEDEC Standard J-STD-020A APRIL 1999 Pre-heat temperature 183 C Peak temperature Time temperature
Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2003 APW3007 www.anpec.com.tw11 Tape & Reel Dimensions Reliability test program Test item Method Description SOLDERABILITY MIL-STD-883D-2003 245°C , 5 SEC HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @ 125 °C PCT JESD-22-B, A102 168 Hrs, 100 % RH , 121°C TST MIL-STD-883D-1011.9 -65°C ~ 150°C, 200 Cycles ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V Latch-Up JESD 78 10ms , I tr > 100mA Application A B C J T1 T2 W P E 330±16 2 ±1.5 12.75 ± 0. F D D1 Po P1 Ao Bo Ko tSOP- 28 t Ao E W Po P Ko Bo D F A J B C
Copyright ANPEC Electronics Corp. Rev. A.5 - Jun., 2003 APW3007 www.anpec.com.tw12 Cover Tape Dimensions Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Application Carrier Width Cover Tape Width Devices Per Reel SOP- 28 24 21.3 1000