APL6535 ANPEC | Alldatasheet

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Two-Channel Supervisory IC Copyright  ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 www.anpec.com.tw1 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. APL6535 Features General Description

Applications

  • Graphics Cards
  • Portable Battery-Powered Equipment
  • µP Voltage Monitoring
  • Set-Top Boxes
  • Notebook Computer
  • Multiple Supply System
  • 2.6V to 5.5V Input Voltage Range
  • Low Quiescent Current : less than 50µA
  • High Accuracy Detection Threshold : ±1.6%
  • Adjustable Undervoltage Lockout for Each Supply
  • Active high PGOOD Output
  • Guaranteed PGOOD Valid to Falling VCC < 1V
  • VMON Glitch Immunity : 30µs
  • Lead Free Available (RoHS Compliant) Pinouts The APL6535 is a two channel supervisory IC designed to monitor voltage supplies in mP and digital system. This IC can supervise any positive voltage using an external resistor divider to translate to a lower voltage for comparison to the internal 0.633V reference. Once any VMON input falls below 0.633V the PGOOD out- put is pulled low, the hysteresis of the internal refer- ence is 15mV. The PGOOD pin has an internal 20kW pull-up to V CC making an external pull-up resistor unnecessary. Each rail’s VMON point is independently adjustable with a resistor divider. The PGOOD output is guaranteed to be valid with IC bias lower than 1V. This IC is designed to reject fast line transient glitches 30ms on VMON input. The PGOOD output is an open- drain to allow ORing of multiple signals. If less than four voltages are being monitored, connect the unused VMON pins to VCC. The ENABLE input pin provides for a reset of the PGOOD output when it is pulled down below 0.5V. With an internal 10mA pull-up to VCC, it can be signaled with common logic or pulled to ground with a push button switch. APL6535 come in a miniature SOT-23-5 package. GND VMON1 PGOOD Vcc VMON2 SOT-23-5 Top View APL6535

Copyright  ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 www.anpec.com.tw2 APL6535 B : SOT-23-5 Temp. Range I : -40 to 85 C Handling Code TU : Tube TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device Handling Code Temp. Range Package Code APL6535 : 535X X - Date Code Lead Free Code Pin Function Description Ordering and Marking Information PIN No. Name I/O

Description

1 VCC Supply Voltage

3 PGOOD O

PGOOD is the AND function of all the VMON inputs being satisfied. This is an open drain output and can be pulled high to the appropriate level with an external resistor. Additionally a 20kO pull up to VCC is provided internally.

2 GND Ground Connection

4, 5 VMON1 VMON2 I These inputs provide for a programmable monitored voltage threshold referenced to an internal 0.633V reference. These inputs have a 30 µs glitch filter to prevent transie nt upsets from being recognized by PGOOD. Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte in plate termina- tion finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classifica- tion at lead-free peak reflow temperature.

Copyright  ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 www.anpec.com.tw3 APL6535 Block Diagram Absolute Maximum Ratings Symbol Parameter Rating Unit VCC Input Voltage 6.5 V VMON1, 2 All Input Pins -0.3V to VCC+0.3V V PGOOD Output Pin -0.3V to VCC+0.3V V TJ Maximum Junction Temperature 150 °C TSTG Storage Temperature -65 to +150 °C TS Soldering Temperature (10 seconds) 260 °C ESD Electrostatic Discharge -3000 to 3000*1 V Note: 1.Human body model: C=100pF, R=1500, 3 positive s pulse plus 3 negative pulses . Falling Edge Glitch Filter VMON1 VMON2 PGOOD 10uA VCC (2.6~5.5V) 20k Ω 1M Ω 0.633V

Copyright  ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 www.anpec.com.tw4 APL6535

Electrical Characteristics

Unless Otherwise noted these specifications apply over full temperature, Vcc = 3.3V, TJ =- 40 °C to 85°C Typical values refer to TJ =25°C APL6535 Symbol Parameter Test condition Min. Typ. Max. Unit B BIAS VMON > VMON_L2H 40 400 µA ICC Supply Current (EN enable) VMON < VMON_H2L 230 2000 µA VMON > VMON_L2H 50 500 µA ICC Supply Current (EN disable) VMON < VMON_H2L 50 500 µA VCC_L2H VCC Power On VCC low to high 2.6 V VCC_POR VCC Power On Reset VCC high to low 2.4 V PGOOD PGpd Pull-Down Current VPGOOD=0.5V 10 mA PGpu Pull-Up Resistance 20 KΩ VPGI Output Low VCC = 1V 0 100 mV TPG del VMON Delay From VMON Rising Last valid input =Vth to PG release 3 µs TPG del ENR Delay From EN Rising EN high to PG release 2 µs TPG del ENF Delay From EN Falling EN low to PG pulling low 10 n s VMON Input VMON_H2L Falling Threshold Voltage TJ=25°C 0.623 0.633 0.643 V VMON_TC Falling Threshold Temperature Coeff. TJ=-40°C to 85°C 100 µV/°C VVMON_HYS Hysteresis Voltage 15 mV VVMON_RNG Range 10 mV TFIL Glitch Filter Duration VMON glitch to PGOOD low filter 30 µs

Copyright  ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 www.anpec.com.tw5 APL6535 Unless Otherwise noted these specifications apply over full temperature, Vcc = 5V, TJ =- 40 °C to 85°C Typical values refer to TJ =25°C APL6535 Symbol Parameter Test condition Min. Typ. Max. Unit B BIAS VMON > VMON_L2H 50 500 µA ICC Supply Current (EN Enable) VMON < VMON_H2L 230 2000 µA VMON > VMON_L2H 60 600 µA ICC Supply Current (EN Disable) VMON < VMON_H2L 60 600 µA VCC_L2H VCC Power On VCC low to high 2.6 V VCC_POR VCC Power On Reset VCC high to low 2.4 V PGOOD PGpd Pull-Down Current VPGOOD=0.5V 10 mA PGpu Pull-Up Resistance 20 KΩ VPGI Output Low VCC = 1V 0 100 mV TPG del VMON Delay From VMON Rising Last valid input = Vth to PG release 5 µs TPG del ENR Delay From EN Rising EN high to PG release 2 µs TPG del ENF Delay From EN Falling EN low to PG pulling low 10 ns VMON Input VMON_H2L Falling Threshold Voltage TJ=25°C 0.623 0.633 0.643 V VMON_TC Falling Threshold Temperature Coeff. TJ=-40°C to 85°C 100 µV/°C VVMON_HYS Hysteresis Voltage 15 mV VVMON_RNG Range 10 mV TFIL Glitch Filter Duration VMON glitch to PGOOD low filter 30 µs

Copyright  ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 www.anpec.com.tw6 APL6535 Timing Diagram Application Circuit 3 4 5VCC GND VMON1 VMON2PGOOD APL6535 3.3V 12V *10K 1uF 22k Ω10kΩ 4.7k Ω 1.5k Ω 0.47uF Vcc PGOOD Output * Optional <TFILTFIL PGOOD VMON EN Vth Vth

Copyright  ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 www.anpec.com.tw7 APL6535 0.618 0.620 0.622 0.624 0.626 0.628 0.630 0.632 0.634 0.636 0.638 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 0.630 0.633 0.636 0.639 0.642 0.645 0.648 0.651 100 150 200 250 300 350 400 Typical Characteristics Supply Current vs. Supply Voltage Supply Current vs. Temperature VMON_H2L vs. Temperature VMON Threshold vs. Supply Voltage VMON_H2L(V) Supply Voltage(V)Temperature(°C) Temperature(°C) Supply Current(µA) Supply Voltage(V) Supply Current(µA) VMON>VMON_L2H VCC=3.3V VMON Threshold(V) VMON_L2H VMON_H2L VCC=3.3V VCC=5V VCC=5V VMON>VMON_L2H VMON<VMON_H2L

Copyright  ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 www.anpec.com.tw8 APL6535 Typical Characteristics (Cont.) VMON High to PGOOD Time(4us/div) EN Low to PGOOD Time(10ns/div) VMON Low to PGOOD Time(20µs/div) VMON(1V/div) PGOOD(2V/div) EN(2V/div) VCC=3.3V VCC=3.3V PGOOD(2V/div) PGOOD(2V/div) VMON(1V/div) VCC=3.3V EN High to PGOOD EN(2V/div) PGOOD(2V/div) VCC=3.3V Time(1us/div)

Copyright  ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 www.anpec.com.tw9 APL6535

Application Information

The APL6535 is a four channel supervisory IC designed to monitor multiple voltages greater than 0.7V. This IC is suitable for both microprocessors or industrial system applications. Once biased to 2.6V and en- abled the IC continuously monitors from one to four voltages independently through external resistor di- viders comparing each VMON pin voltage to an inter- nal 0.633V reference. The PGOOD output is an open- drain to allow ORing of the signals and interfacing to a wide range of logic levels. If less than four voltages are being monitored, connect the unused VMON pins to VCC. The PGOOD pin has an internal 20kW pull-up to V CC making an external pull-up resistor unnecessary. Falling Edge Glitch Filter Once any VMON input falls below 0.633V the PGOOD output is pulled low, the VMON inputs are designed to reject fast transients (30us).

Copyright  ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 www.anpec.com.tw10 APL6535

Package Information

b 1 2 3 e D A2 A A1 L 2 L L 1a Millimeters Inches Dim Min. Max. Min. Max. A 0.95 1.45 0.037 0.057 A1 0.05 0.15 0.002 0.006 A2 0.90 1.30 0.035 0.051 b 0.30 0.50 0.011 0.019 D 2.8 3.00 0.110 0.118 E 2.6 3.00 0.102 0.118 E1 1.5 1.70 0.059 0.067 e 0.95BSC 0.037BSC e1 1.90BSC 0.07 4BSC L 0.35 0.55 0.014 0.022 L1 0.20 BSC 0.008 BSC L2 0.5 0.7 0.020 0.028 N 5 5 α 0° 10 ° 0° 10 °

Copyright  ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 www.anpec.com.tw11 APL6535 Physical Specifications Terminal Material Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb) , 100%Sn Lead Solderability Meets EIA Specification RSI86 -91, ANSI/J -STD-002 Category 3. t 25 C to Peak tp Ramp-up tL Ramp-down ts Preheat Tsmax Tsmin TL TP Temperature Time Critical Zone TL to T P Reflow Condition (IR/Convection or VPR Reflow) (mm) Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average ramp-up rate (TL to TP) 3°C/second max. 3°C/second max. Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds Time maintained above: - Temperature (TL) - Time (tL) 183°C 60-150 seconds 217°C 60-150 seconds Peak/Classificatioon Temperature (Tp) See table 1 See table 2 Time within 5°C of actual Peak Temperature (tp) 10-30 seconds 20-40 seconds Ramp-down Rate 6°C/second max. 6°C/second max. Time 25°C to Peak Temperature 6 minutes max. 8 minutes max. Notes: All temperatures refer to topside of the package .Measured on the body surface.

Copyright  ANPEC Electronics Corp. Rev. Table 1. SnPb Entectic Process – Package Peak Reflow Temperature s Table 2. Pb -free Process – Package Classification Reflow Temperatures including the stated classification temperature (this means Peak reflow temperature +0 °C. For example 260 °C+0 °C) at the rated MSL level.

Copyright  ANPEC Electronics Corp. Rev. Rev. A.1 - May., 2005 www.anpec.com.tw13 APL6535 Carrier Tape & Reel Dimensions(Cont.) A J B C Application A B C J T1 T2 W P E F D D1 Po P1 Ao Bo Ko tSOT-23-5 (mm) Application Carrier Width Cover Tape Width Devices Per Reel SOT- 23 8 5.3 3000 Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Customer Service Cover Tape Dimensions