APL6001 ANPEC | Alldatasheet

Document overview

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Technical content

Features

  • Supply Input Voltages Range: 2.8V to 5.5V
  • 100uA Low Supply Current
  • 3-Ch Analog Voltage Input: AIN1, AIN2, AIN3
  • High Accuracy Nonlinearity: +3LSB
  • High Accuracy A/D Resolution: - 4.6875mV for APL6001 - 10mV for APL6001A
  • High Accuracy A/D Full Scale Range: - 0 ~ 1.2V for APL6001 - 0 ~ 2.56V for APL6001A
  • Built-in Alert Flag, I2C Address Programming and EN control Functions
  • I2C interface with 8-bit AD converter
  • VTQFN1.5x2-10L with Lead Free & RoHS compliant

Applications

  • Phone & NB Application
  • Temperature Measurement
  • Portable Instrumentation
  • Consumer Goods APL6001/A VTQFN1.5x2-10L (TOP View) SCL ADDR Alert GND AIN2 AIN1 AIN3 EN VDD SDA 4 6 Alert AIN1 AIN2 AIN3 ADDR APL6001/A EN ON OFF VDDVDD GND SCL SDA VIN AIN1 AIN2 AIN3 APL6001/A EN ON OFF Alert ADDR VIN VDDVDD GND SCL SDA

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw2 Ordering and Marking Information Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant)and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Package Code Temperature Range Package Code APL6001 Handling Code Assembly Material Operating Ambient Temperature Range Handling Code Assembly Material QF : VTQFN1.5x2-10L I : -40 to 85 °C TR : Tape & Reel G : Halogen and Lead Free Device APL6001 QF 6001 X X : Date Code APL6001A QF 601A X X : Date Code Symbol Parameter Rating Unit VDD VDD Supply Voltage, VDD to GND -0.3 ~ 6.0 V VI/O Input & Output or I/O (ADDR, Alert, EN, SCL, SDA, AIN1, AIN2, AIN3) voltages -0.3 ~ VDD V PD Power Dissipation Internally Limited W TJ Junction Temperature 150 °C TSTG Storage Temperature -65 ~ 150 °C TSDR Maximum Lead Soldering Temperature(10 Seconds) 260 °C VESD Minimum ESD Rating (Human Body Mode) (MM Mode) 0.2 kV Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter Typical Value Unit θJA Junction-to-Ambient Resistance in free air (Note 2) TBD °C/W Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Symbol Parameter Range Unit VDD VDD Supply Voltage, VDD to GND 2.8 ~ 5.5 V VI/O Input & Output pins (ADD, Alert, EN, SCL, SDA) voltage 0 ~ VDD V APL6001 input pins (AIN1, AIN2, AIN3) voltage 0 ~ 1.2 V VAIN APL6001A input pins (AIN1, AIN2, AIN3) voltage 0 ~ 2.56 V TA Ambient Temperature -40 ~ 85 °C TJ Junction Temperature -40 ~ 125 °C Recommended Operating Conditions (Note 3)

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw3

Electrical Characteristics

Unless otherwise specified, these specifications apply over V DD=5V, VEN=3V and TJ= -40 to 85oC. Typical values are at T J=25oC. Specification Symbol Parameter Test condition Min. Typ. Max. Unit SUPPLY CURRENT IVDD VDD Input Current - 80 100 uA IVDD_SHDN VDD Shutdown Current VEN=0V - 0.1 - uA POWER-ON RESET (POR) VPOR VDD POR Threshold Voltage VDD Rising - 2.35 2.6 V VPOR_Hys VDD POR Hysteresis Voltage VDD Falling - 0.1 - V EN threshold VEN_H High Level Input Threshold Voltage 1.4 - - V VEN_L Low Level Input Threshold Voltage - - 0.4 V RPULL_LOW Internal Pull Low Resistor - 700 - kΩ Voltage Monitor (APL6001) - 4.6875 - mV/LSB A/D A/D Resolution (APL6001A) - 10 - mV/LSB (APL6001) 0 - 1.2 V A/D Full Scale Range (APL6001A) 0 - 2.56 V Differential nonlinearity - - 3 LSB Integral nonlinearity - - 3 LSB Input Bias Current - - 10 nA AIN1, AIN2, AIN3 Monitor Time - 1.2 2.4 ms Address Setting ADDR Address Latch Time - - 10 ms Address 1 Voltage Range Address = 0x7E (Hex) 92 95 100 %VDD Address 2 Voltage Range Address = 0x7C (Hex) 82 85 88 %VDD Address 3 Voltage Range Address = 0x7A (Hex) 72 75 78 %VDD Address 4 Voltage Range Address = 0x78 (Hex) 63 65 68 %VDD Address 5 Voltage Range Address = 0x76 (Hex) 52 55 58 %VDD Address 6 Voltage Range Address = 0x74 (Hex) 42 45 48 %VDD Address 7 Voltage Range Address = 0x72 (Hex) 32 35 38 %VDD Address 8 Voltage Range Address = 0x70 (Hex) 0 25 28 %VDD IADDR_LEAK ADDR Leakage Current VADDR=5V - - 100 nA Alert Output When ALT pin pull low, I ALT=10mA - - 0.2 V ALT ALT Output Low Voltage When ALT pin pull low, I ALT=50mA - - 0.8 V ALT Pull Low Pulse Time When ALT pin Alert - 50 - us ALT Pull Low cycle Time When ALT pin Alert - 2 - s IALT_LEAK ALT Leakage Current VALT=5V - - 100 nA I C Interface FI2C I C Clock Rate Range 1 - 400 kHz I2C Input High Voltage 1.4 - - V I C Input Low Voltage - - 0.4 V I C Leakage Current VSCL=VSDA=5V - - 100 nA

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw4 Electrical Characteristics (Cont.) Timing characteristics for I 2C Interface signals over recommended operating conditions (unless otherwise noted) Fast Speed Symbol Parameter Min. Max. Unit fSCL Frequency, SCL - 400 kHz tW(H) Pulse Duration, SCL High 600 - ns tW(L) Pulse Duration, SCL Low 1300 - ns tr Rise Time, SCL and SDA 20+0.1 C L(pF) 300 ns tf Fall Time, SCL and SDA 20+0.1 C L(pF) 300 ns tsetup1 Setup Time, SCL to SDA 100 - ns thold1 Hold Time, SCL to SDA 100 - ns t(buf) Bus Free Time Between Stop and Start Condition 1300 - ns tsetup2 Setup Time, SCL to Start Condition 600 - ns thold2 Hold Time, Start condition to SCL 600 - ns tsetup3 Setup Time, SCL to Stop Condition 600 - ns CL Load Capacitance for Each Bus Line - 400 pF SDA SCL tW(H) tW(L) tf tr tsetup1 thold1 SDA and SCL Timing SDA SCL tsetup2 thold2 Start Condition tsetup3 t(buf) Stop Condition Start and Stop Condition Timing

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw5 Typical Operating Characteristics 0 50 AIN1 Input Voltage (V) Read Reg0x03 (Dec.) APL6001 AIN1 vs. Reg0x03 25 75100125150175200225250275 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 APL6001 AIN2 vs. Reg0x04 0 50 AIN2 Input Voltage (V) Read Reg0x04 (Dec.) 25 75100125150175200225250275 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 APL6001 AIN3 vs. Reg0x05 0 50 AIN3 Input Voltage (V) Read Reg0x05 (Dec.) 25 75100125150175200225250275 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 50 AIN1 Input Voltage (V) Read Reg0x03 (Dec.) APL6001A AIN1 vs. Reg0x03 25 75100125150175200225250275 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 APL6001A AIN2 vs. Reg0x04 0 50 AIN2 Input Voltage (V) Read Reg0x04 (Dec.) 25 75100125150175200225250275 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 APL6001A AIN3 vs. Reg0x05 0 50 AIN3 Input Voltage (V) Read Reg0x05 (Dec.) 25 75100125150175200225250275 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw6 Typical Operating Characteristics Quiescent Current (µA) VDD Input Voltage (V) Quiescent Current vs. VDD 100 120 Quiescent Current (µA) Junction Temperature (oC) Quiescent Current vs. Temperature -50 -25 0 25 50 75 100 125 150 100 120 ALT/ADD Pull Low Time (µs) VDD Input Voltage (V) Alert Low Pulse Time vs. VDD 3 3.5 4 4.5 5 5.5 6 ALT/ADD Pull Low Time (µs) Junction Temperature (oC) Alert Low Pulse Time vs. Temperature -50 -25 0 25 50 75 100 125 150

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw7 Pin Description PIN NO. NAME FUNCTION 1 ADDR Address Selection. Connect a voltage divider to select the APL6001/A I 2C address. Connect this pin to GND definitely for 0x70 address programming. Do not leave ADDR pin floating. 2 Alert Thermal Alert. When anyone of V AINx is lower than setting voltage, it will pull low and send alert signal to the system. If used, connect to VIN via a resistor. Connect this pin without any capacitor. 3 GND Signal and Power Ground. All the voltage levels are measured by reference to this pin. 4 AIN2 Analog Voltage Input 2. 5 AIN1 Analog Voltage Input 1. 6 AIN3 Analog Voltage Input 3. 7 EN Enable Control Input. Forcing this pin above 1.4V to enable the device. Forcing this pin below 0.4V to turn off the regulator and reduce quiescent current, and the I C will be none-ACK. The resistance is internally pulled down by 700k Ω to GND. 8 VDD Device power supply pin. Connect this pin with 0.1uF capacitor.

9 SDA I

C interface Data I/O pin. Connect this pin to I C bus data signal. 10 SCL I2C interface Clock I/O pin. Connect this pin to I 2C bus clock signal. Block Diagram I2C Interface POR A/D Converter Control Logic Timing Control ReferenceVDD EN ADDR Alert SCL SDA AIN1 AIN2 AIN3 GND

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw8 Typical Application Circuit The I2C Address Programming and Alert Flag functions are used. RIN3 RNTC3 C3 AIN1 AIN2 AIN3 APL6001/A RIN2 RNTC2 C2 RIN1 RNTC1 C1 RAlert EN ON OFF Alert ADDR VIN CVDD VDDVDD GND SCL SDA RSCL RSDA The I2C Address is used as default and Alert Flag function is unused. Alert AIN1 AIN2 AIN3 ADDR APL6001/A EN ON OFF CVDD VDDVDD GND SCL SDA RSCL RSDA RIN3 RNTC3 C3 RIN2 RNTC2 C2 RIN1 RNTC1 C1 VIN VAINx = 0~1.2V(for APL6001) or 0~2.56V(for APL6001A) is recommended. RAlert > 1kΩ is recommended. RINx and RNTCx = 10kΩ ~10MΩ is recommended. CVDD, C1, C2 and C3 > 0.1uF is recommended. RSCL and RSDA = 1kΩ ~10kΩ is recommended.

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw9 Function Description Input Voltage and Power-On-Reset The APL6001/A can work normally and start monitoring the AINx voltage, when the supply voltage VDD is greater than the POR and the EN input control signal is high. The POR threshold is 2.5V typically when the VDD rising. I2C Interface Data Validity The SCL voltage level can only be changed to Low to High, when the SDA is stable unless the START and STOP status. The SDA can only be changed the voltage level when the SCL voltage is Low. I2C Start and Stop Conditions The START (S) condition is the SDA transient from High to Low, when SCL is High. The STOP (P) condition is the SDA transient from Low to High, when SCL is High. The STOP condition must send before each START condition. I2C Acknowledge Each Address and Data are transmitted by using 8 clock pulses with 1 clock pulse Acknowledge (A). The Acknowl- edge is used for two purposes: one is the device that recog- nizes its own address. Another one is all of the master and slave to acknowledge receipt the register address or data. The SDA will pull Low to acknowledge. Read and Write Protocol (S=START, P=STOP, A=ACK from Slave, NA=Non-ACK) SDA SCL SDA stable SCL level LowData valid Data change SDA SCL STOP (P)START (S) SDA SCL Bit 1 Bit 0 ACK Slave SDA pull Low Master SDA pull Low SDA SCL 7-Bit Slave Address A 8-Bit Register Address A 8-Bit Register Data for Address A S P MSB to LSB MSB to LSB MSB to LSB Master Write to a Slave Register Example (W) SDA SCL 7-Bit Slave Address A 8-Bit Register Address A 8-Bit Register Data for Address NA S P MSB to LSB MSB to LSB MSB to LSB Master Read from a Slave Register Example 7-Bit Slave Address A MSB to LSB S (W) (R)

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw10 Function Description (Cont.) I2C Address Programming The APL6001/A I 2C address is programmable, which can be selected from 0x70h to 0x7Eh by the 7-bit slave address with one R/W bit. The slave device compares the 7-bit slave address with its address and matches. The programmable address is selected by a voltage di- vider R1 and R2. The ADDR pin voltage is compared with 8 addresses available internal reference voltage for ad- dress programming. Note: If the address programming function is not used, the ADDR pin must be connected to GND and the I 2C address is used as default value 0x70h. Voltage Monitoring and I2C Programming Interface The AINx voltages are digitized directly by high precision A/D converter and interfaced to the I2C bus. The AINx volt- ages are sensed alternately and take 1.2ms every channel. When the VDD supply voltage range from 2.8 to 5.5V, the A/D converter have 4.6875mV (for APL6001) or 10mV (for APL6001A) of resolution, and 0 to 1.2V (for APL6001) or 0 to 2.56V (for APL6001A) of full scale range. The A/D con- verter sensing results are stored in the internal register that shows as follow: AIN1 A/D data store (TD1): Reg0x03[7] (MSB) ~ Reg0x03 [0] (LSB) AIN2 A/D data store (TD2): Reg0x04[7] (MSB) ~ Reg0x04 [0] (LSB) AIN3 A/D data store (TD3): Reg0x05[7] (MSB) ~ Reg0x05 [0] (LSB) If the internal register code is read as Code X in integer decimal format, the AINx voltage transition to the internal register Reg0x03, Reg0x04 and Reg0x05 calculation as follows: The voltage divider at VIN-RINx-RNTCx-GND sets the voltage AINx is calculated as: I2C Interface R1 R2 ADDR VDD 0x7E 0x7C 0x7A 0x78 0x76 0x74 0x72 0x70 Address Selection (Hex) 0 20 30 40 50 60 70 80 90 10010 ADDR Input Voltage (% of VDD) Address R1 (kOhm) R2 (kOhm) ADDR (% of VDD) 0x70 0x72 0x74 0x76 0x78 0x7A 0x7C 0x7E Open 5.1 2.7 4.3 3.6 3.9 4.7 3.6 6.8 6.2 1.5 8.2 Open 100 A/D Converter I2C Interface RINx RNTCx Cx AINx VDD ( ) ( ) APL6001AforCode10mVVor10mV VCode APL6001forCode4.6875mVVor4.6875mV VCode XAINx AINx X XAINx AINx X ×== ×== NTCxINx NTCx AINx RR RVINV +×= According to the above equation: ( ) ( ) APL6001Afor10mV RR RVIN Codeor APL6001for4.6875mV RR RVIN Code NTCxINx NTCx X NTCxINx NTCx X =+× Note: If the AINx pin is not used, that must be pulled to the high level. And the CX is recommended to bypass the AINx pin.

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw11 Function Description (Cont.) Alert Flag The Alert Flag is used to indicate the system state. When the setting condition is established at the AINx voltage, the APL6001/A will make the internal MOS in the Alert pin turns on and pull low 50us every 2s cycle time. Alert Control Logic VDD RAlert Alert Alert Threshold Level Setting The Alert levels are set in the internal register by I 2C interface shows as follows: AIN1 Alert level set-up (TL1): Reg0x00[7] (MSB) ~ Reg0x00[0] (LSB) AIN2 Alert level set-up (TL2): Reg0x01[7] (MSB) ~ Reg0x01[0] (LSB) AIN3 Alert level set-up (TL3): Reg0x02[7] (MSB) ~ Reg0x02[0] (LSB) If one of conditions is established include TL1>TD1, TL2>TD2 or TL3>TD3, the Alert function will be enabled, and the Alert Indication of internal resistor Reg0x06[6:4] will be set to 1 that shows as below: If the Reg0x00 (TL1) > Reg0x03 (TD1), than the bit Reg0x06[4] = 1, else the bit Reg0x06[4] = 0 If the Reg0x01 (TL2) > Reg0x04 (TD2), than the bit Reg0x06[5] = 1, else the bit Reg0x06[5] = 0 If the Reg0x02 (TL3) > Reg0x05 (TD3), than the bit Reg0x06[6] = 1, else the bit Reg0x06[6] = 0 Chip ID: Reg0xB2[7:0] = 0x1A I2C Registers Summary Bits Register Address Register Name D7 D6 D5 D4 D3 D2 D1 D0 Read/ Write Default Value 0x00 TL1 TL1[7:0] R/W 00h 0x01 TL2 TL2[7:0] R/W 00h 0x02 TL3 TL3[7:0] R/W 00h 0x03 TD1 TD1[7:0] R 00h 0x04 TD2 TD2[7:0] R 00h 0x05 TD3 TD3[7:0] R 00h 0x06 ALT Reversed AM3 AM2 AM1 Reversed R 00h 0xB2 Chip ID Chip ID = 0x1A R 1Ah

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw12 Manufature Information APL6001 / A manufaturing information. Including wafer fab and assembly location. ANPEC Device Manufature Assembly APL6001 / A TSMC ASE / CJE ANPEC Electronic Corp. Account manager Kevin Chang

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw13

Package Information

VTQFN1.5x2-10 Pin1 aaa SEATING PLANE A D E NX C eb2 b3 L2 b1 L1 Pin1 Corner S Y M B O L MIN. MAX. 0.60 0.00 0.25 0.35 0.05 A e MILLIMETERS A3 0.152 REF VTQFN1.5*2-10

0.006 REF

MIN. MAX. INCHES 0.024 0.000 0.010 0.014 0.50 0.020 0.002 0.50 BSC 0.020 BSC L1 0.30 0.40 0.012 0.016 aaa 0.08 0.003 L2 0.35 0.45 0.014 0.018 D E 1.40 1.60 0.055 0.063 1.90 2.10 0.075 0.083 0.20 0.30b2 0.008 0.012 0.17 0.28b3 0.007 0.011

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw14 Carrier Tape & Reel Dimensions A AB W F T P0OD0 B SECTION B-B SECTION A-A OD1 H A d Application A H T1 C d D W E1 F 178.0 ± 2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 VTQFN1.5x2 (mm) Devices Per Unit Package Type Unit Quantity VTQFN1.5x2 Tape & Reel 3000

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw15 Taping Direction Information VTQFN1.5x2 USER DIRECTION OF FEED

Copyright  ANPEC Electronics Corp. Rev. A.2 - Feb., 2017 APL6001/A www.anpec.com.tw16 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds Average ramp-up rate (Tsmax to TP) 3 °C/second max. 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 183 °C 60-150 seconds 217 °C 60-150 seconds Peak package body Temperature (Tp)* See Classification Temp in table 1 See Classification Temp in table 2 Time (tP) within 5°C of the specified classification temperature (Tc) 20 seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. Time 25°C to peak temperature 6 minutes max. 8 minutes max. * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Classification Profile

Copyright  ANPEC Electronics Corp. Table 2. Pb-free Process – Classification Temperatures (Tc) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)