APL3225 ANPEC | Alldatasheet

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Technical content

Features

Applications

  • Cell Phones General Description Simplified Application Circuit The APL3225 provides complete Li+ charger protection against input over-voltage, input over-current and over- temperature. When any of the monitored parameters is over the threshold, the IC turns off the charging current. All protections also have deglitch time against false trig- gering due to voltage spikes or current transients. The APL3225 integrates a 5.5V LDO to prevent ACIN over- shoot reaching CHR_LDO and OUT. When any transient peak voltage above 5.5V presenting in ACIN pin, but be- low OVP threshold, the internal LDO will clamp its output at 5.5V. When ACIN voltage exceeds OVP threshold, the device will turn off charging current. The charging current is controlled by the GATDRV pin. When sourcing a cur- rent from the GATDRV pin, the OUT pin delivers the charg- ing current which is 200-fold magnified in amplitude based on GATDRV’s current. Other features include accurate VVCDT/VACIN voltage divider, reverse current blocking from OUT to ACIN and OTP protection. The APL3225 provides complete Li+ charger protections, and saves the external MOSFET and Schottky diode for the charger of cell phone’s PMIC. The above features and small package make the APL3225 an ideal part for cell phones applications.Pin Configuration ACIN 1 ACIN 2 VCDT 4 5 GATDRV GND 3

8 OUT

7 OUT

6 CHR_LDO

(Top View) = Exposed Pad (connected to ground plane for better heat dissipation) DFN3x3-8 (Top View) ACIN 1 GND 3

5 GATDRV

CHR_LDO VCDT GATDRV OUT Adapter VCDT GATDRV CHR_LDO ISENS VBATLi+ Battery

Copyright  ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 APL3225 www.anpec.com.tw2 Ordering and Marking Information Absolute Maximum Ratings (Note 1) Symbol Parameter Rating Unit VACIN ACIN Input Voltage (ACIN to GND) -0.3 ~ 28 V VCHR_LDO CHR_LDO to GND Voltage -0.3 ~ 7 V VGATDRV GATDRV to GND Voltage -0.3 ~ VCHR_LDO V VCDT VCDT to GND Voltage -0.3 ~ 7 V VOUT OUT to GND Voltage -0.3 ~ 7 V IOUT Output Current (OUT to GND) 2 A TJ Maximum Junction Temperature 150 oC TSTG Storage Temperature -65 ~ 150 oC TSDR Maximum Lead Soldering Temperature (10 Seconds) 260 oC Symbol Parameter Typical Value Unit θ JA TDFN2x2-8 Junction-to-Ambient Resistance in free air (Note 2) 75 oC/W θ JA DFN3x3-8 Junction-to-Ambient Resistance in free air (Note 2) 65 oC/W Thermal Characteristic Note 2: θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of TDFN2x2-8 is soldered directly on the PCB. Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Note 1:Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ”recom- mended operating conditions”is not implied. Exposure to absolute maximum rating conditions for extended periods may affect vice reliability. Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material Handling Code Temperature Range Package Code X - Date Code G : Halogen and Lead Free Device Assembly Material QB : TDFN2x2-8 APL3225 QB: L25 X QA : DFN3x3-8 X - Date CodeAPL3225 QA: APL 3225 XXXXX

Copyright  ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 APL3225 www.anpec.com.tw3 Symbol Parameter Range Unit VACIN ACIN Input Voltage 4.5 ~ 6.5 V IOUT Output Current 0 ~ 1 A TA Ambient Temperature -40 ~ 85 oC TJ Junction Temperature -40 ~ 125 oC CCHR_LDO CHR_LDO Output Capacitor 1 µF Recommended Operating Conditions (Note 3) Note 3: Refer to the typical application circuit Unless otherwise specified, these specifications apply over V ACIN=5V, TA= -40 ~ 85 oC. Typical values are at TA=25oC.

Electrical Characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit ACIN INPUT CURRENT and POWER-ON-RESET (POR) IOUT=0A, ICHR_LDO=0A - 350 600 µA In OTP - - 550 µA IACIN ACIN Supply Current VACIN>VOVP - - 550 µA VPOR ACIN POR Threshold VACIN rising 2.4 2.6 2.8 V ACIN POR Hysteresis - 250 - mV TB(ACIN) ACIN Power-On Blanking Time - 8 - ms INTERNAL SWITCH ON RESISTANCE ACIN to OUT On Resistance IOUT = 1A - 0.3 0.35 Ω CHR_LDO Discharge Resistnace VACIN = 12V , VCHR_LDO = 2V - 500 - Ω INPUT OVER-VOLTAGE PROTECTION (OVP) VREG Internal LDO Output Voltage VACIN = 6V, IOUT = 10mA, TJ = -40 ~ 125 oC 5.265 5.5 5.735 V LDO Output Series Resistance 2.4 3 3.6 kΩ VOVP Input OVP Threshold APL3225 VACIN rising, TJ = -40 ~ 125 oC 6.6 6.8 7 V Input OVP Hysteresis 150 200 250 mV TOVP Input OVP Propagation Delay - - 1 µs TON(OVP) Input OVP recovery time - 1 - ms OVER-CURRENT PROTECTION (OCP) IOC Over-Current Trip Threshold TJ = 25 oC, TJ = -40 ~ 25 oC 1.5 - - A ICL Current Limit Level TJ = 25 oC, TJ = -40 ~ 25 oC 1.2 - - A VCDT INTERNAL DIVIDER Divider Ratio VVCDT/VACIN 0.1035 0.1056 0.1078 V/V CHARGE CURRENT CONTROL Current Mirror Gain IOUT = 0.6A, IOUT/IGATDRV 100 200 300 A/A

Copyright  ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 APL3225 www.anpec.com.tw4 Unless otherwise specified, these specifications apply over V ACIN=5V, TA= -40 ~ 85 oC. Typical values are at TA=25oC. Electrical Characteristics (Cont.) APL3225 Symbol Parameter Test Conditions Min. Typ. Max. Unit REVERSE CURRENT BLOCKING PMOS Lockout Threshold - 20 - mV PMOS Lockout Release Threshold - 150 - mV OUT Input Current (Reverse Current Blocking) VACIN = 0V, VOUT = 4.2V, VGATDRV=0V - - 1 µA VOUT OVERSHOOT CLAMP VCCAMP Overshoot Clamp Rising Threshold VOUT rising slew rate > 0.2V/µs 4.6 4.8 5.0 V Overshoot Clamp Pull Low Resistance VOUT rising slew rate > 0.2V/µs - 3 - Ω Overshoot Clamp Active Time From Overshoot Clamp Threshold being surpassed - 150 - µs Thermal Shutdown Protection TOTP Thermal Shutdown Threshold TJ rising - 160 - °C Thermal Shutdown Hysteresis - 40 - °C

Copyright  ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 APL3225 www.anpec.com.tw5 Pin Description PIN NO NAME FUNCTION ACIN Power Supply Input. Connect this pin to external DC supply. Bypass to GND with a 1µF (minimum) ceramic capacitor. 3 GND Ground terminal. 4 VCDT Provide an interval voltage divider. This pin divides ACIN voltage into 39/369 ratio. 5 GATDRV Charging current control pin. When sourcing a current from this pin, the OUT pin will source out a current whose magnitude is 200xIGATDRV . 6 CHR_LDO Output Pin. The pin provides supply voltage to the PMIC input. Bypass to GND with a 1µF (minimum) ceramic capacitor. 7 Output Pins. The pin provides supply source current in series with a resistor to battery. OUT This pin possesses the overshoot clamp function to limit peak voltage. Exposed Pad - Exposed Thermal Pad. Must be electrically connected to the GND pin.

Copyright  ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 APL3225 www.anpec.com.tw6 Block Diagram Typical Application Circuit GATDRV CHR_LDO VCDT OUT GND ACIN OVERSHOOT CLAMP ACIN GND APL3225 PMIC 0.2Ω 1µF1µF CHR_LDO VCDT GATDRV OUT Adapter VCDT GATDRV CHR_LDO ISENS VBATLi+ Battery C1 C2 1, 2 7, 8 Designation Description 1µF, 25V, X5R, 0603 Murata GRM188R61E105K CACIN 1µF, 16V, X5R, 0603 Murata GRM188R61C105K CCHR_LDO 1µF, 6.3V, X5R, 0603 Murata GRM185R60J225KE26

Copyright  ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 APL3225 www.anpec.com.tw7 Function Description ACIN Power-On-Reset (POR) The APL3225 is built-in a power-on-reset circuit to keep the output shut off until internal circuitry is operating properly. The POR circuit has hysteresis and a de-glitch feature so that it will typically ignore undershoot transients on the input. When input voltage exceeds the POR thresh- old and after 8ms blanking time, the output voltage starts a soft-start to reduce the inrush current. ACIN Over-Voltage Protection (OVP) and LDO Mode Operation The CHR_LDO output of the IC operates similar to a lin- ear regulator. When the ACIN input voltage is less than VREG, and above the ACIN POR V ACIN, the internal LDO output voltage tracks the input voltage with a voltage drop caused by R DS(on) of MOSFET Q1. When the ACIN input voltage is greater than V REG plus the R DS(on) drop of Q1, and less than V OVP, the internal LDO output voltage is regulated to VREG, and this is also referred as LDO mode operation. If the input voltage rises above V OVP, the inter- nal FET Q1 and Q2 will be turned off within 1µs to protect connected system on OUT pin. When the input voltage returns below the input OVP threshold minus the hysteresis, the FETs is turned on again after 1ms recov- ery time. The input OVP circuit has a 200mV hysteresis and a recovery time of T ON(OVP) to provide noise immunity against transient conditions. Charging Current Control The charging current is controlled by the GATDRV pin. When sourcing a current from the GATDRV pin, the OUT pin delivers the charging current which is 200-fold mag- nified in amplitude based on GATDRV’s current. The IOUT current can be calculated by this following equation: IOUT=200xIGATDRV where The IOUT is the current flowing out from OUT pin. The IGATDRV is the current flowing out from GATDRV pin. Current Limit The output current is monitored by the internal current limit circuit. When the output current reaches the current limit threshold, the device limits the output current at cur- rent limit threshold. The current limit level decrease as the junction temperature increase. When the Junction temperature increases, the internal current limit circuit reduces the current limit level, allowing the device’s Junc- tion temperature to cool down. Internal P-MOSFET and Reverse Current Blocking The APL3225 integrates a P-channel MOSFET with the body diode reverse protection to replace the external PNP transistor and Schottky diode for cell phone’s PMIC. The body diode reverse protection prevents battery voltage supplies to CHR_LDO and ACIN pin. When the P-chan- nel MOSFET’s negative VSD voltage is detected, the inter- nal bulk selection circuitry will switch the body diode of the P-channel MOSFET forward biased from source to drain, meanwhile the P-channel is turned off regardless of GATDRV’s current. This after the detection of negative VSD, the P-channel MOSFET is in lockout state to prevent battery discharging from ACIN and CHR_LDO to external circuitry. The P-channel MOSFET lockout will be releases when positive VSD is detected. This OUT pin possesses the overshoot clamp function to limit peak voltage. Since the clamping function needs a low resistance path between OUT pin and external high voltage source (in abnormal condition), please connect this OUT pin directly to outside circuit to let clamping work. OUT Overshoot Clamp

Copyright  ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 APL3225 www.anpec.com.tw8

Application Information

The input capacitor is for decoupling and prevents the input voltage from overshooting to dangerous levels. In the AC adapter hot plug-in applications or load current step-down transient, the input voltage has a transient spike due to the parasitic inductance of the input cable. A 25V, X5R, dielectric ceramic capacitor with a value be- tween 1 µF and 4.7 µF placed close to the ACIN pin is recommended. The output capacitor of CHR_LDO is for CHR_LDO volt- age decoupling. And also can be as the input capacitor of the charging circuit. At least, a 1µF, 10V, X5R capacitor is recommended. Layout Consideration In some failure modes, a high voltage may be applied to the device. Make sure the clearance constraint of the PCB layout must satisfy the design rule for high voltage. The exposed pad of the TDFN2x2-8 and DFN3x3-8 performs the function of channeling heat away. It is recommended that connect the exposed pad to a large copper ground plane on the backside of the circuit board through sev- eral thermal vias to improve heat dissipation. The input and output capacitors should be placed close to the IC. The high current traces like input trace and output trace must be wide and short. Recommended Minimum Footprint TDFN2x2-8 Thermal Via diameter12mil X 5 Ground plane for Thermal PAD 0.241mm 0.508mm 0.222mm 0.8mm 0.572mm 1.295mm Thermal Via diameter12mil X 5 Ground plane for Thermal PAD 0.305mm 0.66mm 0.305mm 0.61mm DFN3X3-8 1.575mm 2.146mm

Copyright  ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 APL3225 www.anpec.com.tw9

Package Information

MIN. MAX. 0.80 0.00 0.18 0.30 1.00 1.60 0.05 0.60 A b D E e L MILLIMETERS A3 0.20 REF TDFN2x2-8 0.30 0.45 1.00

0.008 REF

MIN. MAX. INCHES 0.031 0.000 0.007 0.012 0.039 0.063 0.024 0.012 0.018 0.70 0.039 0.028 0.002 0.50 BSC 0.020 BSC SYMBOL 1.90 2.10 0.075 0.083 1.90 2.10 0.075 0.083 D E A b E2L e Pin 1 Corner Note : 1. Follow from JEDEC MO-229 WCCD-3.

Copyright  ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 APL3225 www.anpec.com.tw10 S Y M B O L MIN. MAX. 1.00 0.00 0.25 0.35 1.90 2.40 0.05 1.40 A b D E e L MILLIMETERS A3 0.20 REF DFN3x3-8 0.30 0.50 1.75 MIN. MAX. INCHES 0.039 0.000 0.010 0.014 0.075 0.094 0.055 0.012 0.020 0.80 0.069 0.031 0.002 0.65 BSC 0.026 BSC 0.20 0.008K 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122 D E Pin 1 A A3 b Pin 1 Corner e E2KL

Copyright  ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 APL3225 www.anpec.com.tw11 Devices Per Unit Package Type Unit Quantity TDFN2x2-8 Tape & Reel 3000 DFN3x3-8 Tape & Reel 3000 Carrier Tape & Reel Dimensions H A d A AB W F T P0OD0 B SECTION B-B SECTION A-A OD1 Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 TDFN2x2-8 Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 DFN3x3-8 (mm)

Copyright  ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 APL3225 www.anpec.com.tw12 Taping Direction Information TDFN2x2-8 USER DIRECTION OF FEED DFN3x3-8 USER DIRECTION OF FEED

Copyright  ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 APL3225 www.anpec.com.tw13 Classification Profile

Copyright  ANPEC Electronics Corp. (Tsmax to TP) 3 °C/second max. 3°C/second max. Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. Time 25°C to peak temperature 6 minutes max. 8 minutes max.

  • Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.

** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 2. Pb-free Process – Classification Temperatures (Tc) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

Copyright  ANPEC Electronics Corp. Rev. A.1 - Nov., 2012 APL3225 www.anpec.com.tw15 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838