APL 5916

APL5916 ANPEC | Alldatasheet

Document overview

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Technical content

Features

The APL5916 is a 7A ultra low dropout linear regulator. This product is specifically designed to provide well supply volatage for motherboards and VGA card applications. The IC needs two supply voltages, a con- trol voltage for the circuitry, and a main supply voltage for power conversion, to reduce power dissipation and provide extremely low dropout. The APL5916 integrates many functions into a single package. A Power-On-Reset (POR) circuit monitors both supply voltages to prevent wrong operations. Thermal shutdown and current limit functions protect the de- vice against thermal and current over-loads. POK indi- cates that the output status with time delay which is set internally. It can control other converter for power sequence. The APL5916 can be enabled by other power system. Pulling and holding the EN pin below 0.3V shuts off the output. The APL5916 is available in SOP-8P package which fea- tures small size as SOP-8 and an Exposed Pad to reduce the junction-to-case resistance, being applicable in 2~2.6W applications.

Applications

SOP-8P (Top View) General Description (connected to the VIN plane for better heat dissipation) = Exposed Pad· Note Book PC Applications

• Motherboard Applications
• VGA Card Applications EN POK VCNTL VIN GND FB VOUT VOUT VIN

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw2 Ordering and Marking Information Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Symbol Parameter Rating Unit VCNTL VCNTL Supply Voltage (VCNTL to GND) -0.3 ~ 7 V VIN VIN Supply Voltage (VIN to GND) -0.3 ~ 3.9 V VI/O EN and FB to GND -0.3 ~ VCNTL+0.3 V VPOK POK to GND -0.3 ~ 7 V PD Power Dissipation 3 W TJ Junction Tempera ture 150 oC TSTG Storage Temperature -65 ~ 150 oC TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC Absolute Maximum Ratings (Note 1) Thermal Characteristics Symbol Parameter Typical Value Unit θ JA Junction -to-Ambient Thermal Resistance in Free Air (Note 2) SOP-8P 38 oC/W θ JC Junction -to-Case Thermal Resistance (Note 3) SOP-8P 14 oC/W Note 2 : θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8P is soldered directly on the PCB. Note 3 : The “Thermal Pad Temperature” is measured on the PCB copper area connected to the thermal pad of package. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VIN Measured Point PCB Copper Package Code KA : SOP-8P Operating Ambient Temperature Range I : -40 to 85 oC Handing Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APL5916 Handling Code Temperature Range Package Code APL5916APL5916 KA : XXXXX - Date Code Assembly Material XXXXX

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw3 Recommended Operating Conditions Symbol Parameter Range Unit VCNTL VCNTL Supply Voltage 4.5 ~ 6 V VIN VIN Supply Voltage 1.0 ~ 3.5 V VOUT Output Voltage, VCNTL=5.0±5% 0.8 ~ VIN-0.2 V IOUT VOUT Output Current 0 ~ 7 A TJ Junction Temperature -40 ~ 125 oC

Electrical Characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit SUPPLY CURRENT ICNTL VCNTL Supply Current EN = VCNTL, VFB is well regulated 0.4 1 2 mA ISD VCNTL Shuntdown Current EN = GND - 280 380 µA POWER-ON-RESET VCNTL POR Threshold VCNTL Rising 2.7 2.9 3.1 V VCNTL POR Hysteresis - 0.4 - V VIN POR Threshold VIN Rising 0.8 0.9 1.0 VIN POR Hysteresis - 0.5 - V OUTPUT VOLTAGE VREF Reference Voltage FB =VOUT - 0.8 - V Output Voltage Accuracy IOUT=0A ~ 7A, TJ= -40~125oC -1.5 - +1.5 % Line Regulation VCNTL=4.5 ~ 6V -1.5 - +1.5 mV/V Load Regulation IOUT=0A ~ 7A - 0.06 0.15 % DROPOUT VOLTAGE IOUT = 7A, VCNTL=5V, TJ= 25oC - 0.11 0.14 V Dropout Voltage IOUT = 7A, VCNTL=5V, TJ= -40~125oC - - 0.2 V PROTECTION VCNTL=5V, TJ= 25oC 8 10 12 A ILIM Current Limit VCNTL=5V, TJ= -40 ~ 125oC 7.2 - - A TSD Thermal Shutdown Temperature TJ Rising - 150 - oC Thermal Shutdown Hysteresis - 50 - oC Under-Voltage Threshold VFB Falling - 0.4 - V ENABLE AND SOFT-START EN Logic High Threshold Voltage VEN Rising 0.3 0.4 0.5 V EN Hysteresis - 30 - mV EN Pin Pull-Up Current EN=GND - 10 - µA TSS Soft-Start Interval - 2 - ms Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.25V, VOUT = 1.05V and TA = -40 to 85°C, unless otherwise specified. Typical values refer to TA = 25°C.

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw4 Electrical Characteristics (Cont.) APL5916 Symbol Parameter Test Conditions Min. Typ. Max. Unit POWER-OK AND DELAY VPOK POK Threshold Voltage for Power OK VFB Rising 90% 92% 94% VREF VPNOK POK Threshold Voltage for Power Not OK VFB Falling 79% 81% 83% VREF POK Low Voltage POK sinks 5mA - 0.25 0.4 V TDELAY POK Delay Time 1 3 10 ms Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.25V, VOUT = 1.05V and TA = -40 to 85°C, unless otherwise specified. Typical values refer to TA = 25°C.

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw5 Typical Operating Characteristics VCNTL Supply Current vs. Junction Tem- perature VCNTL Supply Current, ICNTL (mA) Junction Temperature (°C) Reference Voltage vs. Junction Tem- perature Reference Voltage, VREF (mV) Junction Temperature (°C) Junction Temperature (°C) Output Current, IOUT(A) POK Delay Time vs. Junction Temperature POK Delay Time (ms) VIN Dropout Voltage vs. Output Current VIN Dropout Voltage (mV) VIN Dropout Voltage vs. Output Current VIN Dropout Voltage (mV) Output Current, IOUT(A) VIN Dropout Voltage vs. Output Current VIN Dropout Voltage (mV) Output Current, IOUT(A) 0 1 2 3 4 5 6 70 100 120 140 VCNTL = 5V, VOUT = 1.5V T TJ=0oC TJ=-25oC TJ=50oC TJ=125oC TJ=75oC TJ=25oC 0 1 2 3 4 5 6 7 100 120 140 160 TJ=125oC TJ=75oC TJ=25oC T TJ=0oC TJ=-25oC TJ=50oC VCNTL = 5V, VOUT = 2.5V 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -50 -25 0 25 50 75 100 125 VCNTL = 5V -50 -25 0 25 50 75 100 125 0.792 0.794 0.796 0.798 0.800 0.802 0.804 0.806 0.808 VCNTL = 5V -50 -25 0 25 50 75 100 125 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 VCNTL = 5V, VOUT = 1.05V TJ=125oC TJ=75oC TJ=25oC T TJ=0oC TJ=-25oC TJ=50oC 100 120 140 0 1 2 3 4 5 6 7

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw6 Typical Operating Characteristics (Cont.) Junction Temperature (°C) Frequency(Hz) Current-Limit vs. Junction Temperature POK Delay Time (ms) VIN PSRR vs. Frequency VIN PSRR 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 -50 -25 0 25 50 75 100 125 VCNTL = 5V 1000 10000 100000 1000000 -70 -60 -50 -40 -30 -20 -10 IIOUT = 3A IOUT = 1A I IOUT = 5A IOUT = 7A VINPK-PK = 50mV VCNTL = 5V, VIN = 1.25V VOUT = 1.05V, COUT = 22mF VCNTL PSRR vs. Frequency VCNTL PSRR Frequency(Hz) -80 -70 -60 -50 -40 -30 -20 -10 1000 10000 100000 1000000 VCNTL = 5V VIN = 1.25V VOUT = 1.05V COUT = 22µF VCNTLPK-PK = 50mV IOUT = 3A IOUT = 1A IOUT = 5A IOUT = 7A

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw7 1. Load transient Response

1.1 Using an Output Capacitor with ESR≥ 18mW

• COUT = 150µF/6.3V (ESR = 25mΩ ), CIN = 22µF/6.3V - IOUT = 10mA to 7A to 10mA, Rise time = Fall time = 5µs IOUT = 10mA -> 7A IOUT = 10mA -> 7A ->10mA IOUT = 7A -> 10mA VOUT IOUT VOUT IOUT VOUT IOUT CH1 : VOUT, 50mV/Div CH2 : IOUT, 2A/Div Time : 5µs/Div CH1 : VOUT, 50mV/Div CH2 : IOUT, 2A/Div Time : 100µs/Div CH1 : VOUT, 50mV/Div CH2 : IOUT, 2A/Div Time : 5µs/Div Operating Waveforms

1.2 Using an MLCC as the Output Capacitor

• COUT = 22µF/6.3V (ESR = 3mΩ ), CIN = 22µF/6.3V - IOUT = 10mA to 7A to 10mA, Rise time = Fall time = 5µs IOUT = 10mA -> 7A IOUT = 10mA -> 7A ->10mA IOUT = 7A -> 10mA VOUT IOUT VOUT IOUT VOUT IOUT CH1 : VOUT, 100mV/Div CH2 : IOUT, 2A/Div Time : 5µs/Div CH1 : VOUT, 100mV/Div CH2 : IOUT, 2A/Div Time : 100µs/Div CH1 : VOUT, 100mV/Div CH2 : IOUT, 2A/Div Time : 5µs/Div R1=1kΩ , R2=3.2kΩ , C1=33nF R1=124kΩ , R2=396.8kΩ , C1=36pF

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw8 VIN VOUT VCNTL VPOK 2. Power ON and Power OFF - VIN = 1.25V, VCNTL = 5V,VOUT = 1.05V - COUT = 22µF/6.3V (ESR = 3mΩ) , CIN = 22µF/6.3V Operating Waveforms (Cont.) Power ON Power OFF VIN VOUT VCNTL VPOK CH1 : VIN, 1V/div CH2 : VOUT, 1V/div CH3 : VPOK, 1V/div CH4 : VCNTL, 2V/div Time: 5ms/div CH1 : VIN, 1V/div CH2 : VOUT, 1V/div CH3 : VPOK, 1V/div CH4 : VCNTL, 2V/div Time: 500ms/div VEN VOUT IOUT VPOK 3. Shutdown and Enable - VIN = 1.25V, VCNTL = 5V,VOUT = 1.05V - COUT = 22µF/6.3V (ESR = 3mΩ) , CIN = 22µF/6.3V Enable Shutdown CH1 : VEN, 5V/div CH2 : VOUT, 1V/div CH3 : VPOK, 1V/div CH4 : IOUT, 2A/div Time: 1ms/div CH1 : VEN, 5V/div CH2 : VOUT, 1V/div CH3 : VPOK, 1V/div CH4 : IOUT, 2A/div Time: 10µs/div VEN VOUT IOUT VPOK VPOK

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw9 VIN VOUT POK Delay VPOK 4. POK Delay - VIN = 1.25V, VCNTL = 5V,VOUT = 1.05V - COUT = 22µF/6.3V (ESR = 3mΩ) , CIN = 22µF/6.3V Operating Waveforms (Cont.) CH1 : VIN, 1V/div CH2 : VOUT, 1V/div CH3 : VPOK, 1V/div Time: 2ms/div Block Diagram GND VOUT VINVCNTL Current Limit Thermal Limit EN VREF 0.8V FB 90% VREF Delay POK Power-On- Reset Soft-Start and Control Logic 0.4V UV EAMP POK

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw10 Typical Application Circuit 1. Using an Output Capacitor with ESRl18mW 2. Using an MLCC as the Output Capacitor COUT (µF) VOUT (V) R1 (kΩ ) R2 (kΩ ) C1 (pF) 1.2 120 240 36 1.5 120 137.14 39 22 1.8 105 184 39 1.05 240 768 39 1.2 187 374 47 1.5 180 205.71 47 44 1.8 162 129.6 47 VCNTL +5V VOUT +1.05V / 7A CCNTL 1µF VIN +1.25V GND VOUT VCNTL POK VIN CIN 22µF COUT 150µF EN Enable EN POK APL5916 33nF (in the range of 12 ~ 48nF) VOUT 4 FB 2 3.2k VCNTL +5V VOUT +1.05V / 7A VIN +1.25V GND VOUT VCNTL POK VIN CIN 22µF COUT 22µF EN Enable EN POK APL5916 124k 36pF VOUT 4 FB 2 396.8k 22µF/ ECJ3YBOJ226M Panasonic GRM21BR60J226M Murata CCNTL 1µF

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw11 Typical Application Circuit (Cont.) +5V 1µF 470µF x2 1000µF x2 3.3µH APM2014NUGATE LGATE 4 VCC GND OCSET7 PHASE 8 APM2014N 1µF APW7057 FB6 BOOT 1 1N4148 0.1µF 1.125k 8.2k 0.1µFQ3 Shutdown 2.2 470pF 1µH 47µF VCNTL +5V VOUT +1.05V/7A CVCNTL 1µF VIN +1.25V GND VOUT VCNTL POKVIN CIN 22µF COUT 150µF EN Enable EN POK 1k7 APL5916 33nF VOUT 4 FB 2 3.2k

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw12 Pin Description Enable control pin. Pulling and holding this pin below 0. 3V shuts down the output. When re-enabled, the IC un- dergoes a new soft-start cycle. When leave this pin open, an internal current source 10µA pulls this pin up to VCNTL voltage, enabling the regulator.  +⋅= R110.8 VOUT (V) GND (Pin 1) Ground pin of the circuitry. All voltage levels are mea- sured with respect to this pin. FB (Pin 2) Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. The output voltage set by the resistor divider is determined by: where R1 is connected from VOUT to FB with Kelvin sens- ing and R2 is connected from FB to GND. A bypass ca- pacitor may be connected with R1 in parallel to im- prove load transient response. VOUT (Pin 3, 4) Output of the regulator. Please connect Pin 3 and 4 to- gether using wide tracks. It is necessary to connect a output capacitor with this pin for closed-loop compensa- tion and improving transient response. VIN (Pin 5) and Exposed Pad Main supply input pins for power conversions. The Ex- posed Pad provides a very low impedance input path for the main supply voltage. Please tie the Exposed Pad and VIN Pin (Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for Power-On-Reset purpose. VCNTL (Pin 6) Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply voltage provides the bias for the control circuitry. The voltage at this pin is monitored for Power-On-Reset purpose. POK (Pin 7) Power-OK signal output pin. This pin is an open-drain output used to indicate status of output voltage by sens- ing FB voltage. This pin is pulled low when the rising FB voltage is not above the VPOK threshold or the falling FB voltage is below the VPNOK threshold, indicating the output is not OK. EN (Pin 8)

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw13 Function Description Power-On-Reset A Power-On-Reset (POR) circuit monitors both input volt- ages at VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates that a soft-start pro- cess after the two supply voltages exceed their rising POR threshold voltages during powering on. The POR function also pulls low the POK pin regardless the output voltage when the VCNTL voltage falls below it’s falling POR threshold. Internal Soft-Start An internal soft-start function controls rise rate of the out- put voltage to limit the current surge at start-up. The typi- cal soft-start interval is about 2ms. Output Voltage Regulation An error amplifier working with a temperature-compen- sated 0.8V reference and an output NMOS regulates out- put to the preset voltage. The error amplifier is designed with high bandwidth and DC gain provides very fast tran- sient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output NMOS which provides load current from VIN to VOUT. Current-Limit The APL5916 monitors the current via the output NMOS and limits the maximum current to prevent load and APL5916 from damages during overload or short-circuit conditions. Under-Voltage Protection (UVP) The APL5916 monitors the voltage on FB pin after soft- start process is finished. Therefore, the UVP is disable during soft-start. When the voltage on FB pin falls below the under-voltage threshold, the UVP circuit shuts off the output immediately. After a while, the APL5916 starts a new soft-start to regulate output. Thermal Shutdown A thermal shutdown circuit limits the junction tempera- ture of APL5916. When the junction temperature exceeds +150°C, a thermal sensor turns off the output NMOS, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start cycle after the junction temperature cools by 50°C, resulting in a pulsed output during continuous thermal overload conditions. The thermal shutdown is designed with a 50oC hysteresis to lower the average junction tempera- ture during continuous thermal overload conditions, ex- tending lifetime of the device. For normal operation, device power dissipation should be externally limited, so junction temperatures will not exceed +125°C. Enable Control The APL5916 has a dedicated enable pin (EN). A logic low signal (VEN< 0.3V) applied to this pin shuts down the output. Following a shutdown, a logic high signal re-en- ables the output through initiation of a new soft-start cycle. Left open, this pin is pulled up by an internal current source (10µA typical) to enable operation. It’s not necessary to use an external transistor to save cost. Power-OK and Delay The APL5916 indicates the status of the output voltage by monitoring the feedback voltage (VFB) on FB pin. As the VFB rises and reaches the rising Power-OK threshold (VPOK), an internal delay function starts to perform a de- lay time. At the end of the delay time, the IC turns off the internal NMOS of the POK to indicate the output is OK. As the VFB falls and reaches the falling Power-OK threshold (VPNOK), the IC immediately turns on the NMOS of the POK to indicate the output is not OK without a delay time.

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw15 Feedback Network (Cont.) Application Information (Cont.) (5) .. R1 V37.51ESR 20011.5C1 )(k OUT(V) )(m (pF)   +⋅≥ ΩΩ C200ESRC1 )(k F)OUT( )(m(pF) Ω µ Ω ⋅+= (7) .. R1 V37.51C)34ESR(0.17C1 )(k OUT(V) F)OUT()(m(pF)  µΩ (8) .. CESR V1.250.033C1 F)OUT()(m )(k OUT(V) (pF) µΩ Ω ⋅⋅  ⋅+≥

• Condition 2 : Middle ESR - Calculate the R1 as the following equation : 6000R1 OUT(V) )(m )(k +⋅−= Ω Ω Select a proper R1(selected) to be a little larger than the calculated R1. - Calculate the C1 as the following equation: Where R1=R1(selected) Select a proper C1(selected) to be a little smaller than the calculated C1. - The C1 calculated from equation (4) must meet the following equation: Where R1=R1(calculated) from equation (3) If the C1(calculated) can not meet the equation (5), please use the Condition 3. - Use equation (2) to calculate the R2.
• Condition 3 : Low ESR (eg. Ceramic Capacitors) - Calculate the R1 as the following equation: Select a proper R1(selected) to be a little larger than the calculated R1. The minimum selected R1 is equal to 1kW when the calculated R1 is smaller than 1k or negative. - Calculate the C1 as the following equation: (6) .. V37.5C)1175ESR(5.9R1 OUT(V)F)OUT()(m)(k ⋅−⋅+⋅= µΩΩ Where R1=R1(selected) Select a proper C1(selected) to be a little smaller than the calculated C1. - The C1 calculated from equation (7) must meet the following equation : Where R1=R1(calculated) from equation (6) If the C1(calculated) can not meet the equation (8), please use the Condition 2. - Use equation (2) to calculate the R2. The reason to have three conditions described above is to optimize the load transient responses for all kinds of the output capacitor. For stability only, the Condition 2, regardless of equation (5), is enough for all kinds of output capacitor. PCB Layout Consideration (See Figure 2) 1. Please solder the Exposed Pad and VIN together on the PCB. The main current flow is through the exposed pad. 2. Please place the input capacitors for VIN and VCNTL pins near pins as close as possible. 3. Ceramic decoupling capacitors for load must be placed near the load as close as possible. 4. To place APL5916 and output capacitors near the load is good for performance. 5. The negative pins of the input and output capaci-tors and the GND pin of the APL5916 are connected to the ground plane of the load. 6. Please connect PIN 3 and 4 together by a wide track. 7. Large current paths must have wide tracks. 8. See the Typical Application (see next page Figure 2) - Connect the one pin of the R2 to the GND of APL5916 - Connect the one pin of R1 to the Pin 3 of APL5916 - Connect the one pin of C1 to the Pin 3 of APL5916 VCNTL VOUT CCNTL VIN GND VOUT VCNTL VIN CIN COUT APL5916 R1C1 VOUT FB Load Figure 2

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw16 Application Information (Cont.) See Figure 3. The SOP-8P is a cost-effective package featuring a small size like a standard SOP-8 and a bot- tom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications. The exposed pad must be soldered to the top VIN plane. The copper of the VIN plane on the Top layer conducts heat into the PCB and air. Please enlarge the area to reduce the case-to-ambient resistance (θ CA). Figure 3 Recommended Minimum Footprint 0.212 0.072 0.050 0.024 1 2 3 4 8 7 6 5 0.118 0.138 Unit : Inch Exposed PadDie Top VIN plane PCB Ambient Air 118 mil 102 mil SOP-8P Top VOUT plane Thermal Consideration

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw17

Package Information

0.020 0.010 0.020 0.050 0.006 0.063 MAX. 0.40L E e h 0.25 D c b 0.17 0.31 0.0161.27 0.50

1.27 BSC

0.51 0.25

0.050 BSC

0.010 0.012 0.007 MILLIMETERS MIN. SYMB OL A 0.00 1.25 SOP-8P MAX. 0.15 1.60 MIN. 0.000 0.049 INCHES D1 2.25 0.098 2.00 0.079E2 3.50 3.00 0.138 0.118 8o 0o 8o0o h X 45° D e E SEE VIEW A cb E2THERMAL PAD A VIEW A 0.25 SEATING PLANE GAUGE PLANE A1 A2 Inter-lead flash and protrusions shall not exceed 10 mil per side. Note : 1. Follow JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. 4.80 5.00 5.80 6.20 3.80 4.00 0.2440.228 0.1570.150 0.1970.189

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw18 Carrier Tape & Reel Dimensions A AB W F T P0OD0 B SECTION B-B SECTION A-A OD1 H A d Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 SOP-8P (mm) Devices Per Unit Package Type Unit Quantity SOP-8P Tape & Reel 2500

Copyright  ANPEC Electronics Corp. Rev. A.3 - Jan., 2009 APL5916 www.anpec.com.tw19 Reflow Condition (IR/Convection or VPR Reflow) t 25 C to Peak tp Ramp-up tL Ramp-down ts Preheat Tsmax Tsmin TL TP Temperature Time Critical Zone TL to TP Test item Method Description SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C PCT JESD-22-B,A102 168 Hrs, 100%RH, 121°C TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V Latch-Up JESD 78 10ms, 1tr > 100mA Reliability Test Program Taping Direction Information SOP-8P USER DIRECTION OF FEED

Copyright  ANPEC Electronics Corp. (TL to TP) 3°C/second max. 3°C/second max. Ramp-down Rate 6°C/second max. 6°C/second max. Time 25°C to Peak Temperature 6 minutes max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. Table 2. Pb-free Process – Package Classification Reflow Temperatures Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures