APDS-9309

APDS-9309 AVAGO | Alldatasheet

Document overview

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Technical content

Features

• Approximate the human-eye response
• Precise Illuminance measurement under diverse light - ing conditions
• Programmable Interrupt Function with User-Defined Upper and Lower Threshold Settings
• 16-Bit Digital Output with I2C Fast-Mode at 400 kHz
• Programmable Analog Gain and Integration Time
• Miniature ChipLED Package o Height – 0.65 mm o Length – 2.00 mm o Width – 2.00 mm
• 50/60 Hz Lighting Ripple Rejection
• Low 2.5 V Input Voltage and 1.8 V Digital Output
• Low Active Power (0.6 mW Typical) with Power Down Mode
• RoHS Compliant Application Support Information The Application Engineering Group is available to assist you with the application design associated with APDS-9309 ambient light photo sensor module. You can contact them through your local sales representatives for additional details.

Description

The APDS-9309 is a low-voltage Digital Ambient Light Photo Sensor that converts light intensity to digital signal output capable of direct I 2C-bus interface. Each device consists of one broadband photodiode (visible plus infrared) and one infrared photodiode. Two integrat- ing ADCs convert the photodiode currents to a digital output that represents the irradiance measured on each channel. This digital output can be input to a micropro - cessor where illuminance (ambient light level) in lux is derived using an empirical formula to approximate the human-eye response.

Applications

• Detection of ambient light to control display backlighting o Mobile devices – Cell phones, PDAs, PMP o Computing devices – Notebooks, Tablet PC, Key board o Consumer devices – LCD Monitor, Flat-panel TVs, Video Cameras, Digital Still Camera
• Automatic Residential and Commercial Lighting Management
• Automotive instrumentation clusters.
• Electronic Signs and Signals

Ordering Information

Part Number Packaging Type Package Quantity APDS-9309 Tape and Reel 6-pins Chipled package 5000 per reel Functional Block Diagram IO Pins Configuration Table Pin Symbol Description

1 SCL Serial Clock

2 INT Interrupt

3 SDA Serial Data

4 VDD Voltage Supply

5 ADDR SEL Address Select

6 GND Ground

Address SelectCh0 (Visible + IR) Ch1 (IR) SCL SDA ADDR SEL VDD INT ADC ADC GND

Parameter Symbol Min Max Unit Supply voltage VDD – 3.8 V Digital output voltage range VO -0.5 3.8 V Digital output current IO -1 20 mA Storage temperature range Tstg -40 85 ºC ESD tolerance human body model – 2000 V Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Condition Supply Voltage VDD 2.4 2.5 3.0 V Operating Temperature Ta -30 – 85 ºC SCL, SDA input low voltage VIL -0.5 – 0.58 V SCL, SDA input high voltage VIH 1.13 – 3.6 V 2.4 ≤ VDD ≤ 2.6 1.25 – 3.6 V 2.4 ≤ VDD ≤ 3.0

Electrical Characteristics

Parameter Symbol Min Typ Max Unit Conditions Supply current IDD – 0.24 3.2 0.6 mA μA Active Power down INT, SDA output low voltage VOL 0 0.4 0.6 V V 3 mA sink current 6 mA sink current Leakage current ILEAK -5 – 5 μA Operating Characteristics, High Gain (16X), VDD = 2.5 V, Ta = 25° C, (unless otherwise noted) (see Notes 1, 2, 3, 4) Parameter Symbol Channel Min Typ Max Unit Conditions Oscillator frequency fosc 690 735 780 kHz Dark ADC count value Ch0 0 4 counts Ee = 0, Tint = 402 ms Ch1 0 4 Full scale ADC count value Ch0 65535 counts Tint > 178 ms Ch1 65535 Ch0 37177 Tint = 101 ms Ch1 37177 Ch0 5047 Tint = 13.7 ms Ch1 5047 ADC count value Ch0 750 1000 1250 counts λp = 640 nm, Tint = 101 ms Ch1 200 Ee = 36.3 μW/cm2 Ch0 700 1000 1300 λp = 850 nm, Tint = 101 ms Ch1 820 Ee = 60.2 μW/cm2

Notes: 1. Integration time Tint, is dependent on internal oscillator frequency (fosc) and on the integration field value in the timing register as described in the Register Set section. For nominal fosc = 735 kHz, nominal Tint = (number of clock cycles)/fosc. Field value 00: Tint = (11 • 918)/fosc = 13.7 ms Field value 01: Tint = (81 • 918)/fosc = 101 ms Field value 10: Tint = (322 • 918)/fosc = 402 ms Scaling between integration times vary proportionally as follows: 11/322 = 0.034 (field value 00), 81/322 = 0.252 (field value 01), and 322/322 = 1 (field value 10). 2. Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods and also by a 2-count offset. Full scale ADC count value = ((number of clock cycles)/2 - 2) Field value 00: Full scale ADC count value = ((11 • 918)/2 - 2) = 5047 Field value 01: Full scale ADC count value = ((81 • 918)/2 - 2) = 37177 Field value 10: Full scale ADC count value = 65535, which is limited by 16 bit register. This full scale ADC count value is reached for 131074 clock cycles, which occurs for Tint = 178 ms for nominal fosc = 735 kHz. 3. Low gain mode has 16x lower gain than high gain mode: (1/16 = 0.0625). Parameter † Min. Typ. Max. Unit t(CONV) Conversion time 12 100 400 ms f(SCL) Clock frequency – – 400 kHz t(BUF) Bus free time between start and stop condition 1.3 – – μs t(HDSTA) Hold time after (repeated) start condition. After this period, the first clock is generated. 0.6 – – μs t(SUSTA) Repeated start condition setup time 0.6 – – μs t(SUSTO) Stop condition setup time 0.6 – – μs t(HDDAT) Data hold time 0 – 0.9 μs t(SUDAT) Data setup time 100 – – ns t(LOW) SCL clock low period 1.3 – – μs t(HIGH) SCL clock high period 0.6 – – μs tF Clock/data fall time – – 300 ns tR Clock/data rise time – – 300 ns Cj Input pin capacitance – – 10 pF † Specified by design and characterization; not production tested. Computed Lux = In open air (no window) above the sensor condition, the Lux value can be computed from the CH0 and Ch1 ADC values per below: In Incandescent light source: In Non-Incandescent light source: where Lighsource_Ratio=0.55 Lux_factor_Incan=24.01 Lux_factor_Non_Incan=170.18 Integration Time = 13.7ms, 101ms or 402ms GAIN = 1 or 16 When CH0 (GAIN ×Integration Time) > Lightsource_Ratio CH1 CH0 × Lux_factor_Incan CH0 (GAIN ×Integration Time) Computed Lux = × Lux_factor_Non_Incan When ≤ Lightsource_RatioCH1 CH0

results of the ADC conversions. The register set is summarized in Table 2. Table 2. Register Address

Table 3. The command register defaults to 00h at power on. Table 3. Command Register CMD 7 Select command register. Must write as 1. CLEAR 6 Interrupt clear. Clears any pending interrupt. This bit is a write–one–to–clear bit. It is self clearing. WORD 5 I2C Write/Read Word Protocol. 1 indicates that this I2C transaction is using either the I2C Write Word or Read Word protocol. Reserved 4 Reserved. Write as 0. ADDRESS 3:0 Register Address. Table 4. Control Register Reserved 7:2 Reserved. Write as 0. POWER 1:0 Power up/power down. By writing a 03h to this register, the device is powered up. By writing a 00h to this register, the device is powered down.

is provided that controls both ADC channels. The TIMING register defaults to 02h at power on. Table 5. Timing Register Reserved 7-5 Reserved. Write as 0. GAIN 4 Switches gain between low gain and high gain modes. Writing a 1 selects high gain (16x). MANUAL 3 Manual timing control. Writing a 1 begins an integration cycle. Writing a 0 stops an integration cycle. NOTE: This field only has meaning when INTEG = 11. It is ignored at all other times. Resv 2 Reserved. Write as 0. INTEG 1:0 Integrate time. This field selects the integration time for each conversion. page 4 for detailed information regarding how the scale values were obtained. Table 6. Integration Time simply writing a 0 to the same bit field.

combined to form a 16-bit threshold value. The interrupt threshold registers default to 00h on power up. Table 7. Interrupt Threshold Register THRESHHIGHHIGH registers) can be written together to set the 16-bit ADC value in a single transaction. example, if N is equal to 10 and the integration time is 402 ms, then the total time is approximately 4 seconds. COMMAND register with the CLEAR bit set. Note: Interrupts are based on the value of Channel 0 only. Table 8. Interrupt Control Register Reserved 7:6 Reserved. Write as 0. INTR 5:4 INTR Control Select. This field determines mode of interrupt logic according to Table 9, below.

Table 9. Interrupt Control Select

00 Interrupt output disabled

01 Level Interrupt

Table 10. Interrupt Persistence Select

0000 Every ADC cycle generates interrupt

0001 Any value outside of threshold range

read-only register, whose value never changes. Table 11. ID Register

data registers are read–only and default to 00h on power up. Table 12. ADC Channel Data Registers the reading of the lower and upper registers.

Note: 1. All linear dimensions are in millimeters. PCB Pad Layout Note: 1. All dimensions are in millimeters. Package Outline - APDS-9309 0.10 0.15 2.20 0.90 1.70 0.25 0.40 0.40 1 2 3 456 PINOUT 1- SCL 2- INT 3- SDA 4- VDD 5- ADDR SEL 6- GND 2 ±0.10 2 ±0.10 Pin #1 0.30 ±0.05 (x6) 0.75 ±0.075 (x6) 0.10 ±0.10

All dimensions unit: mm Reel Dimensions TAPE WIDTH T W1 W2 W3 8 MM 3 ± 0.50 8.4 + 1.5 - 0.0 14.4 MAX 7.9 MIN

10.9 MAX

13 ± 0.2 Arbor Hole ∅180 ± 0.50 Diameter 60 ± 0.50 Hub Dia. Access HoleAccess Hole T Tape Start Slot T Tape Start Slot Access Hole Measured at Outer Edge Measured at Hub Measured at Hub 20.2 Min. CCD/KEACO MADE IN MALAYSIA Front View Back View Side View 4 ±0.10 3.50 ±0.05 +0.30 -0.10 2.18 ±0.05 SECTION B-B

5 Deg Max

0.254 ±0.020 0.83 ±0.05 SECTION A-A A A Ø 1 ±0.25

Recommended Storage Conditions Storage Temperature 10° C to 30° C Relative Humidity Below 60% RH Time from Unsealing to Soldering After removal from the bag, the parts should be soldered within seven days if stored at the recommended storage conditions. When MBB (Moisture Barrier Bag) is opened and the parts are exposed to the recommended storage conditions more than seven days the parts must be baked before reflow to prevent damage to the parts. Baking conditions If the parts are not stored per the recommended storage conditions they must be baked before reflow to prevent damage to the parts. Package Temp. Time In Reels 60°C 48 hours In Bulk 100°C 4 hours Note: Baking should only be done once. Moisture Proof Packaging Chart All APDS-9309 options are shipped in moisture proof package. Once opened, moisture absorption begins. This part is compliant to JEDEC Level 3. UNITS IN A SEALED MOISTURE-PROOF PACKAGE ENVIRONMENT LESS THAN 30° C AND LESS THAN 60% RH PACKAGE IS OPENED (UNSEALED) PACKAGE IS OPENED LESS THAN 168 HOURS NO BAKING IS NECESSARY PERFORM RECOMMENDED BAKING CONDITIONS YES YES NO NO BAKING CONDITIONS CHART

Heat Up P1, R1 25° C to 150° C 3°C/s Solder Paste Dry P2, R2 150° C to 200° C 100 s to 180 s Solder Reflow P3, R3 200° C to 260° C 3°C/s P3, R4 260° C to 200° C -6°C/s Cool Down P4, R5 200° C to 25° C -6°C/s Time maintained above liquidus point, 217° C > 217° C 60 s to 90 s Peak Temperature 260° C – Time within 5° C of actual Peak Temperature – 20 s to 40 s Time 25° C to Peak Temperature 25° C to 260° C 8 mins The reflow profile is a straight-line representation of a nominal temperature profile for a convective reflow solder process. The temperature profile is divided into four process zones, each with different DT/Dtime tem - perature change rates or duration. The DT/Dtime rates or duration are detailed in the above table. The temperatures are measured at the component to printed circuit board connections. In process zone P1, the PC board and component pins are heated to a temperature of 150° C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 3° C per second to allow for even heating of both the PC board and component pins. Process zone P2 should be of sufficient time duration (100 to 180 seconds) to dry the solder paste. The temperature is raised to a level just below the liquidus point of the solder. Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 260° C (500° F) for optimum results. The dwell time above the liquidus point of solder should be between 60 and 90 seconds. This is to assure proper coalescing of the solder paste into liquid solder and the formation of good solder connections. Beyond the recommended dwell time the intermetallic growth within the solder con- nections becomes excessive, resulting in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25° C (77° F) should not exceed 6° C per second maximum. This limitation is necessary to allow the PC board and component pins to change dimensions evenly, putting minimal stresses on the component. It is recommended to perform reflow soldering no more than twice. Recommended Reflow Profile 50 100 150 200 250 300 t-TIME (SECONDS) 120 150 180 200 230 255 T - TEMPERATURE (°C) R3 R4 217 MAX 260°C 60 sec to 90 sec Above 217°C HEAT UP SOLDER PASTE DRY SOLDER REFLOW COOL DOWN

For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved. AV02-3689EN - November 13, 2015 The power supply lines must be decoupled with a 0.1 μF capacitor placed as close to the device package as possible, as shown in Figure B1. The bypass capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents caused by internal logic switching. Pull-up resistors, R1 and R2, maintain the SDA and SCL lines at a high level when the bus is free and ensure the signals are pulled up from a low to a high level within the required rise time. For a complete description of I2C maximum and minimum R1 and R2 values, please review the I 2C Specifi- cation at http://www.semiconductors.philips.com. A pull-up resistor, R3, is also required for the interrupt (INT), which functions as a wired-AND signal in a similar fashion to the SCL and SDA lines. A typical impedance value between 10 kΩ and 100 kΩ can be used. Appendix A: Application circuit Figure A1. Application circuit for APDS-9309 APDS-9309 VDD VIO 0.1 µF ADDR_SEL SDA SCL MCU R1 R2 R3 Note: ADDR_SEL Float : Slave address is 0111001 VDD SCLGND INT SDA ADDR_SEL INT