APDS-9303-020

APDS-9303 AVAGO | Alldatasheet

Document overview

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• PDF pages: 21

Technical content

Features

• Approximate the human-eye response
• Precise Illuminance measurement under diverse light - ing conditions
• Programmable Interrupt Function with User-Defined Upper and Lower Threshold Settings
• 16-Bit Digital Output with SMBus at 100 kHz
• Programmable Analog Gain and Integration Time
• Miniature ChipLED Package – Height – 0.55mm – Length – 2.60mm – Width – 2.20mm
• 50/60-Hz Lighting Ripple Rejection
• Low Active Power (0.6 mW Typical) with Power Down Mode
• RoHS Compliant

Applications

• Detection of ambient light to control display backlighting – Mobile devices – Cell phones, PDAs, PMP – Computing devices – Notebooks, Tablet PC, Key board – Consumer devices – LCD Monitor, Flat-panel TVs, Video Cameras, Digital Still Camera
• Automatic Residential and Commercial Lighting Management
• Automotive instrumentation clusters.
• Electronic Signs and Signals

Ordering Information

Part Number Packaging Type Package Quantity APDS-9303-020 Tape and Reel 6-pins Chipled package 2500

Ch0 (Visible + IR) Ch1 (IR)VDD ADC ADC GND SCL INT SDA ADDR SEL Command Register Address Select I/O Pins Configuration Table Pin Symbol Type Description

1 VDD Supply Supply voltage

2 GND Ground Power supply ground. All voltages are referenced to GND

3 ADDR SEL I SMBUS device select – three-state

4 SCL I SMBUS serial clock input terminal

5 SDA I/O SMBUS serial data I/O terminal

6 INT O Level interrupt – open drain

Parameter Symbol Min Max Unit Supply voltage VDD – 3.8 V Digital output voltage range VO -0.5 3.8 V Digital output current IO -1 20 mA Storage temperature range Tstg -40 85 ºC ESD tolerance human body model – 2000 V Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Condition Supply Voltage VDD 2.7 3.3 3.6 V Operating Temperature Ta -30 – 85 ºC SCL, SDA input low voltage VIL -0.5 – 0.8 V SCL, SDA input high voltage VIH 2.1 – 3.6 V

Electrical Characteristics

Parameter Symbol Min Typ Max Unit Conditions Supply current IDD – 0.24 0.6 mA Active – 3.2 15 μA Power down INT, SDA output low voltage VOL 0 – 0.4 V 3 mA sink current 0 – 0.6 V 6 mA sink current Leakage current ILEAK -5 – 5 μA

Operating Characteristics, High Gain (16x), Ta = 25°C, (unless otherwise noted) (see Notes 2, 3, 4, 5) Parameter Symbol Channel Min Typ Max Unit Conditions Oscillator frequency fosc 690 735 780 kHz Dark ADC count value Ch0 0 4 counts Ee = 0, Tint = 402 ms Ch1 0 4 Full scale ADC count value (Note 6) Ch0 65535 counts Tint > 178 ms Ch1 65535 Ch0 37177 Tint = 101 ms Ch1 37177 Ch0 5047 Tint = 13.7 ms Ch1 5047 ADC count value Ch0 750 1000 1250 counts λp = 640 nm, Tint = 101 ms Ch1 200 Ee = 36.3 μW/cm2 Ch0 700 1000 1300 λp = 940 nm, Tint = 101 ms Ch1 820 Ee = 119 μW/cm2 ADC count value ratio: Ch1/Ch0 0.15 0.2 0.25 λp = 640 nm, Tint = 101 ms 0.69 0.82 0.95 λp = 940 nm, Tint = 101 ms Irradiance responsivity Re Ch0 27.5 counts/ (μW/cm2) λp = 640 nm, Tint = 101 msCh1 5.5 Ch0 8.4 λp = 940 nm, Tint = 101 msCh1 6.9 Illuminance responsivity Rv Ch0 36 counts/ lux Fluorescent light source: Tint = 402 msCh1 4 Ch0 144 Incandescent light source: Tint = 402 msCh1 72 ADC count value ratio: Ch1/Ch0

0.11 Fluorescent light source:

Tint = 402 ms

0.5 Incandescent light source:

Tint = 402 ms Illuminance responsivity, low gain mode (Note 7) Rv Ch0 2.3 counts/ lux Fluorescent light source: Tint = 402 msCh1 0.25 Ch0 9 Incandescent light source: Tint = 402 msCh1 4.5 (Sensor Lux) /(actual Lux), high gain mode (Note 8) 0.65 1 1.35 Fluorescent light source: Tint = 402 ms 0.60 1 1.40 Incandescent light source: Tint = 402 ms

NOTES: 2. Optical measurements are made using small–angle incident radiation from light–emitting diode optical sources. Visible 640 nm LEDs and infrared 940 nm LEDs are used for final product testing for compatibility with high–volume production. 3. The 640 nm irradiance E e is supplied by an AlInGaP light–emitting diode with the following characteristics: peak wavelength λp = 640 nm and spectral halfwidth Δλ½ = 17 nm. 4. The 940 nm irradiance Ee is supplied by a GaAs light–emitting diode with the following characteristics: peak wavelength λp = 940 nm and spectral halfwidth Δλ½ = 40 nm. 5. Integration time Tint, is dependent on internal oscillator frequency (f osc) and on the integration field value in the timing register as described in the Register Set section. For nominal fosc = 735 kHz, nominal Tint = (number of clock cycles)/f osc Field value 00: T int = (11 x 918)/f osc = 13.7 ms Field value 01: Tint = (81 x 918)/fosc = 101 ms Field value 10: Tint = (322 x 918)/fosc = 402 ms Scaling between integration times vary proportionally as follows: 11/322 = 0.034 (field value 00), 81/322 = 0.252 (field value 01), and 322/322 = 1 (field value 10). 6. Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods and also by a 2–count offset. Full scale ADC count value = ((number of clock cycles)/2 - 2) Field value 00: Full scale ADC count value = ((11 x 918)/2 - 2) = 5047 Field value 01: Full scale ADC count value = ((81 x 918)/2 - 2) = 37177 Field value 10: Full scale ADC count value = 65535, which is limited by 16 bit register. This full scale ADC count value is reached for 131074 clock cycles, which occurs for Tint = 178 ms for nominal fosc = 735 kHz. 7. Low gain mode has 16x lower gain than high gain mode: (1/16 = 0.0625). 8. For sensor Lux calculation, please refer to the empirical formula below. It is based on measured Ch0 and Ch1 ADC count values for the light source specified. Actual Lux is obtained with a commercial luxmeter. The range of the (sensor Lux) / (actual Lux) ratio is estimated based on the variation of the 640 nm and 940 nm optical parameters. Devices are not 100% tested with fluorescent or incandescent light sources. CH1/CH0 Sensor Lux Formula 0 ≤ CH1/CH0 ≤ 0.52 Sensor Lux = (0.0315 x CH0) – (0.0593 x CH0 x ((CH1/CH0)1.4)) 0.52 ≤ CH1/CH0 ≤ 0.65 Sensor Lux = (0.0229 x CH0) – (0.0291 x CH1) 0.65 ≤ CH1/CH0 ≤ 0.80 Sensor Lux = (0.0157 x CH0) – (0.0180 x CH1) 0.80 ≤ CH1/CH0 ≤ 1.30 Sensor Lux = (0.00338 x CH0) – (0.00260 x CH1) CH1/CH0 ≥ 1.30 Sensor Lux = 0 PARAMETER† MIN TYP MAX UNIT t(CONV) Conversion time 12 100 400 ms f(SCL) Clock frequency – – 400 kHz t(BUF) Bus free time between start and stop condition 1.3 – – μs t(HDSTA) Hold time after (repeated) start condition. After this period, the first clock is generated. 0.6 – – μs t(SUSTA) Repeated start condition setup time 0.6 – – μs t(SUSTO) Stop condition setup time 0.6 – – μs t(HDDAT) Data hold time 0 – 0.9 μs t(SUDAT) Data setup time 100 – – ns t(LOW) SCL clock low period 1.3 – – μs t(HIGH) SCL clock high period 0.6 – – μs tF Clock/data fall time – – 300 ns tR Clock/data rise time – – 300 ns Cj Input pin capacitance – – 10 pF † Specified by design and characterization; not production tested.

the channel 0 and channel 1 data registers, respectively. device automatically begins the next integration cycle. SEL). The slave address options are shown in Table 1. Table 1. Slave Address Selection communicate with the APDS-9303 device. stored register select address.

• Send Byte protocol
• Receive Byte protocol
• Write Byte protocol
• Write Word protocol
• Read Word protocol
• Block Write protocol
• Block Read protocol When an SMBus Block Write or Block Read is initiated (see description of COMMAND Register), the byte following the COMMAND byte is ignored but is a requirement of the SMBus specification. This field contains the byte count (i.e. the number of bytes to be transferred). The APDS-9303 device ignores this field and extracts this information by counting the actual number of bytes transferred before the Stop condition is detected.

Table 3. The command register defaults to 00h at power on. Table 3. Command Register CMD 7 Select command register. Must write as 1. CLEAR 6 Interrupt clear. Clears any pending interrupt. This bit is a write–one–to–clear bit. It is self clearing. Write Word or Read Word protocol. Resv 4 Reserved. Write as 0. commands according to Table 2. Table 4. Control Register Resv 7:2 Reserved. Write as 0. this register, the device is powered down. verify that the device is communicating properly.

is provided that controls both ADC channels. The TIMING register defaults to 02h at power on. Table 5. Timing Register Resv 7-5 Reserved. Write as 0. MANUAL 3 Manual timing control. Writing a 1 begins an integration cycle. Writing a 0 stops an integration cycle. NOTE: This field only has meaning when INTEG = 11. It is ignored at all other times. Resv 2 Reserved. Write as 0. INTEG 1:0 Integrate time. This field selects the integration time for each conversion. page 5 for detailed information regarding how the scale values were obtained. Table 6. Integration Time simply writing a 0 to the same bit field.

combined to form a 16–bit threshold value. The interrupt threshold registers default to 00h on power up. Table 7. Interrupt Threshold Register THRESHHIGHHIGH registers) can be written together to set the 16–bit ADC value in a single transaction.

total time is approximately 4 seconds. COMMAND register with the CLEAR bit set. cleared. The Alert Response Address is 0Ch. in an SMBAlert mode, and the software set interrupt may be cleared by an SMBAlert cycle. NOTE: Interrupts are based on the value of Channel 0 only. Table 8. Interrupt Control Register Resv 7:6 Reserved. Write as 0. INTR 5:4 INTR Control Select. This field determines mode of interrupt logic according to Table 9, below. PERSIST 3:0 Interrupt persistence. Controls rate of interrupts to the host processor as shown in Table 10, below.

Table 9. Interrupt Control Select

00 Level Interrupt output disabled

01 Level Interrupt output enabled

Table 10. Interrupt Persistence Select

0000 Every ADC cycle generates interrupt

0001 Any value outside of threshold range

read–only register, whose value never changes. Table 11. ID Register

data registers are read–only and default to 00h on power up. Table 12. ADC Channel Data Registers the reading of the lower and upper registers.

Notes: All dimensions are in millimeters. Dimension tolerance is ±0.2 mm unless otherwise stated PCB pad layout The suggested PCB layout is given below: Notes: All linear dimensions are in millimeters. Pin 1 Marker Pin 1 : Vdd Pin 2 : GND Pin 3 : ADR SEL Pin 4 : SCL Pin 5 : SDA Pin 6 : INT Coplanarity±0.1 0.55±0.1 2x0.6±0.05 4x0.35±0.15 0.25±0.15 0.35±0.15\` 0.70 1.05 6X0.65±0.15 0.18 2.60±0.1 0.1 0.35±0.15 0.25±0.15 6 X R0.18 3.00° 2.20±0.1

APDS-9303 Tape and Reel Dimensions

Moisture Proof Packaging Chart All APDS-9303 options are shipped in moisture proof package. Once opened, moisture absorption begins. This part is compliant to JEDEC Level 3. Recommended Storage Conditions Storage Temperature 10°C to 30°C Relative Humidity Below 60% RH Time from Unsealing to Soldering After removal from the bag, the parts should be soldered within seven days if stored at the recommended storage conditions. When MBB (Moisture Barrier Bag) is opened and the parts are exposed to the recommended storage conditions more than seven days the parts must be baked before reflow to prevent damage to the parts. Baking Conditions If the parts are not stored per the recommended storage conditions they must be baked before reflow to prevent damage to the parts. Package Temp. Time In Reels 60°C 48 hours In Bulk 100°C 4 hours Note: Baking should only be done once. UNITS IN A SEALED MOISTURE-PROOF PACKAGE ENVIRONMENT LESS THAN 30°C AND LESS THAN 60% RH PACKAGE IS OPENED (UNSEALED) PACKAGE IS OPENED LESS THAN 168 HOURS NO BAKING IS NECESSARY PERFORM RECOMMENDED BAKING CONDITIONS YES YES NO NO BAKING CONDITIONS CHART

Recommended Reflow Profile 50 100 300150 200 250 t-TIME (SECONDS) 120 150 180 200 230 255 T - TEMPERATURE (°C) R3 R4 217 MAX 260C 60 sec to 90 sec Above 217 C HEAT UP SOLDER PASTE DRY SOLDER REFLOW COOL DOWN The reflow profile is a straight-line representation of a nominal temperature profile for a convective reflow solder process. The temperature profile is divided into four process zones, each with different ΔT/Δtime tem - perature change rates or duration. The ΔT/Δtime rates or duration are detailed in the above table. The temperatures are measured at the component to printed circuit board connections. In process zone P1 , the PC board and component pins are heated to a temperature of 150°C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 3°C per second to allow for even heating of both the PC board and component pins. Process zone P2 should be of sufficient time duration (100 to 180 seconds) to dry the solder paste. The temperature is raised to a level just below the liquidus point of the solder. Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 260°C (500°F) for optimum results. The dwell time above the liquidus point of solder should be between 60 and 90 seconds. This is to assure proper coalescing of the solder paste into liquid solder and the formation of good solder connections. Beyond the recommended dwell time the intermetallic growth within the solder con- nections becomes excessive, resulting in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25°C (77°F) should not exceed 6°C per second maximum. This limitation is necessary to allow the PC board and component pins to change dimensions evenly, putting minimal stresses on the component. It is recommended to perform reflow soldering no more than twice. Process Zone Symbol ∆T Maximum ∆T/∆time or Duration Heat Up P1, R1 25°C to 150°C 3°C/s Solder Paste Dry P2, R2 150°C to 200°C 100s to 180s Solder Reflow P3, R3 P3, R4 200°C to 260°C 260°C to 200°C 3°C/s -6°C/s Cool Down P4, R5 200°C to 25°C -6°C/s Time maintained above liquidus point, 217°C > 217°C 60s to 120s Peak Temperature 260°C – Time within 5°C of actual Peak Temperature – 20s to 40s Time 25°C to Peak Temperature 25°C to 260°C 8mins

Appendix A: Window Design Guide A1: Optical Window Dimensions To ensure that the performance of the APDS-9303 will not be affected by improper window design, there are some criteria requested on the dimensions and design of the window. There is a constraint on the minimum size of the window, which is placed in front of the photo light sensor, so that it will not affect the angular response of the APDS- 9303. This minimum dimension that is recommended will ensure at least a ±35° light reception cone. If a smaller window is required, a light pipe or light guide can be used. A light pipe or light guide is a cylindrical piece of transparent plastic, which makes use of total internal reflection to focus the light. The thickness of the window should be kept as minimum as possible because there is a loss of power in every optical window of about 8% due to reflection (4% on each side) and an additional loss of energy in the plastic material. Figure A1 illustrates the two types of window that we have recommended which could either be a flat window or a flat window with light pipe. Figure A1. Recommended Window Design Table A1 and Figure A2 show the recommended dimen - sions of the window. These dimension values are based on a window thickness of 1.0mm with a refractive index 1.585. The window should be placed directly on top of the light sensitive area of APDS-9303 (see Figure A3) to achieve better performance. If a flat window with a light pipe is used, dimension D2 should be 1.55mm to optimize the performance of APDS-9303. Figure A2. Recommended Window Dimensions WD: Working Distance between window front panel & APDS-9303 D1: Window Diameter T: Thickness L: Length of Light Pipe D2: Light Pipe Diameter Z: Distance between window rear panel and APDS-9303 Z L T Top View APDS-9303 Ambient Light Sensor WD D2 D1

Figure A3. APDS-9303 Light Sensitive Area Notes: 1. All dimensions are in millimeters 2. All package dimension tolerance in ± 0.2mm unless otherwise specified A2: Optical Window Material The material of the window is recommended to be poly - carbonate. The surface finish of the plastic should be smooth, without any texture. The recommended plastic material for use as a window is available from Bayer AG and Bayer Antwerp N. V. (Europe), Bayer Corp.(USA) and Bayer Polymers Co., Ltd. (Thailand), as shown in Table A2. Table A2. Recommended Plastic Materials Material number Visible light transmission Refractive index Makrolon LQ2647 87% 1.587 Makrolon LQ3147 87% 1.587 Makrolon LQ3187 85% 1.587 Table A1. Recommended dimension for optical window WD (T+L+Z) Flat Window (L = 0.0 mm, T = 1.0 mm) Flat window with Light Pipe (D2 = 1.55mm, Z = 0.5mm, T = 1.0mm) Z D1 D1 L 1.5 0.5 2.25 – – 2.0 1.0 3.25 – – 2.5 1.5 4.25 – – Pin 1 Marker 1.05±0.15 1.30±0.15 2.60 1.50 2.20 Active area

For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. AV02-2299EN - December 29, 2009 Appendix B: Application circuit APDS-9303 Pin 1: VDD Pin 5 Pin 4 VIO Pin 6 Pin 2: GND 0.1uF Pin 3 ADDR_SEL INT SDA SCLPin 1 Pin 2 MCU Note: ADDR_SEL Float : Slave address is 0111001 R1 R2 R3 Figure B1. Application circuit for APDS-9303 The power supply lines must be decoupled with a 0.1 uF capacitor placed as close to the device package as possible, as shown in Figure B1. The bypass capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents caused by internal logic switching. Pull-up resistors, R1 and R2, maintain the SDA and SCL lines at a high level when the bus is free and ensure the signals are pulled up from a low to a high level within the required rise time. For a complete description of the SMBus maximum and minimum Rp values, please review the SMBus Specification at http://www.smbus.org/specs A pull-up resistor, R3, is also required for the interrupt (INT), which functions as a wired-AND signal in a similar fashion to the SCL and SDA lines. A typical impedance value between 10 kΩ and 100 kΩ can be used.