APA6003 ANPEC | Alldatasheet

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Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw1 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. 15W Stereo Class D Audio Power Amplifier APA6003 The APA6003 is a stereo, high efficiency, Class-D audio amplifier available in TSSOP-28P and QFN4x4-28 pins packages. The Class-D power amplifier has higher efficiency com- paring to the tradition Class-AB power amplifier. The fil- ter free Class-D architecture eliminates the external low pass filters. The internal gain setting can minimum the external component counts, and for the flexible applica- tion the gain can be set to 4-step 20, 26, 32, 36dB by gain control pins (GAIN0 and GAIN1). The AGC function pro- tects speaker from being out of its power rating but keeps acceptable performance. The integration of Class-D power amplifier is a best so- lution for power efficiency and lower the total BOM costs. The operating voltage is from 4.5V to 24V. The APA6003 power amplifiers are capable of driving 15 W at VDD=16V into 8Ω speaker, and provides thermal and over-current protections also can detection the DC that prevent to de- stroy the speaker voice coil. Features General Description

Applications

  • LCD Monitor
  • Consumer Audio Equipment
  • Supply Voltage is 4.5V ~ 24V
  • Class D operation eliminates heat sink & reduce power supply requirement
  • 20,26, 32, 36, 4 steps gain setting
  • 15W/ch into an 8 W Loads at 10% THD+N from a 16-V supply
  • 10W/ch into 8W Loads at 10% THD+N from a 12-V supply
  • 30W into a 4W Mono Load at 10% THD+N from a 16-V Supply
  • 90% Efficient Class-D Operation Eliminates Need for Heat Sinks
  • External AGC function
  • Adjustable switch frequency
  • Flow Through Pin Out Facilitates Easy Board Lay- out
  • Robust Pin-to-Pin Short Circuit Protection and Ther- mal Protection with Auto Recovery Option
  • Excellent THD+N / Pop-Free Performance
  • Thermal and Over-Current Protections with Auto- Recovery option
  • Dual Differential Inputs with MUX
  • TSSOP-28P with thermal pad packages
  • QFN4x4-28B with thermal pad packages Simplified Application Circuit APA6003 Left Channel Input Right Channel Input Left Channel Speaker Right Channel Speaker LOUTP RINN ROUTN RINP LOUTN ROUTP FERRITE BEAD FILTER FERRITE BEAD FILTER RINNA RINPA LINN LINP LINNA LINPA

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw2 APA6003 Ordering and Marking Information Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration R: TSSOP-28P Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material Assembly Material Handling Code Temperature Range Package Code APA6003 R: XXXXX - Date Code G : Halogen and Lead Free Device APA6003 XXXXX QA: QFN4x4-28B APA6003 QA: XXXXX - Date CodeAPA6003 XXXXX LINP 3 LINN 4 VCLAMP 9 AGND 8 GAIN0 5 AGC 10 RINN 11 RINNA 13 APA6003 TSSOP-28P

15 SEL

16 MONO

17 RPVDD

18 RBSP

21 RBSN

19 ROUTP

20 ROUTN

22 LBSN

23 LOUTN

24 LOUTP

25 LBSP

26 LPVDD

28 FLAG

19 MONO

15 RINP

16 RINNA

17 RINPA

18 SEL

20 RPVDD

21 RBSP

22 ROUTP

28 LOUTP

23 ROUTN

24 RBSN

25 PGND

26 LBSN

27 LOUTN

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw3 APA6003 Recommended Operating Conditions Symbol Parameter Min. Max. Unit VDD Supply Voltage 4.5 24 SD 2.2 - VIH High Level Threshold Voltage GAIN0, GAIN1, MONO 2.0 - SD - 0.8 VIL Low Level Threshold Voltage GAIN0, GAIN1, MONO - 0.8 V TA Ambient Temperature Range -40 85 oC TJ Junction Temperature Range -40 125 oC RL Speaker Resistance 3.5 - Ω Thermal Characteristics Symbol Parameter Typical Value Unit θJA Thermal Resistance -Junction to Ambient (Note 2) TSSOP-28P QFN4x4-28B θJC Thermal Resistance -Junction to Case (Note 3) TSSOP-28P QFN4x4-28B οC /W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of TSSOP-28P is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TSSOP-28P package. Absolute Maximum Ratings (Note 1) Symbol Parameter Rating Unit VDD Supply Voltage -0.3 to 30 Input Voltage (/SD, GAIN0 and GAIN1, MONO and /FLAG) -0.3 to VDD+0.3 AGC -0.3 to 6.3 VI LINP, LINN, RINP, RINN -0.3 to 6.3 V TJ Maximum Junction Temperature 150 TSTG Storage Temperature Range -65 to +150 TSDR Maximum Soldering Temperature Range, 10 seconds 260 οC PVDD > 15V 4.8 PVDD ? 15V 3.2 RL MONO mode 3.2 Ω PD Power Dissipation Internally Limited W Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom- mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (Over operating free-air temperature range unless otherwise noted.)

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw4 APA6003

Electrical Characteristics

Symbol Parameter Test Condition Min. Typ. Max. VCLAMP Regulated voltage IO=2mA,VDD=6~22V,TJ=-40οC ~125οC 4.5 5 5.5 V VO Maximum Output Voltage Under AGC Control VAGC=1V, AV=20dB - 5.5 - Vp tDCDET DCP detect time VRINP=5V,VRINN=0V - 500 - ms TSD(ON) Shutdown Turn-On Time /SD=2.2V - 20 - ms TSD(OFF) Shutdown Turn-Off Time /SD=0.8V - 2 - μs IDD Quiescent Supply Current No Load - 17 35 mA ISD Quiescent Supply Current in shutdown mode /SD = 0V - 180 250 μA II Input Current /SD, GAIN0, GAIN1, MONO=12V - 23 50 μA FOSC Internal Oscillator Frequency - 300 - kHz RDSON Static Drain-Source On-State Resistance IL=0.5A - 200 - mΩ Gain0=0, Gain1=0 - 20 - Gain0=1, Gain1=0 - 26 - Gain0=0, Gain1=1 - 32 - AV Gain Gain0=1, Gain1=1 - 36 - dB VDD=12V, GND=0V, AV=20dB, TA= 25οC (unless otherwise noted). APA6003 Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD=19V, TA=25°C, AV=20dB VDD=16V THD+N = 1%, FIN = 1KHz, RL = 8Ω - 14 - Po Output Power VDD=16V THD+N = 10%, FIN = 1kHz RL = 8Ω - 17 - W THD+N Total Harmonic Distortion Pulse Noise VDD=16V FIN = 1kHz, PO= 7.5W , RL = 8Ω - 0.05 - % Crosstalk Channel separation VO=1Vrms, FIN = 1kHz, AV=20dB - -90 - PSRR Power Supply Rejection Ratio RL=4Ω ,input AC-Ground, FIN=1kHz - -70 - SNR Signal-to-noise ratio Maximum output at THD+N<1%, FIN=1kHz, AV=20dB, A-weighted - 90 - Attshutdown Shutdown Attenuation FIN = 1kHz, RL = 8Ω, Vin= 1VPP - -100 - dB |VOS| Offset Voltage AV=20dB - 10 - mV Vn Noise Output Voltage With A-weighted Filter (A V=20dB) - 170 - µV (rms) VDD=12V, GND=0V, AV=20dB, TA= 25οC (unless otherwise noted). Stereo Mode

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw5 APA6003 VDD=12V,TA=25°C APA6003 Symbol Parameter Test Condition Min. Typ. Max. Unit VDD=16V THD+N = 1%, FIN = 1KHz RL = 8 - 8 - Po Output Power VDD=16V THD+N = 10%, FIN = 1KHz RL = 8 - 9.5 - W THD+N Total Harmonic Distortion Pulse Noise VDD=16V FIN = 1kHz, PO= 6W, RL = 4Ω - 0.05 - % Crosstalk Channel separation VO=1Vrms, FIN = 1kHz, AV=20dB - -90 - PSRR Power Supply Rejection Ratio RL=4Ω ,input AC-Ground,FIN=1kHz - -70 - SNR Signal-to-noise ratio Maximum output at THD+N<1%, FIN=1kHz, AV=20dB, A-weighted - 90 - Attshutdown Shutdown Attenuation FIN = 1kHz, RL = 8Ω, Vin= 1Vrms - -100 - dB |VOS| Offset Voltage Vin = 0V, AV=20dB - 10 - mV Vn Noise Output Voltage Input AC ground, With A-weighted Filter (AV=20dB) - 170 - µV (rms) Mono Mode VDD=12V, GND=0V, AV=20dB, TA= 25οC (unless otherwise noted). APA6003 Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD=12V, TA=25°C VDD=16 THD+N = 1%, FIN = 1KHz RL = 4 - 28 - Po Output Power VDD=16 THD+N = 10%, FIN = 1kHz, RL = 4 - 35 - W THD+N Total Harmonic Distortion Pulse Noise VDD=16 FIN = 1kHz, PO= 6, RL = 4Ω - 0.05 - % PSRR Power Supply Rejection Ratio RL=4Ω ,input AC-Ground,FIN=1kHz - -50 - SNR Signal-to-noise ratio Maximum output at THD+N<1%, FIN=1kHz, AV=20dB, A-weighted - 90 - Attshutdown Shutdown Attenuation FIN = 1kHz, RL = 8Ω, Vin= 1Vrms - -100 - dB |VOS| Offset Voltage AV=20dB - 15 - mV Vn Noise Output Voltage Input AC ground, With A-weighted Filter (AV=20dB) - 150 - µV (rms) VDD=12V, GND=0V, AV=20dB, TA= 25οC (unless otherwise noted). Stereo Mode

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw6 APA6003 Pin NO. TSSOP-28P QFN4x4-28 B Name I/O/P FUNCTION 1 5 LINPA I Positive audio input for left channel. 2 6 LINNA I Negative audio input for left channel. 3 7 LINP I Positive audio input for left channel. 4 8 LINN I Negative audio input for left channel. 5 9 GAIN0 I Gain select least significant bit. TTL logic levels with compliance to AVDD. 6 10 GAIN1 I Gain select least significant bit. TTL logic levels with compliance to AVDD. 7 11 AVDD P Analog supply. 8 - AGND P Analog signal ground. Connect to the thermal pad. 9 12 VCLAMP I Regulated voltage, Nominal voltage is 5V. 10 13 AGC I AGC level adjust. Connect a resistor divider from VCLAMP to GND to set AGC. Connect directly to VCLAMP for no AGC. 11 14 RINN I Negative audio input for right channel. 12 15 RINP I Positive audio input for right channel. 13 16 RINNA I Negative audio input for right channel. 14 17 RINPA I Positive audio input for right channel. 15 18 SEL I Dual Differential Inputs control, SEL to low: INN / INP input, SEL to high : INNA / INNP input 16 19 MONO I Parallel BTL mode switch 17 20 RPVDD P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connect internally. 18 21 RBSP I Bootstrap I/O for right channel, positive high-side FET. 19 22 ROUTP O Class-D H-bridge positive output for right channel. 20 23 ROUTN O Class-D H-bridge negative output for right channel. 21 24 RBSN I Bootstrap I/O for right channel, negative high-side FET. 22 26 LBSN I Bootstrap I/O for left channel, negative high-side FET. 23 27 LOUTN O Class-D H-bridge negative output for left channel. 24 28 LOUTP O Class-D H-bridge positive output for left channel. 25 1 LBSP I Bootstrap I/O for left channel, positive high-side FET. 26 2 LPVDD P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect internally. 27 3 /SD I Shutdown logic input for audio amp (Low=outputs disabled, High=output enabled). . TTL logic levels with compliance to AVDD. 28 4 /FLAG O Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVDD. Short circuit faults can be set to auto-recovery by connecting /FLAG pin to /SD pin. - 25 PGND P Power ground for the H-bridges. 29(Thermal Pad) 29(Thermal Pad) GND P Power ground for the H-bridges. Pin Description

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw7 APA6003 Block Diagram AGC Reference Startup Protection AVDD RAMP GEN. SD GAIN1 GAIN0 PGND GAIN Control AGC FLAG VCLAMP LINP LINN PWM Logic MONO Select LOUTP LBSP LOUTP FB LBSN PGND LOUTN LOUTN FB PGND RINN RINP PWM Logic MONO Select ROUTN RBSP ROUTN FB RBSN PGND ROUTP ROUTP FB LDO Regulator TTL Buffer DC Detect UVLO/OCL O Thermal Detect SD Detect Logic Biases and References VCLAMP TTL BufferMONO MONO Select AGND Gate Drive Gate Drive Gate Drive Gate Drive VCLAMP VCLAMP VCLAMP VCLAMP LPVDD LPVDD RPVDD RPVDD LPVDD LPVDD RPVDD RPVDD LPVDD RPVDD Gain Control LOUTP FB LOUTN FB Gain Control ROUTP FB ROUTN FB AGC Control AGC Control AGC Control AGC Control LINPA LINNA RINNA RINPA SEL ControlSEL SEL Control SEL Control

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw8 APA6003 Typical Application Circuit Stereo LINP 3 AGND 8 VCLAMP9 RINNA 13 V DD GND LINPA 1 LINNA 2 1µFLeft Channel Input Signal 1µF Gain Setting 1µF 1µF Left Channel Input Signal 1µFRight Channel Input Signal 1µF 1µF 1µF Right Channel Input Signal 1µF 1µF 1µF 10kΩ 10kΩ  100kΩ (Recommmanded) V DD 100µF 0.1µF 1nF 0.22µF 0.22µF 1000pF 1000pF BEAD BEAD 0.22µF 0.22µF 1000pF 1000pF BEAD BEAD Dual Differential Inputs Control 100µF 0.1µF 1nF MONO LINP 3 AGND 8 VCLAMP9 RINNA 13 V DD GND LINPA 1 LINNA 2 Gain Setting 1µFRight Channel Input Signal 1µF 1µF 1µF Right Channel Input Signal 1µF 1µF  100kΩ (Recommmanded) V DD 100µF 0.1µF 1nF 0.47µF 0.47µF 1000pF 1000pF BEAD BEAD Dual Differential Inputs Control 100µF 0.1µF 1nF

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw9 APA6003 AGC Gain Table VDD=12V, VGND=0V, TA=25OC, No Load Gain=20dB Gain=26dB Gain=32dB Gain=36dB Step dB dB dB dB 1 20.15 26.15 32.15 36.15 2 19.65 25.65 31.65 35.65 3 19.15 25.15 31.15 35.15 4 18.65 24.65 30.65 34.65 5 18.15 24.15 30.15 34.15 6 17.65 23.65 29.65 33.65 7 17.15 23.15 29.15 33.15 8 16.65 22.65 28.65 32.65 9 16.15 22.15 28.15 32.15 10 15.65 21.65 27.65 31.65 11 15.15 21.15 27.15 31.15 12 14.65 20.65 26.65 30.65 13 14.15 20.15 26.15 30.15 14 13.65 19.65 25.65 29.65 15 13.15 19.15 25.15 29.15 16 12.65 18.65 24.65 28.65 17 12.15 18.15 24.15 28.15 18 11.65 17.65 23.65 27.65 19 11.15 17.15 23.15 27.15 20 10.65 16.65 22.65 26.65 21 10.15 16.15 22.15 26.15 22 9.65 15.65 21.65 25.65 23 9.15 15.15 21.15 25.15 24 8.65 14.65 20.65 24.65

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw10 APA6003 AGC Gain Table VDD=12V, VGND=0V, TA=25OC, No Load Gain=20dB Gain=26dB Gain=32dB Gain=36dB Step dB dB dB dB 25 8.15 14.15 20.15 24.15 26 7.15 13.15 19.15 23.15 27 6.15 12.15 18.15 22.15 28 5.15 11.15 17.15 21.15 29 4.15 10.15 16.15 20.15 30 3.15 9.15 15.15 19.15 31 2.15 8.15 14.15 18.15 32 0.15 6.15 12.15 16.15

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw11 APA6003 Function Description Class-D Operation Figure1. The APA6003 Output Waveform The APA6003 uses a modulation scheme that allows op- eration without the classic LC reconstruction filter when the amp is driving an inductive load. Each output is switch- ing from 0 volts to the supply voltage. The VOUTP and VOUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of VOUTP is greater than 50% and VOUTN is less than 50% for positive output voltages. The duty cycle of VOUTP is less than 50% and VOUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0V throughout most of the switching period, Gain Setting Operation The APA6003’s gain can be set by GAIN0, GAIN1. The detail gain setting value is list at table 1. Shutdown Operation In order to reduce power consumption while not in use, the APA6003 contains a shutdown function to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when logic low is placed on the SD pin for APA6003. The trigger point between a logic high and logic low level is typically 2.2V. It is best to switch between ground and the supply voltage VDD to provide maximum device performance. By switching the SD pin to low level, the amplifier enters a low-consumption- cur- rent state, IDD for APA6003 is in shutdown mode. On normal operating, APA6003 ’s SD pin should pull to high level to keeping the IC out of the shutdown mode. The SD pin should be tied to a definite voltage to avoid unwanted state changes. Gain1 Gain0 Gain Input Impedance 0 0 20 60kΩ 0 1 26 30kΩ 1 0 32 15kΩ 1 1 36 9kΩ Table 1 : The Gain Setting reducing the switching current, which reduces any I 2R losses in the load. AGC Function Operation The APA6003 provides the non-clipping Control, When the output reaches the maximum power setting value, the internal Programmable Gain Amplifier (PGA) will de- crease the gain for prevent the output waveform clipping. Using the AGC pin to set the non-clipping function and limit the output power. VP=5.6 x AGC voltage if AGC<2.5V VOUTP VOUTN VOUT (VOUTP-VOUTN) IOUT Output = 0 Output > 0 Output < 0 VOUTP VOUTN VOUT (VOUTP-VOUTN) IOUT VOUTP VOUTN VOUT (VOUTP-VOUTN) IOUT VCLAMP Supply The VCLAMP is used to power the gates of the output full bridge transistors. It can also be used to supply the AGC voltage divider circuit. Add a 1 µF capacitor to ground at this pin.

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw12 APA6003 Function Description (Cont.) Stereo/mono switching Operation APA6003 offers the feature of Stereo operation with two outputs of each channel connected directly. If the MONO pin (pin 14) is tied high, the positive and negative outputs of each channel (left and right) are synchronized and in phase. To operate in this mono mode, apply the input signal to the RIGHT input and place the speaker between the LEFT and RIGHT outputs. Connect the positive and negative output together for best efficiency. Mono mode can increase more output power compare to the stereo mode single channel ’s output power. DC Detect When a DC signal applies to the input of APA6003 and the time excesses 500ms, the APA2621’s DC detect fault will be reported on the FLAG pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the state of the outputs to Hi-Z. To clear the DC Detect it is necessary to cycle the PVDD supply. Cycling SD will NOT clear a DC detect fault. Thermal Protection Thermal protection on the APA6003 prevents damage to the device when the internal die temperature exceeds 150oC. There is a +15oC tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15 oC. The device begins normal operation at this point with no external system interaction. Thermal protection faults are NOT reported on the FLAG terminal. Over-Circuit Protection APA6003 has protection from over-current conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the FLAG pin as a low state. The amplifier outputs are switched to a Hi-Z state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through the low state. Connect FLAG to SD pin, the over current protection will be auto recovery. A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 12% for more than 500 msec at the same polarity. This feature protects the speaker from large DC currents or AC currents less than 2Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-up until the signals at the inputs are stable. Also, take care to match the imped- ance seen at the positive and negative inputs to avoid nuisance DC detect faults.

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw13 APA6003

Application Information

Input Resistance, Ri Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 kΩ ±20%, to the largest value, 60 kΩ ±20%. As a result, if a single capaci- tor is used in the input high-pass filter, the -3 dB or cutoff frequency may change when changing gain steps. Input Capacitor, Ci In the typical application, an input capacitor Ci is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, C i and the input impedance of the amplifier (R I) form a high-pass filter with the corner frequency determined in Equation 1. The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where RI is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 1 is reconfigured as Equation 2. ii )hipass(C CR2 1f π= (1) In this example, CI is 0.13 µF; so, one would likely choose a value of 0.15 µF as this value is commonly used. If the gain is known and is constant, use R I from Table 1 to calculate C I. A further consideration for this capacitor is the leakage path from the input source through the input network C I and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applica- tions as the dc level there is held at V CLAMP /2, which is likely higher than the source dc level. Note that it is impor- tant to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset volt- ages and it is important to ensure that boards are cleaned properly. ci i fR2 1C π= (2) Figure 3. Ferrite Bead Output Filter require output filter for FCC & CE standard. series-resistance (ESR) ceramic capacitor, typically 0. near the audio power amplifier is recommended.

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw15 APA6003 Application Information (Cont.) 5. Thermal Pad - The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and ther- mal land should be 6.46 mm by 2.35mm. Seven rows of solid vias (three vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the ther- mal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. Layout Recommendation (cont.) Via diameter = 0.3mm x 9 2.7mm 1.5mm 0.25mm 0.4mm QFN4x4-28B Land Pattern Recommendation 0.3mm 3.0mm 6mm Via diameter = 0.3mm x 8 6.4mm 2.0mm 0.3mm 0.65mm TSSOP-28P Land Pattern Recommendation

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw16 APA6003

Package Information

Note : 1. Followed from JEDEC MO-153 AET. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. S Y M B O L MIN. MAX. 1.20 0.05 0.09 0.20 9.60 9.80 0.15 A c D E e L MILLIMETERS b 0.19 0.30

0.65 BSC

0.45 0.75

0.026 BSC

MIN. MAX. INCHES 0.047 0.002 0.007 0.012 0.004 0.008 0.378 0.386 0.169 0.177 0.018 0.030 0.006 A2 0.80 1.05 4.30 4.50E1 0.031 0.041 4.50D1 0.177 E2 2.50 0.098 6.00 3.50 0.236 0.138 INCHES 8o 0o 8o0o VIEW A 0.25 SEATING PLANE GAUGE PLANE SEE VIEW A E b c A e L EXPOS ED PAD D 6.20 6.60 0.244 0.260

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw17 APA6003 QFN4x4-28B e D E Pin 1 b A aaa NX c SYMBOL MIN. MAX. 1.00 0.00 0.15 0.25 2.50 2.80 0.05 2.50 A b D E e L MILLIMETERS A3 0.20 REF QFN4x4-28B 0.30 0.50 2.80

0.008 REF

MIN. MAX. INCHES 0.039 0.000 0.006 0.010 0.098 0.110 0.098 0.012 0.020 0.80 0.110 0.031 0.002 0.4 BSC 0.016 BSC K 0.20 0.008 3.90 4.10 0.154 0.161 3.90 4.10 0.154 0.161 aaa 0.08 0.003

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw18 APA6003 Application A H T1 C d D W E1 F - 0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 TSSOP-28P Application A H T1 C d D W E1 F - 0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 QFN4x4-28B (mm) Carrier Tape & Reel Dimensions Devices Per Unit Package Type Unit Quantity TSSOP-28P Tape & Reel 2000 QFN4x4-28B Tape & Reel 3000 H A d A AB W F T P0OD0 B SECTION B-B SECTION A-A OD1

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw19 APA6003 Taping Direction Information TSSOP-28P USER DIRECTION OF FEED QFN4x4-28B USER DIRECTION OF FEED

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw20 APA6003 Classification Profile

Copyright  ANPEC Electronics Corp. (Tsmax to TP) 3 °C/second max. 3 °C/second max. Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. Time 25°C to peak temperature 6 minutes max. 8 minutes max.

  • Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.

** Tolerance for time at peak profile temperature (t p) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Table 2. Pb-free Process – Classification Temperatures (Tc)

Copyright  ANPEC Electronics Corp. Rev. P.1 - Sep., 2015 www.anpec.com.tw22 APA6003 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838