APA3002 ANPEC | Alldatasheet

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Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw1 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. 12W Stereo Class-D Audio Power Amplifier APA3002

  • Class-D Operation with High Efficiency.
  • 32-Step DC Volume Control With Hysteresis
  • 9W Per Channel Output Power into 8W Load at 12V, Class-D Output
  • 12W Per Channel Output into 6W Load at 12V, Class-D Output
  • 5V LDO Output for Powering APA4801 Head- phone Driver
  • Line Output for APA4801 Headphone Driver with DC Volume Control
  • Low Current Consumption in Shutdown Mode (10mA, Typical)
  • APA3002 will Auto-Recovery after Over-Current Protection
  • Thermal and Over-Current Protections
  • TQFN7x7-48 with Thermal Pad Package TQFP7x7-48P with Thermal Pad Package
  • Lead Free and Green Devices Available (RoHS Compliant) The APA3002 is a monolithic integrated circuit, which pro- vides precise DC volume control, and a stereo Class-D audio power amplifiers capable of producing 9W into 8 Ω (12V) with less than 10% THD+N. The attenuator range of the volume control in the APA3002 is from 36dB (VVOLUME=5V) to -40dB (VVOLUME=0V) with 32 steps. The ad- vantage of internal gain setting can be less components and PCB area. The circuitries of both thermal and the over-current protections are integrated in the APA3002. It protects the chip from being destroyed by over tempera- ture and over current failure. To simplify the audio system design, the APA3002 com- bines a line output for external headphone driver with volume control and a 5V regulator for external headphone drive, where the speaker output can be switched off by the headphone jack’s switch pin that connects to the APA3002’s mode pin as shown in the application circuit. Features General Description

Applications

  • LCD TV
  • Active Speaker Ordering and Marking Information Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). APA3002 Handling Code Temperature Range Package Code Package Code QB: TQFN7x7-48 QCA: TQFP7x7-48P Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR: Tape & Reel Assembly Material G : Halogen and Lead Free Device APA3002 QB: XXXXX - Date Code Assembly Material APA3002 XXXXX XXXXX - Date CodeAPA3002 QCA: APA3002 XXXXX

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw2 APA3002 Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol Parameter Rating Unit VDD Supply Voltage (AVDD to AGND, LPVDD to LPGND, and RPVDD to RPGND) -0.3 to 15 V VMODE, VVREF, VVOLUME, VVARDIFF, VVARMAX Input Voltage (MODE to AGND, VREF, VOLUME, VARDIFF, and VARMAX to REFGND) -0.3 to 5.5 VSD Input Voltage (SD to AGND) -0.3 to VDD+0.3 VRIN+, VRIN-,VLIN+,VLIN- Input Voltage (RIN+, RIN-, LIN+, and LIN- to AGND) -0.3 to 7 Input Voltage (RPGND and LPGND to AGND) -0.3 to +0.3 V I5VLDO Output Current (5VLDO) 120 ILDOREF Output Current (LDOREF) 20 mA TJ Maximum Junction Temperature 150 ο C TSTG Storage Temperature Range -65 to +150 ο C TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 ο C PD Power Dissipation Internally Limited W RL Class-D Power Amplifier Minimum Load Resistance 4 Ω Pin Configurations (APA3002D) TQFN7x7-48 (TOP VIEW) APA3002 2.5VREF 4 VARDIFF 9 VREF 8 VARMAX 10 VOLUME 11 LIN+ 5 LIN- 6 RIN- 2 RIN+ 3 LDOREF 7 REFGND 12 SD 1

33 AVDD

28 COSC

35 MODEOUT

32 RVAROUT

27 ROSC

34 MODE

36 RCLAMP

25 LCLAMP

31 LVAROUT

30 AGND

26 AGND

46 RPVDD

45 ROUT-

40 ROUT+

47 RPVDD

44 ROUT-

39 RPVDD

48 RBS-

37 RBS+

43 RPGND

42 RPGND

38 RPVDD

41 ROUT+

(TOP VIEW) APA3002 2.5VREF 4 VARDIFF 9 VREF 8 VARMAX 10 VOLUME 11 LIN+ 5 LIN- 6 RIN- 2 RIN+ 3 LDOREF 7 REFGND 12 SD 1 LOUT+ 21 LOUT- 16 LPVDD 23 LOUT+ 20 LPVDD 15 LPVDD 22 LBS+ 24 LBS- 13 LPGND 19 LPGND 18 LPVDD 14 LOUT- 17 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw3 APA3002 Symbol Parameter Typical Value Unit θ JA Thermal Resistance -Junction to Ambient (Note 2) TQFN7x7-48 TQFP7x7-48P ο C/W Recommended Operating Conditions Range Symbol Parameter Min. Max. Unit VDD Supply Voltage 8.5 14 V Volume Reference Voltage VREF 3.0 5.5 V Volume Control Pin, Input Voltage VOLUME, VARMAX, VARDIFF - 5.5 V SD 2 - V VIH High-level Input Voltage MODE 3.5 - V SD - 0.8 V VIL Low-level Input Voltage MODE - 2 V VOH High-level Output Voltage MODEOUT sources 1mA V5VLDO -100m - V VOL Low-level Output Voltage MODEOUT sinks 1mA - +100m V fOSC Oscillator Frequency 225 275 kHz TA Operating Free-Air Temperature -40 85 °C RL Class-D Power Amplifier Minimum Load Resistance 6 - Ω

Electrical Characteristics

VDD =12V, DGND=AGND=0V, TA= 25ο C (unless otherwise noted) APA3002 Symbol Parameter Test Condition Min. Typ. Max. Unit VDD Supply Voltage 8.5 - 14 V Class-D mode, V MODE=0V, VSD =5V, no load - 20 40 mA IDD VDD Supply Current VAROUT mode, VMODE=5V, VSD =5V, no load - 3 6 mA ISD VDD Shutdown Current VSD = 0V - 10 100 µA CLASS-D MODE, AV=15.7dB (VOLTAGE GAIN=RATIO OF THE FILTERED OUTPUT VOLTAGE TO INPUT VOLTAGE) THD+N = 1%, fin = 1kHz, RL = 6Ω - 10 - THD+N = 1%, fin = 1kHz, RL = 8Ω 6 7.5 - THD+N = 10%, fin = 1kHz, RL = 6Ω - 12 - PO Output Power THD+N = 10%, fin = 1kHz, RL = 8Ω - 9 - W THD+N Total Harmonic Distortion Plus Noise PO= 5W, fin= 1kHz, RL = 8Ω - 0.2 - % Crosstalk Channel Separation PO= 5W, fin=1kHz, CB=1µF - 90 - dB PSRR Power Supply Rejection Ratio RL = 8Ω , fin = 120Hz - 85 - dB Thermal Characteristics Note 2: Please refer to “Thermal Pad Consideration”. The Thermal Pad on the bottom of the IC should be soldered directly to the PCB’s Thermal Pad area connected to the ground plan by several thermal vias, and the PCB is a 2-layer, 5-inch square area with 2oz copper thickness.

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw4 APA3002 Electrical Characteristics (Cont.) VDD =12V, DGND=AGND=0V, TA= 25ο C (unless otherwise noted) APA3002 Symbol Parameter Test Condition Min. Typ. Max. Unit CLASS-D MODE, AV=15.7dB (VOLTAGE GAIN=RATIO OF THE FILTERED OUTPUT VOLTAGE TO INPUT VOLTAGE) (CONT.) S/N With A-Weighting Filter PO = 5W, RL = 8Ω - 85 - dB VOS Output Offset Voltage RL = 8Ω - - 20 mV Vn Noise Output Voltage - 250 - µV (rms) High side - 300 - Low side - 250 - Rds(on) Power MOSFET Drain-Source On-State Resistance IO=1A Total - 550 650 mΩ VAROUT OUTPUT, AV=10dB PO Output Power THD+N = 1%, fin = 1kHz, RL = 32Ω - 20 - mW THD+N = 10%, fin = 1kHz, RL = 32Ω - 25 - THD+N Total Harmonic Distortion Plus Noise fin= 1kHz, RL = 32Ω, PO = 14mW, - 0.05 - % VO= 1Vrms, RL=47kΩ, fin=1kHz - 0.005 - Crosstalk Channel Separation PO=14mW, RL = 32Ω , fin=1kHz, CB=1µF - 63 - dB PSRR Power Supply Rejection Ratio CB = 1µF, RL = 32Ω , fin =120Hz, VRR=0.2Vrms - 85 - dB Vos Output Offset Voltage RL = 32Ω - - 20 mV S/N With A-Weighting Filter PO= 20mW, RL = 32Ω , - 80 - dB Vn Noise Output Voltage CB = 1µF - 30 - µV (rms) LINEAR REGULATORS (LDO) V5VLDO 5V LDO Regulator Output I5VLDO =0-100mA, VSD =5V 4.5 5 5.5 V V2.5VREF 2.5V Reference Voltage No load 0.45X V5VLDO 0.50X V5VLDO 0.55X V5VLDO V PSRR Power Supply Rejection Ratio CB = 1µF, fin= 120Hz - 73 - dB

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw5 APA3002 Typical Operating Characteristics Efficiency vs. Output Power Efficiency vs. Output Power Output Power vs. Load Resistance Output Power vs. Supply Voltage Output Power vs. Supply Voltage THD+N vs. Output Power Output Power (W) Efficiency (%) VDD =12V RL=8Ω AV=36dB Bead filter AUX-0025 AES-17(20kHz) Class-D 100 0 2 4 6 8 10 12 Output Power (W) Efficiency (%) VDD =12V RL=8Ω +33µH AV=36dB Bead filter AUX-0025 AES-17(20kHz) Class-D 100 0 2 4 6 8 10 12 Output Power (W) Load Resistance (Ω ) VDD=14V THD+N=1% VDD=14V THD+N=10% VDD=8.5V THD+N=1% VDD=8.5V THD+N=10% Ci=1µF Av=36dB fin=1kHz AUX-0025 AES-17 (20kHz) Class-D 6 8 10 12 14 16 Supply Voltage (V) Output Power (W) THD+N=10% THD+N=1% Ci=1µF RL=8Ω AV=36dB fin=1kHz AUX-0025 AES-17 (20kHz) Class-D 8.5 9 10 11 12 13 14 Ci=1µF RL=6Ω Av=36dB fin=1kHz AUX-0025 AES-17 (20kHz) Class-D THD+N=10% THD+N=1% Output Power (W) Supply Voltage (V) 8.5 9 10 11 12 13 14 VDD=12V Ci=1µF RL=6Ω Av=15.7dB AUX-0025 AES-17 (20kHz) Class-D THD+N (%) Output Power (W) fin=1kHz fin=50Hz fin=15kHz 0.005 0.01 0.1 10m 20100m 1 10

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw6 APA3002 THD+N vs. Output Power THD+N vs. Frequency Typical Operating Characteristics (Cont.) THD+N vs. Frequency Crosstalk vs. Frequency Noise vs. Frequency THD+N vs. Output Power fin=1kHz fin=15kHz fin=50Hz Output Power (W) THD+N (%) VDD =14V Ci=1µF RL=8Ω AV=15.7dB AUX-0025 AES-17 (20kHz) Class-D 0.005 0.01 0.1 10m 20100m 1 10 RVDD =14V Ci=1µF RL=8Ω AV=15.7dB AUX-0025 AES-17 (20kHz) Class-D Frequency (Hz) THD+N (%) PO=7W PO=3.5W PO=0.5W 0.01 0.1 20 20K100 1K 10K VDD =14V Ci=1µF RL=8Ω PO=7W AUX-0025 AES-17 (20kHz) Class-D THD+N (%) Frequency (Hz) AV=36dB AV=20.8dB AV=10.7dB 0.01 0.1 20 20k100 1k 10k VDD =14V Ci=1µF RL=8Ω PO=3.5W AV=15.7dB AUX-0025 AES-17 (20kHz) Class-D Crosstalk (dB) Frequency (Hz) Right channel to Left channel Left channel to Right channel -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD =14V Ci=1µF RL=8Ω AV=15.6dB AUX-0025 LPF=22~22kHz A-Weighting Class-D Right Channel Frequency (Hz) Output Noise Voltage (µV) Left Channel 10µ 500µ 100µ 20 20k100 1k 10k VDD =12V Ci=1µF RL=8Ω Av=15.7dB AUX-0025 AES-17(20kHz) Class-D fin=1kHz fin=50Hz fin=20kHz THD+N (%) Output Power (W) 10m 10100m 1 5 0.001 0.01 0.1

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw7 APA3002 THD+N vs. Frequency THD+N vs. Frequency Typical Operating Characteristics (Cont.) Crosstalk vs. Frequency Noise vs. Frequency THD+N vs. Output Power THD+N vs. Frequency THD+N (%) Frequency (Hz) VDD =12V Ci=1µF RL=8Ω AV=15.7dB AUX-0025 AES-17(20kHz) Class-D PO=5W PO=0.5W PO=2.5W 0.01 0.1 20 20k100 1k 10k VDD =12V Ci=1µF RL=8Ω PO=2.5W AV=15.7dB AUX-0025 AES-17 (20kHz) Class-D Crosstalk (dB) Right channel to Left channel Left channel to Right channel Frequency (Hz) 20 20k100 500 10k-120 -100 -80 -60 -40 -20 Frequency (Hz) THD+N (%) VDD =12V Ci=1µF RL=8Ω PO=5W AUX-0025 AES-17 (20kHz) Class-D AV=10.7dBAV=20.8dB AV=36dB 0.01 0.1 20 20k100 1k 10k VDD =12V Ci=1µF RL=8Ω AV=15.6dB AUX-0025 LPF=22~22kHz A-Weighting Class-D Right Channel Frequency (Hz) Output Noise Voltage (µV) Left Channel 20 20k100 1k 10k 10µ 500µ 100µ fin=1kHz fin=15kHz fin=50Hz Output Power (W) THD+N (%) VDD =8.5V Ci=1µF RL=8Ω AV=15.7dB AUX-0025 AES-17 (20kHz) Class-D 10m 5100m 10.01 0.1 THD+N (%) Frequency (Hz) VDD =8.5V Ci=1µF RL=8Ω AV=15.7dB AUX-0025 AES-17(20kHz) Class-D PO=2.5W PO=0.5W PO=1.25W 20 20k100 1k 10k 0.01 0.1

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw8 APA3002 THD+N vs. Frequency Noise vs. Frequency Typical Operating Characteristics (Cont.) Input Resistance vs. Gain CMRR vs. Frequency Frequency Response Shutdown Attenuation vs. Frequency Frequency (Hz) THD+N (%) VDD =8.5V Ci=1µF RL=8Ω PO=2.5W AUX-0025 AES-17 (20kHz) Class-D AV=36dB AV=20.8dB AV=10.7dB 20 20k100 1k 10k0.01 0.1 VDD =8.5V Ci=1µF RL=8Ω AV=15.6dB AUX-0025 LPF=22~22kHz A-Weighting Class-D Right Channel Frequency (Hz) Output Noise Voltage (µV) Left Channel 20 20k100 1k 10k 10µ 500µ 100µ Gain (dB) Input Resistance (kΩ ) Class-D -50 -30 -10 10 30 500 100 120 140 160 Frequency (Hz) Common-Mode Rejection Ratio (dB) VDD =12V Ci=1µF RL=8Ω VO=1V AV=15.7dB AUX-0025 Class-D -70 -20 -60 -50 -40 -30 20 20k100 1k 10k VDD =12V Ci=1µF RL=8Ω PO=0.75W AUX-0025 Class-D Gain (dB) Frequency (Hz) Gain (36dB) Gain (15.7dB) Phase (36dB) Phase (15.7dB) Phase (degree) -150 +150 -100 -50 +50 +100 +40 +10 +15 +20 +25 +30 +35 10 100k100 1k 10k Shutdown Attenuation (dB) VDD =12V Ci=1µF RL=8Ω PO=1W AV=36dB VSD=0V AUX-0025 AES-17(20kHz) Class-D Frequency (Hz) 20 20k100 1k 10k-130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw9 APA3002 Mute Attenuation vs. Frequency Mode Attenuation vs. Frequency Typical Operating Characteristics (Cont.) Inter-modulation Performance PSRR vs. Frequency PSRR vs. Frequency PSRR vs. Frequency Frequency (Hz) Mute Attenuation (dB) VDD =12V Ci=1µF RL=8Ω PO=1W Volume=0V AUX-0025 AES-17(20kHz) Class-D 20 20k100 1k 10k-80 -70 -60 -50 -40 -30 -20 -10 Mode Attenuation (dB) Frequency (Hz) VDD =12V Ci=1µF RL=8Ω PO=1W AV=36dB Mode=5V AUX-0025 AES-17(20kHz) Class-D 20 20k100 1k 10k-130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 VDD =12V Ci=1µF fin=19kHz&20kHz RL=8Ω PO=1W AV=36dB AUX-0025 Class-D FFT (dB) Frequency (Hz) -140 -120 -100 -80 -60 -40 -20 50 20k100 1k 10k VDD =12V RL=8Ω VRR=0.5Vrms AV=36dB AUX-0025 AES-17(20kHz) Class-D Frequency (Hz) PSRR (dB) VRR: Ripple Voltage on VDD -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k TTTTTTTTT TTTTTT PSRR (dB) Frequency (Hz) VDD =12V RL=10kΩ VRR=0.5Vrms AV=20dB VAROUT VRR: Ripple Voltage on VDD -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k PSRR (dB) Frequency (Hz) TTTTTTTTT VDD =12V No load VRR=0.5Vrms LDO VRR: Ripple Voltage on VDD 20 20k100 1k 10k-100 -90 -80 -70 -60 -50 -40 -30 -20 -10

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw10 APA3002 THD+N vs. Output Power THD+N vs. Frequency Typical Operating Characteristics (Cont.) Crosstalk vs. Frequency Noise vs. Frequency Frequency Response THD+N vs. Output Voltage VDD =12V Ci=1µF COUT=150µF RL=10kΩ AV=10dB LPF=80kHz VAROUT THD+N (%) Output Voltage (V) fin=50Hz fin=1kHz fin=20kHz 0.001 0.01 0.1 0 2.5500m 1 1.5 2 VDD =12V Ci=1µF COUT=150µF RL=32Ω AV=10dB A-weighting VAROUT Frequency (Hz) Output Noise Voltage (V) 100µ 10µ 20 20k100 1k 10k RRR RRR VDD =12V Ci=1µF COUT=150µF RL=32Ω AV=10dB PO=14mW LPF=80kHz VAROUT Crosstalk (dB) Frequency (Hz) Left channel to Right channel Right channel to Left channel 20 20k100 1k 10k-90 -80 -70 -60 -50 -40 -30 -20 -10 VDD =12V Ci=1µF COUT=150µF RL=32Ω AV=10dB PO=2mW VAROUT Frequency (Hz) Gain (dB) Phase (Degree) Gain Phase +10 +120 +300 +140 +160 +180 +200 +220 +240 +260 +280 20 200k100 1k 10k Frequency (Hz) THD+N (%) VDD =12V Ci=1µF COUT=150µF RL=32Ω AV=10dB PO=14mW LPF=80kHz VAROUT 20 20k100 1k 10k0.01 0.1 VDD =12V Ci=1µF COUT=150µF RL=32Ω AV=10dB LPF=80kHz VAROUT THD+N (%) Output Power (W) fin=50Hz fin=1kHz fin=20kHz 0 30m5m 10m 15m 20m 25m0.01 0.1

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw11 APA3002 THD+N vs. Frequency Crosstalk vs. Frequency Typical Operating Characteristics (Cont.) Noise vs. Frequency Frequency Response Input Resistance vs. Gain Supply Current vs. Output Power Gain (dB) Input Resistance (kΩ ) VAROUT 100 120 140 160 0-60 -45 -30 -15 0 15 30 VDD =12V Ci=1µF COUT=150µF RL=10kΩ AV=10dB A-Weighting VAROUT Frequency (Hz) Output Noise Voltage (V) 20 20k100 1k 10k1µ 100µ 10µ VDD =12V Ci=1µF COUT=150µF RL=10kΩ AV=10dB PO=0.18V VAROUT Frequency (Hz) Gain (dB) Phase (Degree) Gain Phase 10 200k100 1k 10k +150 +230 +160 +170 +180 +190 +200 +210 +220 +10 TTTTTT TT TT TTTTVDD =12V Ci=1µF COUT=150µF RL=10kΩ AV=10dB VO=1.25V LPF=80kHz VAROUT Left channel to Right channel Right channel to Left channel Frequency (Hz) Crosstalk (dB) -120 -100 -80 -60 -40 -20 20 20k100 1k 10k Output Power (W) Supply Current (A) RL=8Ω &33µH fin=1kHz Ci=1µF Mono AUX-0025 AES-17 (20kHz) VDD=14V VDD=12V VDD=8.5V 0 2 4 6 8 10 120 0.2 0.4 0.6 0.8 1.0 1.2 Frequency (Hz) THD+N (%) VDD =12V Ci=1µF COUT=150µF RL=10kΩ AV=10dB VO=1.25V LPF=80kHz VAROUT 20 20k100 1k 10k 0.001 0.01 0.1

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw12 APA3002 Supply Current vs. Supply Voltage Typical Operating Characteristics (Cont.) 0 5 10 15 Supply Current (mA) Supply Voltage (V) No Load

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw13 APA3002 Pin Description PIN NO. NAME I/O FUNCTION SD I Shutdown mode control signal input. Pulling the voltage on SD below 0.8V makes the IC enter low-power shutdown mode with 10µA (typical) IDD. 2 RIN- I Right channel negative input. 3 RIN+ I Right channel positive input. 4 2.5VREF O 2.5V reference for analog circuits. 5 LIN+ I Left channel positive input. 6 LIN- I Left channel negative input. 7 LDOREF O 5V reference output (5V LDO), connect it to VREF pin. 8 VREF I Gain control section’s reference voltage input. 9 VARDIFF I Input pin to set the difference in gain between the VAROUT and Class-D outputs by using the DC voltage. Connect this pin to the ground or LDOREF when the VAROUT is not used. 10 VARMAX I Input pin to set the maximum gain of VAROUT by using the DC voltage. Connect this pin to ground or LDOREF directly when the VAROUT is not used. 11 VOLUME 1 Input pin to set the gain of VAROUT and Class-D outputs by using the DC voltage. 12 REFGND - Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DAC ground to this terminal. 13 LBS- I/O Left channel bootstrap power input for negative high-side MOSFET. 14,15,22 ,23 LPVDD - Power supply for left channel H-bridge. 16,17 LOUT- O Class-D left channel negative output. 18,19 LPGND - Power ground for left channel H-bridge. 20,21 LOUT+ O Class-D left channel positive output. 24 LBS+ I/O Left channel bootstrap power input for positive high-side MOSFET. 25 LCLAMP - Left channel internal voltage supply output for bootstrap capacitor. 26,30 AGND - Analog ground. 27 ROSC I/O Voltage of ROSC pin equal 0.125VDD, current setting resistor for internal ramp generator. 28 COSC I/O Charge/Discharge capacitor for generating triangle wave. 29 5VLDO O Internal 5V regulator output for external headphone driver used. 31 LVAROUT O Left channel variable audio output, for external headphone driver. 32 RVAROUT O Right channel variable audio output, for external headphone driver. 33 AVDD - Analog power supply (8.5 to 14V).

34 MODE I

Control pin for amplifier operation. A logic high places the amplifier in variable output mode, and the Class-D output will disable; a logic low places the amplifier in variable output mode (line-level output for external amplifier) and stereo Class-D outputs.

35 MODEOUT O

Inverse output of MODE pin, this pin can control the external headphone driver’s (APA4801) mute pin for changing operation from speaker operation to headphone operation. Leave this pin unconnected when the external headphone driver is not in using. 36 RCLAMP - Right channel internal voltage supply output for bootstrap capacitor. 37 RBS+ I/O Right channel bootstrap voltage input for positive high-side MOSFET. 38,39,46 ,47 RPVDD - Power supply for right channel H-bridge. 40,41 ROUT+ O Class-D right channel positive output. 42,43 RPGND - Power ground for right channel H-bridge. 44,45 ROUT- O Class-D right channel negative output. 48 RBS- I/O Right channel bootstrap voltage input for negative high-side MOSFET.

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw14 APA3002 Block Diagram Startup protection logic Gain Control Biases Reference Gain Adj. Gain Adj. Gate Drive De-glitch & Modulation Logic Gate Drive Gain Adj. Gate Drive De-glitch & Modulation Logic Gate Drive Gain Adj. RBS- RPVDD ROUT- RPGND RBS+ RPVDD ROUT+ RPGND LBS- LPVDD LOUT- LPGND LBS+ LPVDD LOUT+ LPGND RVAROUT RIN- RIN+ LIN- LIN+ LVAROUT Over-Current Protection Thermal Shutdown 5VLDO ok AVDD ok 5VLDO RAMP GEN. VOLTAGE CLAMP GEN. VOLTAGE CLAMP GEN. ROSC COSC VREF VOLUME VARMAX VARDIFF REFGND 2.5VREF 5VLDO LDOREFTTL Input BufferSD RCLAMP LCLAMP AVDD AGND

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw15 APA3002 Operating Mode Selection Table MODE SD Operating mode H L Shutdown mode L H Class-D operation H H Class-D disable, VAROUT output. Class-D DC Volume Control Table GAIN Voltage range (% of VVREF) Increasing VVOLUME Decreasing VVOLMUE (dB) (%) (%) -75 0 -4.5 0 -2.9 13.2 50.8 -53 48.9 -51.0 15.7 53 -55.2 51.0 -53.2 25.9 61.8 -64 59.8 -62.0 28.4 64 -66.2 62.0 -64.2 36 >70.6 >68.6

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw16 APA3002 GAIN Voltage range (% of V VREF) Increasing V VOLUME Decreasing V VOLMUE (dB) (%) (%) -66 0 -4.5 0 -2.9 12.4 64 -66.2 62.0 -64.2 20.0 >70.6 >68.6 VAROUT VOLUME Control Table

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw17 APA3002 Typical Application Circuits ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. TOP VIEW APA3002 50kΩ 50kΩ 50kΩ 1µF 1µF 1µF 1µF 1µF Bead 10µF 10nF 0.1µF 10nF 0.1µF 1nF 1nF Bead SPEAKER VDD VDD Bead 10µF 10nF 0.1µF 10nF 0.1µF 1nF1nF Bead SPEAKER VDD VDD 1µF 0.1µF 220pF 1µF 120kΩ SHUTDOWNRIN- LIN- Left channel Right channel 10µF 0.1µF MODEOUT LVAROUT RVAROUT MODE VDD CBS(R-) CBS(R+) Ci(RIN+) Ci(RIN-) CB Ci(LIN-) Ci(LIN+) RVARDIFF RVARMAX RVOLUME CBS(L-) CBS(L+) CCLAMP(R) COSC ROSC CCLAMP(L) SD RIN- RIN+ 2.5VREF LIN+ LIN- LDOREF VREF VARDIFF VARMAX VOLUME REFGND LBS- LPVDD LPVDD LOUT- LOUT- LPGND LPGND LOUT+ LOUT+ LPVDD LPVDD LBS+ LCLAMP AGND ROSC COSC 5VLDO AGND LVAROUT RVAROUT AVDD MODE MODEOUT RCLAMP RBS+ RPVDD RPVDD ROUT+ ROUT+ RPGND RPGND ROUT- ROUT- RPVDD RPVDD RBS- AGnd PGnd

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw18 APA3002 Typical Application Circuits (Cont.) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. TOP VIEW APA3002 50kΩ 50kΩ 50kΩ 1µF 1µF 1µF 1µF 1µF 1µF 10µF 0.1µF 220pF 1µF 120kΩ SHUTDOWNRIN- LIN- 10µF 0.1µF VDD 120kΩ Ci(RIN+) Ci(RIN-) CB Ci(LIN-) Ci(LIN+) RVARDIFF RVARMAX RVOLUME CCLAMP(R) CCLAMP(L) COSC ROSC SD RIN- RIN+ 2.5VREF LIN+ LIN- LDOREF VREF VARDIFF VARMAX VOLUME REFGND LBS- LPVDD LPVDD LOUT- Bead 10µF 10nF 0.1µF 10nF 0.1µF 1nF 1nF Bead SPEAKER VDD VDD Left channel CBS(L-) CBS(L+) LOUT- LPGND LPGND LOUT+ LOUT+ LPVDD LPVDD LBS+ LCLAMP AGND ROSC COSC 5VLDO AGND LVAROUT RVAROUT AVDD MODE MODEOUT RCLAMP RBS+ RPVDD RPVDD ROUT+ Bead 10µF 10nF 0.1µF 10nF 0.1µF 1nF1nF Bead SPEAKER VDD VDD Right channel CBS(R-) CBS(R+) ROUT+ RPGND RPGND ROUT- ROUT- RPVDD RPVDD RBS- AGnd PGnd APA4801 Ring Headphone Jack Sleeve Control Pin Tip 1µF 1µF 220µF 220µF 1kΩ 1kΩ OUTA MUTE INPUTA VSSINPUTB BIAS OUTB VDD 4.7µF

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw19 APA3002

Application Information

Figure1. APA3002 Output Waveform (Voltage & Current) The value of C i must be considered carefully because it directly affects the low frequency performance of the circuit. Consider the example, where R i is 10k Ω and the specification calls for a flat bass response down to 40Hz. The equation is reconfigured as below: When the input resistance variation is considered, the C i is 0.40 µF, so a value in the range of 0.47 µF to 1.0 µF would be chosen. A further consideration for this ca- pacitor is the leakage path from the input source through the input network (Ri + Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, In the typical application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri form a high-pass filter with the corner frequency is determined in the following equation: Input Capacitor (Ci) Input Resistor (Ri) In order to achieve the 32 steps gain setting, the Ri varies the input resistance network (Ri & Rf) of amplifier. The input resistor’s range from the smallest to the maximum is about 15 times, therefore, the input high-pass filter’s low cutoff frequency will change 15 times from low to high. The cutoff frequency can be calculated by equation Square Wave Into the Speaker To apply the square wave into the speaker may cause the voice coil of speaker jumps out the air gap and defaces the voice coil. However, this depends on if the amplitude of square wave is high enough and the bandwidth of speaker is higher than the square wave’s frequency. For 250kHz switching frequency, this is not an issue for the speaker because the frequency is beyond the audio band, and can’t significantly move the voice coil, as cone move- ment is proportional to 1/f2 for frequency out of audio band. The APA3002 modulation scheme is shown in Figure 1, the outputs OUT+ and OUT- are in phase with each other when no input signals. When output > 0V, the duty cycle of OUT+ is greater than 50% and OUT- is less than 50%; on the contrary, when output <0V, the duty cycle of OUT+ is less than 50% and OUT- is greater than 50%. This method reduces the switching current across the load and reduces the I2R loss in the load that improves the amplifier’s efficiency. This modulation scheme has very short pulses across the load. This makes the small ripple current and very little loss on the load, and the LC filter can be eliminated in most applications. Adding the LC filter can increase the efficiency by filter the ripple current. OUT+ OUT OUT IOUT IOUT Output = 0V Output > 0V OUT IOUT Output < 0V OUT- OUT+ OUT- OUT+ OUT- (OUT+)-(OUT-) (OUT+)-(OUT-) (OUT+)-(OUT-) (1) CR2 ii )C(highpass (2) fR2 ci i

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw20 APA3002 Application Information (Cont.) Input Capacitor (Ci) (Cont.) especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications because the DC level of the amplifiers’ inputs is held at 2.5VREF . Please note that it is important to confirm the capacitor polarity in the application. COSC & ROSC The Class-D amplifier’s switching frequency is deter- mined by the component that connected to ROSC (pin) and COSC (pin). The frequency can be calculated by the following equation: BS+ &BS- Capacitor (CBS) Since the Full-bridge output stages are only using the N- channel power MOSFET, the high-side MOSFET’s driver needs bootstrap circuit to turn on the high side power MOSFET correctly. A 10nF/35V ceramic capacitor is recommended. CLAMP Capacitor (CCLAMP) These capacitors are regulated the clamp voltage of N- channel power MOSFET’s gate voltage, ensuring the maximum gate-to-source voltage of the MOSFET not to exceed. 1µF/25V capacitors are recommended. Power Supply Decoupling (Cs) The APA3002 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to en- sure the output total harmonic distortion (THD+N) is as low as possible. Power supply decoupling also pre- vents the oscillations being caused by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two dif- ferent types of capacitors that target on different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically is 0.1µF which is placed as close as possible to the device VDD lead to achieve the best performance. For filtering lower frequency noise signals, a large alu- minum electrolytic capacitor of 10µF or greater placed near the audio power amplifier is recommended. Ferrite Bead Selection If the traces from the APA3002 to speaker are short, the ferrite bead filters can reduce the high frequency radiated to meet the FCC & CE’s requirements. A ferrite that has very low impedance at low frequencies and high impedance at high frequencies (above 1 MHz) is recommended. Output LC Filter If the traces from the APA3002 to speaker are short, it doesn’t require output filter for FCC & CE standard. Fig- ure 2 is an example for adding the LC filter, it’s recom- mended for the situation that the trace from amplifier to speaker is too long, and needed to eliminate the radiated emission or EMI. The bootstrap capacitors are like floating power supply for high side N-channel power MOSFET gate driver. The bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side N-channel power MOSFET turn-on at high side switching cycle. At the high-side turn- on cycle, the voltage of bootstrap capacitors will decrease through the leakage path. The bootstrap voltage can de- crease below the minimum Vgs that required to keep the high-side N-channel power MOSFET turn-on, if driving into heavy clipping with a less than 50Hz sine wave. When this occurs, the output power MOSFET becomes source- follower and the output drops from VDD to approximately Vclamp. Driving a square wave at low frequencies is not a design consideration for majority application, so the 10nf boot- strap capacitor is recommended. If the low frequency is a concern, please increase the bootstrap capacitor value to hold the gate voltage for a longer period and the voltage drop will not occur. (3) CR 6.6f oscosc osc =

Copyright  ANPEC Electronics Corp. Figure 4. VAROUT Volume Control Flow table “VAROUT VOLUME Control Table”. nels to avoid the un-comfortable listening of headphone. avoid unwanted state change. 1µF and 0.1µF are sufficient enough.

Copyright  ANPEC Electronics Corp. Figure 5. TQFP7x7-48 thermal pad layout recommenda-

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw24 APA3002

Package Information

D E Pin 1 SYMBOL MIN. MAX. 0.80 0.00 0.18 0.30 5.50 5.80 0.05 5.50 A b D E e L MILLIMETERS A3 0.20 REF TQFN7x7-48 0.35 0.45 5.80

0.008 REF

MIN. MAX. INCHES 0.031 0.000 0.007 0.012 0.217 0.228 0.217 0.014 0.018 0.50 BSC 0.020 BSC K 0.20 0.008 6.90 7.10 0.272 0.280 6.90 7.10 0.272 0.280 0.70 0.228 0.028 0.002 Note : 1. Followed from JEDEC MO-220 WKKD-4. Pin 1 Corner E2KL e A b

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw25 APA3002 D E eb A2A1 A c E2EXPOSED PAD 0.25 SEATING PLANE GAUGE PLANE L 0.006 0o0 7o0o7o 0.50 BSC 0.020 BSC 0.45 0.75 0.018 0.030 SYMBOL MIN. MAX. 1.20 0.05 0.17 0.27 0.09 0.20 0.15 A b c D E e MILLIMETERS A2 0.95 1.05 TQFP7x7-48P MIN. MAX. INCHES 0.047 0.002 0.037 0.041 0.007 0.011 0.004 0.008 3.00 0.118 3.00 4.50 4.50 0.177 0.118 0.177 8.80 9.20 0.346 0.362 6.90 7.10 0.272 0.280 8.80 6.90 7.10 9.20 0.346 0.272 0.362 0.280 Note : 1. Followed from JEDEC MS-026 ABC. 2. Dimension "D1" and "E1" do not include mold protrusions. Allowable protrusions is 0.25 mm per side. "D1" and "E1" are maximun plasticbody size dimensions including mold mismatch.

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw26 APA3002 Carrier Tape & Reel Dimensions Package Type Unit Quantity TQFP7x7-48P Tape & Reel 2500 TQFN7x7-48 Tape & Reel 2500 Devices Per Unit Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 TQFP7x7-48P Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 TQFN7x7-48 (mm) A AB W F T P0OD0 B SECTION B-B SECTION A-A OD1 H A d

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw27 APA3002 Taping Direction Information TQFP7x7-48P TQFN7x7-48 USER DIRECTION OF FEED USER DIRECTION OF FEED

Copyright  ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 www.anpec.com.tw28 APA3002 Classification Profile Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds Average ramp-up rate (Tsmax to TP) 3 °C/second max. 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 183 °C 60-150 seconds 217 °C 60-150 seconds Peak package body Temperature (Tp)* See Classification Temp in table 1 See Classification Temp in table 2 Time (tP) within 5°C of the specified classification temperature (Tc) 20 seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. Time 25°C to peak temperature 6 minutes max. 8 minutes max. * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Classification Reflow Profiles

Copyright  ANPEC Electronics Corp. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Table 2. Pb-free Process – Classification Temperatures (Tc)