APA2120 ANPEC | Alldatasheet
Document overview
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Technical content
Features
- •••• Low operating current with 14mA
- Improved depop circuitry to eliminate turn-on and turn off transients in outputs
- High PSRR
- 32 steps volume adjustable by DC voltage with hysteresis
- 2W per channel output power into 4Ω load at 5V, BTL mode
- Two output modes allowable with BTL and SE modes selected by SE/BTL pin
- Low current consumption in shutdown mode (50µA)
- Short Circuit Protection
- Power off depop circuit integration
- TSSOP-24 with or without thermal pad package
Applications
Ordering and Marking Information * TSSOP-P is a standard TSSOP package with a thermal pad exposure on the bottom of the package. APA2120/1 is a monolithic integrated circuit, which provides precise DC volume control, and a stereo bridged audio power amplifiers capable of producing 2.7W(2.0W) into 3Ω with less than 10% (1.0%) THD+N. The attenuator range of the volume control in APA2120/1 is from 20dB (DC_Vol=0V) to -80dB (DC_Vol=3.54V) with 32 steps. The advantage of internal gain setting can be less components and PCB area. Both of the depop circuitry and the thermal shutdown protection circuitry are integrated in APA2120/1, that reduce pops and clicks noise dur- ing power up or shutdown mode operation. It also improves the power off pop noise and protects the chip from being destroyed by over temperature and short current failure. To simplify the audio system design, APA2120/1 combines a stereo bridge-tied loads (BTL) mode for speaker drive and a stereo single-end (SE) mode for headphone drive into a single chip, where both modes are easily switched by the SE/BTL input control pin signal. Besides, the multiple input selection is used for portable audio system.
- NoteBook PC
- LCD Monitor or TV A P A 2 1 2 0/1 H a n d lin g C o d e T e m p . R a n g e P a c k a g e C o d e P a c k a g e C o d e R : T S S O P -P * T e m p . R a n g e I : - 4 0 to 8 5 C H a n d lin g C o d e T U : T u b e T R : T a p e & R e e l T Y : T ra y A P A 2 1 2 0 /1 R : A P A 2 1 2 0 /1 X X X X X X X X X X - D a te C o d e
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw Block Diagram (Over operating free-air temperature range unless otherwise noted.) Symbol Parameter Rating Unit VDD Supply Voltage Range -0.3 to 6 V VIN Input Voltage Range, SE/BTL, HP/LINE, SHUTDOWN, PCBEN -0.3 to VDD+0.3 V TA Operating Ambient Temperature Range -40 to 85 TJ Maximum Junction Temperature Intermal Limited*1 TSTG Storage Temperature Range -65 to +150 TS Soldering Temperature,10 seconds 260 VESD Electrostatic Discharge -3000 to 3000*2 -200 to 200*3 V PD Power Dissipation Intermal Limited Absolute Maximum Ratings Shutdow n ckt HP/LINE Volum e Control M UX M UX SE/BTL LOUT+ LOUT- ROUT+ ROUT- LLINEIN RLINEIN LHPIN RHPIN HP/LINE SE/BTL SHUTDOWN RBYPASS LBYPASS VOLUME BYPASS BYPASS PC-BEEP ckt PCBEEP Clock G en CLK For APA2121 Note: 1.APA2120/1 integrated internal thermal shutdown protection when junction temperature ramp up to 150°C 2.Human body model: C=100pF, R=1500Ω, 3 positives pulse plus 3 negative pulses 3.Machine model: C=200pF, L=0.5µF, 3 positive pulses plus 3 negative pulses
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw Recommended Operating Conditions Min. Max. Unit Supply Voltage, VDD 4.5 5.5 V SHUTDOWN, PCBEN High level threshold voltage, VIH SE/BTL , HP/LINE V SHUTDOWN, PCBEN 1.0 Low level threshold voltage, VIL SE/BTL , HP/LINE V Common mode input voltage, VICM VDD-1.0 V VDD=5V, -20°C<TA<85°C (unless otherwise noted)
Electrical Characteristics
Thermal Resistance from Junction to Ambient in Free Air TSSOP-P* K/W APA2120/1 Symbol Parameter Test Condition Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.5 V SE/BTL=0V IDD Supply Current SE/BTL=5V 8.0 mA ISD Supply Current in Shutdown Mode SE/BTL=5V SHUTDOWN=0V µA IIH High input Current 900 nA IIL Low Input Current 900 nA VOS Output Differential Voltage mV * 5 in2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias. The thermal pad on the TSSOP_P package with solder on the printed circuit board.
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw APA2120/1 Symbol Parameter Test Condition Min. Typ. Max. Unit THD=10%, RL=3Ω, Fin=1kHz 2.7 THD=10%, RL=4Ω, Fin=1kHz 2.3 THD=10%, RL=8Ω, Fin=1kHz 1.5 THD=1%, RL=3Ω, Fin=1kHz 2.0 THD=1%, RL=4Ω, Fin=1kHz 1.9 PO Maximum Output Power THD=0.5%, RL=8Ω, Fin=1kHz 1.1 W PO=1.5W, RL=4Ω, Fin=1kHz 0.05 THD+N Total Harmonic Distortion Plus Noise PO=1W, RL=8Ω, Fin=1kHz 0.07 PSRR Power Ripple Rejection Ratio VIN=0.1Vrms, RL=8Ω, CB=1µF, Fin=120Hz dB Xtalk Channel Separation CB=1µF, RL=8Ω, Fin=1kHz dB S/N Signal to Noise Ratio PO=1.1W, RL=8Ω, A_wieght dB Operating Characteristics, BTL mode VDD=5V,TA=25°C,RL=4Ω, Gain=2V/V (unless otherwise noted) Electrical Characteristics (Cont.) Operating Characteristics, SE mode VDD=5V,TA=25°C,RL=4Ω, Gain=1V/V (unless otherwise noted) APA2120/1 Symbol Parameter Test Condition Min. Typ. Max. Unit THD=10%, RL=8Ω, Fin=1kHz 400 THD=10%, RL=32Ω, Fin=1kHz 110 THD=1%, RL=8Ω, Fin=1kHz 320 PO Maximum Output Power THD=1%, RL=32Ω, Fin=1kHz mW PO=250mW, RL=8Ω, Fin=1kHz 0.08 THD+N Total Harmonic Distortion Plus Noise PO=75mW, RL=32Ω, Fin=1kHz 0.08 PSRR Power Ripple Rejection Ratio VIN=0.1Vrms, RL=8Ω, CB=1µF, Fin=120Hz dB Xtalk Channel Separation CB=1µF, RL=32Ω, Fin=1kHz 100 dB S/N Signal to Noise Ratio PO=75mW, SE, RL=32Ω, A_wieght 100 dB
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw Pin Description LOUT- LHPIN RBYPASS GND PCBEN VOLUME LOUT+ LLINEIN LBYPASS PVDD GND BYPASS GND RLINEIN SHUTDOWN ROUT+ RHPIN SE/BTL PVDD GND PC-BEEP VDD CLK ROUT- APA2120 TOP View LOUT- LHPIN RBYPASS GND HP/LINE VOLUME LOUT+ LLINEIN LBYPASS PVDD GND BYPASS GND RLINEIN SHUTDOWN ROUT+ RHPIN SE/BTL PVDD GND PC-BEEP VDD CLK ROUT- APA2121 TOP View APA2120/1 Bottom View Thermal Pad Multiple Input Selection PCBEEP Control Input APA2120 SE/BTL PCBEN APA2121 HP/LINE
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw Pin Name No Config.
Description
1,12, 13,24 Ground connection, Connected to thermal pad. PCBEN I/P BEEP mode control input, active H, for APA2120 only HP/LINE I/P Multi-input selection input, headphone mode when held high, line-in mode when held low for APA2121 only. VOLUME Input signal for internal volume gain setting. LOUT+ O/P Left channel positive output in BTL mode and SE mode. LLINEIN I/P Left channel line input terminal, selected when HP/LINE is held low. LHPIN O/P Left channel headphone input terminal, selected when HP/LINE is held high. PVDD 7,18 Supply voltage only for power amplifier. RBYPASS I/P Right channel bypass voltage. LOUT- O/P Left channel negative output in BTL mode and high impedance in SE mode. LBYPASS I/P Left channel bias voltage generator. BYPASS Bias voltage generator PC_BEEP I/P PCBEP signal input SE/BTL I/P Output mode control input, high for SE output mode and low for BTL mode. ROUT- O/P Right channel negative output in BTL mode and high impedance in SE mode. CLK Clock signal generator VDD Supply voltage for internal circuit excepting power amplifier. RHPIN I/P Right channel headphone input terminal, selected when HP/LINE is held high. ROUT+ O/P Right channel positive output in BTL mode and SE mode. SHUTDOWN I/P It will be into shutdown mode when pull low. RLINEIN I/P Right channel line input terminal, selected when HP/LINE is held low. Pin Function Description
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw SE/BTL SHUTDOWN PC-BEEP Operating mode X L Disable Shutdown mode L H Disable Line input, BTL out H H Disable HP input, SE out X X Enable PCBEEP input, BTL out SE/BTL HP/LINE SHUTDOWN PC-BEEP Operating mode X X L Disable Shutdown mode L L H Disable Line input, BTL out L H H Disable HP input, BTL out H L H Disable Line input, SE out H H H Disable HP input, BTL out X X X Enable PCBEEP input, BTL out For APA2121 Control Input Table For APA2120
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw Typical Application Circuit Shutdown ckt Volume Control MUX MUX SE/BTL LOUT+ LOUT- ROUT+ ROUT- LLINEIN RLINEIN LHPIN RHPIN PCBEN SE/BTL SHUTDOWN RBYPASS LBYPASS VOLUME BYPASS BYPASS PC-BEEP ckt PCBEEP Clock Gen CLK Ring Headphone Jack Sleeve Control Pin Tip SE/BTL 0.47µF 2.2µF 1µF 1µF 1µF 1µF 220µF 220µF 1kΩ 1kΩ L-LINE R-LINE R-HP L-HP VDD 50kΩ VDD 100kΩ BEEP Signal Shutdown Signal VDD VDD PVDD GND 47nF 100µF 0.1µF PCBEN Signal APA2120
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw Typical Application Circuit Shutdown ckt HP/LINE Volume Control MUX MUX SE/BTL LOUT+ LOUT- ROUT+ ROUT- LLINEIN RLINEIN LHPIN RHPIN RBYPASS LBYPASS VOLUME BYPASS BYPASS PC-BEEP ckt PCBEEP Clock Gen CLK Ring Headphone Jack Sleeve Control Pin Tip 0.47µF 2.2µF 1µF 1µF 1µF 1µF 220µF 220µF 1kΩ 1kΩ L-LINE R-LINE R-HP L-HP VDD 50kΩ VDD 100kΩ BEEP Signal Shutdown Signal HP/LINE Signal VDD VDD PVDD GND 47nF 100µF 0.1µF HP/LINE SE/BTL SHUTDOWN SE/BTL APA2121
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw Volume Control Table_BTL Mode Gain(dB) High(V) Low(V) Hysteresis(mV) Recommended Voltage(V) 0.12 0.00 0.23 0.17 0.20 0.34 0.28 0.31 0.46 0.39 0.43 0.57 0.51 0.54 0.69 0.62 0.65 0.80 0.73 0.77 0.91 0.84 0.88 1.03 0.96 0.99 1.14 1.07 1.10 1.25 1.18 1.22 1.37 1.29 1.33 1.48 1.41 1.44 1.59 1.52 1.56 1.71 1.63 1.67 -10 1.82 1.74 1.78 -12 1.93 1.85 1.89 -14 2.05 1.97 2.01 -16 2.16 2.08 2.12 -18 2.28 2.19 2.23 -20 2.39 2.30 2.35 -22 2.50 2.42 2.46 -24 2.62 2.53 2.57 -26 2.73 2.64 2.69 -28 2.84 2.75 2.80 -30 2.96 2.87 2.91 -32 3.07 2.98 3.02 -34 3.18 3.09 3.14 -36 3.30 3.20 3.25 -38 3.41 3.32 3.36 -40 3.52 3.43 3.48 -80 5.00 3.54 Supply Voltage Vdd=5V
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw 0.01 0.1 20k 100 Typical Characteristics THD+N vs. Frequency Frequency (Hz) THD+N (%) VDD=5V RL=3Ω Po=1.75W BTL AV=2 AV=5 AV=10 0.01 0.1 20k 50 100 200 500 1k THD+N vs. Frequency Frequency (W) THD+N (%) VDD=5V RL=4Ω Po=1.5W BTL 0.01 0.1 100m 200m 500m 800m THD+N vs. Output Power Output Power (W) THD+N (%) VDD=5V RL=4Ω AV=2 BTL f=20Hz f=20kHz f=1kHz 0.01 0.1 10m 100m THD+N vs. Output Power Output Power (W) THD+N (%) VDD=5V RL=3Ω AV=2 BTL f=20Hz f=20kHz f=1kHz AV=2 AV=5 AV=10
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw 0.01 0.1 20k 100 0.01 0.1 10m 100m Typical Characteristics (Cont.) THD+N vs. Output Power Output Power (W) THD+N (%) THD+N vs. Frequency Frequency (Hz) THD+N (%) VDD=5V RL=8Ω AV=2 BTL f=20Hz f=20kHz f=1kHz VDD=5V RL=8Ω Po=250mW SE 0.01 0.1 20k 100 THD+N vs. Frequency Frequency (Hz) THD+N (%) VDD=5V RL=8Ω Po=1.0W BTL AV=2 AV=5 AV=10 AV=1 AV=5 AV=2.5 0.01 0.1 10m 500m 100m THD+N vs. Output Power Output Power (W) THD+N (%) VDD=5V RL=8Ω AV=2 BTL f=20Hz f=20kHz f=1kHz
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw 0.01 0.1 10m 200m 50m 100m Typical Characteristics (Cont.) THD+N vs. Output Power Output Power (W) THD+N (%) VDD=5V RL=32Ω AV=1 BTL f=20Hz f=20kHz f=1kHz 0.01 0.1 20k 50 100 200 500 1k THD+N vs. Frequency Frequency (Hz) THD+N (%) VDD=5V RL=16Ω Po=100mW SE AV=2 AV=1 AV=2.5 0.01 0.1 10m 300m 100m THD+N vs. Output Power Output Power (W) THD+N (%) VDD=5V RL=16Ω AV=1 BTL f=20Hz f=20kHz f=1kHz 0.01 0.1 20k 100 THD+N vs. Frequency Frequency (Hz) THD+N (%) VDD=5V RL=32Ω Po=75mW SE AV=1 AV=5 AV=2.5
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw 0.01 0.1 100m 500m 0.01 0.1 20k 100 Typical Characteristics (Cont.) THD+N vs. Frequency Frequency (Hz) THD+N (%) THD+N vs. Output Swing Output Swing (VRMS) THD+N (%) VDD=5V RL=10Ω Vo=1VRMS SE VDD=5V RL=10Ω AV=1 SE f=20Hz f=20kHz f=1kHz AV=1 AV=5 AV=2.5 -120 -100 -80 -60 -40 -20 20k 100 Crosstalk vs. Frequency Frequency (Hz) Crosstalk (dB) VDD=5V RL=32Ω Po=75mW AV=1 SE R-ch to L-ch L-ch to R-ch -120 -100 -80 -60 -40 -20 20k 100 Crosstalk vs. Frequency Frequency (Hz) Crosstalk (dB) VDD=5V RL=8Ω Po=1.0W AV=2 BTL R-ch to L-ch L-ch to R-ch
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 100u 10u 20u 50u 20k 100 100u 10u 20u 50u 20k 100 Typical Characteristics (Cont.) Noise Floor vs. Frequency Frequency (Hz) Noise Floor (µVRMS) Noise Floor vs. Frequency Frequency (Hz) Power Dissipation vs. Output Power Output Power (W) Power Dissipation (W) Noise Floor (µVRMS) VDD=5V RL=32Ω AV=1 SE No Filter A-Weight VDD=5V RL=10KΩ AV=1 SE No Filter A-Weight VDD=5V AV=1 SE RL=32Ω RL=16Ω RL=8Ω 100u 10u 20u 50u 20k 100 Noise Floor vs. Frequency Frequency (Hz) Noise Floor (µVRMS) VDD=5V RL=8Ω AV=2 BTL No Filter A-Weight
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.5 4.5 5.5 Output Power vs. Supply Voltage Supply Voltage (V) Output Power (W) RL=8Ω AV=2 BTL THD+N=10% THD+N=1% 100 120 140 160 2.5 3.5 4.5 5.5 Typical Characteristics (Cont.) Output Power vs. Supply Voltage Supply Voltage (V) Output Power (mW) RL=32Ω AV=1 SE THD+N=10% THD+N=1% 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 0.5 1.5 2.5 Power Dissipation vs. Output Power Output Power (W) Power Dissipation (W) VDD=5V AV=2 BTL RL=3Ω RL=4Ω RL=8Ω 2.5 7.5 12.5 17.5 1.5 2.5 3.5 4.5 5.5 Supply Current vs. Supply Voltage Supply Voltage (V) Suuply Current (mA) No Load SE BTL
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw 20k 100 +12 +10 20k 100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 4 8 12 1620 24 2832 3640 44 4852 566064 0.5 1.5 2.5 4 8 12 1620 24 2832 3640 44 4852 5660 64 Typical Characteristics (Cont.) Output Power vs. Load Resistance Load Resistance (Ω) Output Power (W) Output Power vs. Load Resistance Load Resistance (Ω) Output Power (W) Close Loop Response Frequency (Hz) Close Loop Response Frequency (Hz) Loop Gain (dB) Loop Gain (dB) VDD=5V AV=2 BTL THD+N=10% THD+N=1% VDD=5V AV=1 SE THD+N=10% THD+N=1% AV=2 AV=5 AV=10 VDD=5V RL=32Ω AV=1 SE CO=330µF AV=1 AV=2.5 AV=5 VDD=5V RL=8Ω AV=2 BTL CO=330µF
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw -80 -60 -40 -20 20k 100 Typical Characteristics (Cont.) PSRR vs. Frequency Frequency (Hz) Ripple Rejection Ratio (dB) VDD=5V Vin=100mVRMS RL=8Ω Cbypass=2.2µF BTL SE
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw Vbias Circuit OUT+ OUT- RL OP1 OP2 Volume Control amplifier output signal Application Descriptions BTL Operation BTL Operation (Cont.) Four times the output power same conditions. A BTL configuration, such as the one used in APA2120/1, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUT+, ROUT-, LOUT+, and LOUT-, are biased at half-supply, no need DC voltage exists across the load. This elimi- nates the need for an output coupling capacitor which is required in a single supply, SE configuration. Single-Ended Operation Consider the single-supply SE configuration shown Application Circuit. A coupling capacitor is required to block the DC offset voltage from reaching the load. These capacitors can be quite large (approximately 33µF to 1000µF) so they tend to be expensive, oc- cupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system (refer to the Output Coupling Capacitor). The rules described still hold with the addition of the following relationship: The APA2120/1 output stage (power amplifier) has two pairs of operational amplifiers internally, allowed for different amplifier configurations. Output SE/BTL Operation The ability of the APA2120/1 to easily switch between BTL and SE modes is one of its most important costs saving features. This feature eliminates the require- ment for an additional headphone amplifier in appli- cations where internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated. Figure 1: APA2120/1 internal configuration (each channel) The power amplifier’s OP1 gain is setting by internal unity-gain and input audio signal is come from inter- nal volume control amplifier, while the second ampli- fier OP2 is internally fixed in a unity-gain, inverting configuration. Figure 1 shows that the output of OP1 is connected to the input to OP2, which results in the output signals of with both amplifiers with identical in magnitude, but out of phase 180°. Consequently, the differential gain for each channel is 2 x (Gain of SE mode). By driving the load differentially through outputs OUT+ and OUT-, an amplifier configuration commonly re- ferred to as bridged mode is established. BTL mode operation is different from the classical single-ended SE amplifier configuration where one side of its load is connected to ground. A BTL amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive to the load, thus doubling the output swing for a specified supply voltage. Cbypass x 125kΩ≤ RiCi << RLCC (1)
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw The gain for each audio input of the APA2120/1 is set by the internal resistors (Ri and Rf) of volume control amplifier in inverting configuration. Ri vs Gain(BTL) 100 120 -40 -30 -20 -10 Gain(dB) Ri(kΩ) Application Descriptions (Cont.) Volume Control Function (Cont.) For highest accuracy, the voltage shown in the ‘rec- ommended voltage’ column of the table is used to select a desired gain. This recommended voltage is exactly halfway between the two nearest transitions. The gain levels are 2dB/step from 20dB to -40dB in BTL mode, and the last step at -80dB as mute mode. Input Resistance, Ri BTL mode operation brings the factor of 2 in the gain equation due to the inverting amplifier mirroring the voltage swing across the load. For the varying gain setting, APA2120/1 generates each input resistance on figure 4. The input resistance will affect the low frequency performance of audio signal. The minmum input resistance is 10kΩ when gain setting is 20dB and the resistance will ramp up when close loop gain below 20dB. The input resistance has wide variation (+/-10%) caused by process variation. Figure 4: Input resistance vs Gain setting RF Ri (3) BTL Gain = -2 x In the typical application an input capacitor, Ci, is re- quired to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri (10kΩ) form a high-pass filter with the corner frequency de- termined in the follow equation : Input Capacitor, Ci The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the example where Ri is 10kΩ and the speci- fication calls for a flat bass response down to 100Hz. Equation is reconfigured as follow : Consider to input resistance variation, the Ci is 0.16µF so one would likely choose a value in the range of 0.22µF to 1.0µF. FC(highpass)= 2πx10kΩxCi (4) Ci= 2πx10kΩxfC (5) SE Gain = RF Ri (2) AV = -
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw Input Capacitor, Ci (Cont.) A further consideration for this capacitor is the leak- age path from the input source through the input net- work (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the ampli- fier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tan- talum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at VDD/2, which is likely higher that the source DC level. sPlease note that it is important to confirm the ca- pacitor polarity in the application. Application Descriptions (Cont.) As other power amplifiers, proper supply bypassing is critical for low noise performance and high power supply rejection. Effective Bypass Capacitor, Cbypass The capacitors located on both the bypass and power supply pins should be as close to the device as possible. The effect of a larger bypass capacitor will improve PSRR due to increased supply stability. Typi- cal applications employ a 5V regulator with 1.0µF and a 0.1µF bypass capacitor as supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA2120/1. The selection of bypass capacitors, especially Cbypass, is thus dependent upon desired PSRR requirements, click and pop performance. On the chip, there are three bypass pins for used, and they are tied together in the internal circuit. To avoid start-up pop noise occurred, the bypass voltage should rise slower than the input bias voltage and the relationship shown in equation (6) should be maintained. The bypass capacitor is fed thru from a 125kΩ resis- tor inside the amplifier and the 100kΩ is maximum input resistance of (Ri+ Rf). Bypass capacitor, Cb, values of 3.3µF to 10µF ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance. Cbypass x 125kΩ<< 100kΩ x Ci (6) The bypass capacitance also effects to the start up time. It is determined in the following equation : Tstart up = 5 x (Cbypass x 125KΩ) (7) Effective Bypass Capacitor, Cbypass (Cont.) The effective capacitance is the Cbypass=(Cb// CLbyasss//CRbypass). When absolute minimum cost and/or component space is required, one by- pass capacitor can be used. In the typical single-supply SE configuration, an out- put coupling capacitor (Cc) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output coupling capacitor and imped- ance of the load form a high-pass filter governed by equation. Output Coupling Capacitor, Cc FC(highpass)= 2πRLCC (8)
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw Application Descriptions (Cont.) For example, a 330µF capacitor with an 8Ω speaker would attenuate low frequencies below 60.6Hz. The main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-frequency corner higher degrading the bass response. Large values of CC are required to pass low frequencies into the load. Output Coupling Capacitor, Cc (Cont.) Power Supply Decoupling, Cs The APA2120/1 provides PVDD and VDD two indepen- dent power inputs for used. PVDD is used for power amplifier only and VDD is used for volume control amplifier and internal circuit excepting power amplifier. The APA2120/1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic dis- tortion (THD) is as low as possible. Power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different type capacitors that target on dif- ferent type of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1µF placed as close as possible to the device VDD and PVDD lead works best. For filtering lower-frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near the audio power ampli- fier is recommended. Optimizing Depop Circuitry Circuitry has been included in the APA2120/1 to mini- mize the amount of popping noise at power-up and when coming out of shutdown mode. Popping oc- curs whenever a voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops. (Refer to Effective Bypass Capacitance) The bypass volt- age ramp up should be slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of Cbypass can be changed to al- ter the device turn-on time and the amount of clicks and pops. By increasing the value of Cbypass, turn- on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn- on time for this device. There is a linear relationship between the size of Cbypass and the turn-on time. In a SE configuration, the output coupling capacitor, CC, is of particular concern. This capacitor discharges through the internal 10kΩ resistors. Depending on the size of CC, the time con- stant can be relatively large. To reduce transients in SE mode, an external 1kΩ resistor can be placed in parallel with the internal 10kΩ resistor. The tradeoff for using this resistor is an increase in quiescent current. In the most cases, choosing a small value of Ci in the range of 0.33µF to 1µF, Cb being equal to 4.7µF and an external 1kΩ resistor should be placed in parallel with the internal 10kΩ resistor should pro- duce a virtually clickless and popless turn-on.
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw As APA2121, HP/LINE input multiplexor, and SE/BTL output operating mode have independent control paths, which can be used for multiple audio input system. This function will be the same as APA2120 when HP/LINE and SE/BTL are tied together. This logic-low voltage at the SE/BTL pin makes APA2120 into LINE input mode operation. It becomes HP input mode when phonejack plugged. Application Descriptions (Cont.) Optimizing Depop Circuitry (Cont.) A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. So it is advantageous to use low-gain configurations. Shutdown Function In order to reduce power consumption while not in use, the APA2120/1 contains a shutdown pin to ex- ternally turn off the amplifier bias circuitry. This shut- down feature turns the amplifier off when a logic low is placed on the SHUTDOWN pin. The trigger point between a logic high and logic low level is typically 2.0V. It is best to switch between ground and the sup- ply VDD to provide maximum device performance. By switching the SHUTDOWN pin to low, the ampli- fier enters a low-current state, IDD<50µA. APA2120/1 is in shutdown mode, except PC-BEEP detect circuit. On normal operating, SHUTDOWN pin pull to high level to keeping the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a definite volt- age to avoid unwanted state changes. Input HP/LINE Operation (Cont.) An internal multiplexor selects the input to connect to the amplifier based on the state of the HP/LINE pin of the APA2121.
- To select the LINE inputs, set HP/LINE pin to low level.
- To enable the HP(headphone) inputs, set HP/LINE pin to high level. Input HP/LINE Operation APA2120/1 amplifier has two separate inputs for each of the left and right stereo channels. The APA2120 and APA2121 have different control input by SE/BTL and HP/LINE, respectively. APA2120 internal multiplexor is selected by SE/BTL control input. Refer to the ‘Output SE/BTL Operation’, the voltage divider of 100kΩ and 1kΩ sets the volt- age at the SE/BTL pin to be approximately 50mV when no phonejack plugged into the system. PC-BEEP Detection APA2120/1 integrates a BEEP detect circuit for NOTEBOOK PC. When BEEP signal is provided on PCBEEP input pin, the BEEP mode is active. APA2120/1 will force to BTL mode and the internal gain is fixed at -10dB. The PCBEEP signal becomes the amplifier input signal and plays on the speaker without coupling capacitor. It will be out of shutdown mode whenever BEEP mode is enabled. APA2120/ 1 will return to previous setting when it is out of BEEP mode. The input impedance is 100kΩ on PCBEEP input pin. APA2120 provides extra PCBEN control input signal to force IC into BEEP mode. The BEEP mode will be enabled when PCBEN goes to high level. When BEEP mode is overridden, the signal from PCBEEP will pass to speaker directly.
Copyright ANPEC Electronics Corp. supply to the power delivered to the load. quency if no capacitor place on CLK pin to ground. and will generates 147Hz frequency on CLK pin. power dissipation over the normal operating range. on the power supply is almost 3W. speaker impedance for the application. **High peak voltages cause the THD to increase. Table 1. Efficiency Vs Output Power in 5-V/8Ω BTL
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw Application Descriptions (Cont.) Power Dissipation Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. In equation13 states the maximum power dissipation point for a SE mode operating at a given supply volt- age and driving a specified load. SE mode : PD,MAX= (13) VDD 2π RL In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus the maximum power dissipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. Since the APA2120/1 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both of equations depending on the mode of operation. Even with this substantial increase in power dissipation, the APA2120/1 does not require extra heatsink. The power dissipation from equation14, assuming a 5V-power supply and an 8Ω load, must not be greater than the power dissipation that results from the equation15 : BTL mode : PD,MAX= (14) 4VDD 2π RL Power Dissipation (Cont.) For TSSOP-24 package with thermal pad, the ther- mal resistance (θJA) is equal to 45οC/W. Since the maximum junction temperature (TJ,MAX) of APA2120/1 is 150οC and the ambient temperature (TA) is defined by the power system design, the maxi- mum power dissipation which the IC package is able to handle can be obtained from equation16. TJ,MAX - TA θJA PD,MAX= (15) Once the power dissipation is greater than the maxi- mum limit (PD,MAX), either the supply voltage (VDD) must be decreased, the load impedance (RL) must be in- creased or the ambient temperature should be reduced. The thermal pad must be connected to ground. The package with thermal pad of the APA2120/1 requires special attention on thermal design. If the thermal design issues are not properly addressed, the APA2120/1 4Ω will go into thermal shutdown when driving a 4Ω load. Thermal Pad Considerations For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to conduct heat away from the thermal pad should be as large as practical. If the ambient temperature is higher than 25°C, a larger copper plane or forced-air cooling will be re- quired to keep the APA2120/1 junction temperature below the thermal shutdown temperature (150°C). In higher ambient temperature, higher airflow rate and/ or larger copper area will be required to keep the IC out of thermal shutdown. The thermal pad on the bottom of the APA2120/1 should be soldered down to a copper pad on the cir- cuit board. Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on the top surface of the cir- cuit board, 8 to 10 vias of 13 mil or smaller in diam- eter should be used to thermally couple the thermal pad to the bottom plane.
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw TSSOP/ TSSOP-P ( Reference JEDEC Registration MO-153) M illimeters Inches Dim Min. Max. Min. Max. A 1.2 0.047 0.00 0.15 0.000 0.006 0.80 1.05 0.031 0.041 D 6.4 (N=20PIN) 7.7 (N=24PIN) 9.6 (N=28PIN) 6.6 (N=20PIN) 7.9 (N=24PIN) 9.8 (N=28PIN) 0.252 (N=20PIN) 0.303 (N=24PIN) 0.378 (N=28PIN) 0.260 (N=20PIN) 0.311 (N=24PIN) 0.386 (N=28PIN)
4.2 BSC (N=20PIN)
4.7 BSC (N=24PIN)
3.8 BSC (N=28PIN)
0.165 BSC (N=20PIN)
0.188 BSC (N=24PIN)
0.150 BSC (N=28PIN)
e
0.65 BSC
0.026 BSC
E
6.40 BSC
0.252 BSC
4.30 4.50 0.169 0.177
3.0 BSC (N=20PIN)
3.2 BSC (N=24PIN)
2.8 BSC (N=28PIN)
0.118 BSC (N=20PIN)
0.127 BSC (N=24PIN)
0.110 BSC (N=28PIN)
L 0.45 0.75 0.018 0.030
1.0 REF
0.039REF R 0.09 0.004 0.09 0.004 S 0.2 0.008 12° REF 12° REF 12° REF 12° REF BOTTOM VIEW (THERMALLY ENHANCED VARIATIONDS ONLY) b A D e 2 x E / 2 E e/2 N EXPOSED THERMAL PAD ZONE L (L1) S 0.25 GAUGE PLANE Packaging Information
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw Reference JEDEC Standard J-STD-020A APRIL 1999 Reflow Condition (IR/Convection or VPR Reflow) Physical Specifications Pre-heat temperature 183 C Peak temperature Time temperature Classification Reflow Profiles Convection or IR/ Convection VPR Average ramp-up rate(183°C to Peak) 3°C/second max. 10 °C /second max. Preheat temperature 125 ± 25°C) 120 seconds max Temperature maintained above 183°C 60 – 150 seconds Time within 5°C of actual peak temperature 10 –20 seconds 60 seconds Peak temperature range 215-219°C or 235 +5/-0°C Ramp-down rate 6 °C /second max. 10 °C /second max. Time 25°C to peak temperature 6 minutes max. Package Reflow Conditions pkg. thickness ≥≥≥≥ 2.5mm and all bgas pkg. thickness < 2.5mm and pkg. volume ≥≥≥≥ 350 mm³ pkg. thickness < 2.5mm and pkg. volume < 350mm³ Convection 220 +5/-0 °C Convection 235 +5/-0 °C VPR 215-219 °C VPR 235 +5/-0 °C IR/Convection 220 +5/-0 °C IR/Convection 235 +5/-0 °C Terminal Material Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb) Lead Solderability Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw Reliability test program Test item Method 245°C , 5 SEC HOLT MIL-STD-883D-1005.7
1000 Hrs Bias @ 125 °C
JESD-22-B, A102
168 Hrs, 100 % RH , 121°C
MIL-STD-883D-1011.9 -65°C ~ 150°C, 200 Cycles ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V Latch-Up JESD 78 10ms , Itr > 100mA Carrier Tape & Reel Dimensions A J B C t Ao E W Po P Ko Bo D F Application A B C J W P E 330 ±1 100 ref 13 ±0.5 2 ±0.5 16.4 ±0.2 2 ±0.2 16 ±0.3 12 ±0.1 1.75±0.1 F D Po Ao Bo Ko t TSSOP- 24 7.5 ±0.1 1.5 +0.1 1.5 min 4.0 ±0.1 2.0 ±0.1 6.9 ±0.1 8.3 ±0.1 1.5 ±0.1 0.3±0.05
Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2003 APA2120/2121 www.anpec.com.tw Application Carrier Width Cover Tape Width Devices Per Reel TSSOP- 24 21.3 2000 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Cover Tape Dimensions