APA2070JI-TUL

APA2070 ANPEC | Alldatasheet

Document overview

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Technical content

Features

• Low Operating Current about 9mA (typical)
• Improved Depop Circuitry to Eliminate Turn-on and Turn-off Transients in Outputs
• 32-Step Volume Adjustable by DC Voltage with Hysteresis
• Output Power at 1% THD+N - 2.4W, at VDD=5V, BTLMode, RL=3W - 2W, at VDD=5V, BTLMode, RL=4W at 10% THD+N - 3.1W, at VDD=5V, BTLMode, RL=3W - 2.6W, at VDD=5V, BTLMode, RL=4W
• Two Output Modes: BTL and SE Modes Selected by SE/BTL Pin
• Low Current Consumption in Shutdown Mode (1mA, typical)
• Short Circuit Protection
• Thermal Shutdown Protection and Over-Current Protection Circuitry
• The OUTP Signal and the INN Signal are Outphase
• Power Enhanced Package (DIP-16/DIP-16A)
• Lead Free and Green Devices Available (RoHS Compliant) Applications General Description The APA2070 is a monolithic integrated circuit, which provides precise DC volume control, and a stereo bridged audio power amplifiers capable of producing 2.6W (2W) into 4Ω with less than 10% (1.0%) THD+N. The attenuator range of the volume control in APA2070 is from 18dB (VVOLUME=0V) to -80dB (VVOLUME=3.54V) with 32 steps. The advantage of internal gain setting can be less components and PCB area. Both the depop circuitry and the thermal shutdown protection circuitry are integrated in the APA2070, that reduce pops and clicks noise dur- ing power up or shutdown mode operation. It also im- proves the power off pop noise and protects the chip be- ing destroyed by over temperature and short current failure. To simplify the audio system design, the APA2070 combines a stereo bridge-tied load (BTL) mode for speaker drive and a stereo single-end (SE) mode for head- phone drive into a single chip, where both modes are easily switched by the SE/BTL input control pin signal.
• Notebook PC
• LCD Monitor or TVSimplified Application Circuit R-CH Input L-CH Input LOUTP LOUTN LINN VOLUME APA2070 ROUTP RINN ROUTN Stereo Headphone Stereo Speaker DC Volume Control

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw2 Symbol Parameter Rating Unit VDD Supply Voltage (VDD to GND) -0.3 to 6 V Input Voltage (SE/BTL, SHUTDOWN, VOLUME, RINN, LINN to GND) -0.3 to VDD+ 0.3 V Output Voltage (LOUTN, LOUTP, ROUTP, ROUTN to GND) -0.3 to VDD+ 0.3 V TA Operating Ambient Temperature Range -40 to 85 ο C TJ Maximum Junction Temperature 150 ο C TSTG Storage Temperature Range -65 to +150 ο C TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 ο C PD Power Dissipation Internally Limited W Pin Configuration Ordering and Marking Information Absolute Maximum Ratings (Note 1) Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). APA2070 Handling Code Temperature Range Package Code APA2070 J : APA2070 XXXXX XXXXX - Date Code Assembly Material Package Code J : DIP-16 / DIP-16A Operating Ambient Temperature Range I : - 40 to 85 oC Handling Code TU : Tube Assembly Material L : Lead Free Device G : Halogen and Lead Free Device GND 5 GND 4 13 GND SE/BTL 8

15 VDD

12 GND

16 ROUTN

11 LOUTP

10 VDDVOLUME 7

9 LOUTN

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw3 Symbol Parameter Typical Value Unit θ JA Junction-to-Ambient Resistance in Free Air (Note 2) 45 oC/W θ JC Junction-to-Case Resistance in Free Air (Note 3) 8 oC/W Symbol Parameter Range Unit VDD Supply Voltage 4.5 ~ 5.5 SHUTDOWN 0.4VDD ~ VDD VIH High Level Threshold Voltage SE/BTL 0.8VDD ~ VDD SHUTDOWN 0 ~ 1.0 VIL Low Level Threshold Voltage SE/BTL 0 ~ 1.0 VCIM Common Mode Input Voltage ~ V DD-1.0 V TA Ambient Temperature Range -40 ~ 80 TJ Junction Temperature Range -40 ~ 125 ο C RL Speaker Resistance 3 ~ RL Headphone Resistance 16 ~ Ω Recommended Operating Conditions (Note 4)

Electrical Characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit VSE/BTL =0V - 9 20 IDD Supply Current VSE/BTL=5V - 4 10 mA ISD Shutdown Current VSE/BTL=0V VSHUTDOWN =0V - 1 - µA TSTART-UP Start-Up Time from Shutdown CBYPASS=2.2µF - 1.6 - s BTL MODE. VDD=5V, GAIN=6dB (UNLESS OTHERWISE NOTED) THD+N=10%, RL=3Ω, fin=1kHz - 3.1 - THD+N =10%, RL=4Ω , fin=1kHz - 2.6 - THD+N =10%, RL=8Ω , fin=1kHz - 1.6 - THD+N =1%, RL=3Ω , fin=1kHz - 2.4 - THD+N =1%, RL=4Ω , fin=1kHz - 2 - PO Output Power THD+N =0.5%, RL=8Ω , fin=1kHz 1 1.3 - W PO=1.2W, RL=4Ω , fin=1kHz - 0.07 - THD+N Total Harmonic Distortion Pulse Noise PO=0.9W, RL=8Ω , fin=1kHz - 0.08 - Unless otherwise specified, these specifications apply over V DD=5V, VGND=0V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Note 4 : Refer to the typical application circuit Thermal Characteristics Note 2: θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. Note 3: The case temperature is measured at the center of the GND pin on the beside of the DIP-16/DIP-16A package.

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw4 Electrical Characteristics (Cont.) APA2070 Symbol Parameter Test Conditions Min. Typ. Max. Unit BTL MODE. VDD=5V, GAIN=6dB (UNLESS OTHERWISE NOTED) (CONT.) PSRR Power Supply Rejection Ratio VDD Ripple=0.1Vrms, RL=8Ω , CBYPASS=2.2µF, fin=217Hz - 60 - dB Crosstalk Channel Separation CBYPASS=2.2µF, RL=8Ω , fin=1kHz - 90 - dB VOS Output Offset Voltage RL=4Ω - 5 - mV S/N Signal to Noise Ratio PO=1.1W, RL=8Ω , A_Weighting - 95 - dB SE MODE. VDD=5V, GAIN=0dB THD+N=10%, RL=16Ω, fin=1kHz - 220 - THD+N =10%, RL=32Ω , fin=1kHz - 120 - THD+N =1%, RL=16Ω , fin=1kHz - 160 - Po Output Power THD+N =1%, RL=32Ω , fin=1kHz - 95 - mW PO=125mW, RL=16Ω , fin=1kHz - 0.09 - THD+N Total Harmonic Distortion Pulse Noise PO=65mW, RL=32Ω , fin=1kHz - 0.09 - % PSRR Power Supply Rejection Ratio VDD Ripple =0.1Vrms, RL=32Ω , CBYPASS =2.2µF, fin=217Hz - 60 - dB Crosstalk Channel Separation CBYPASS=2.2µF, RL=32Ω , fin=1kHz - 60 - dB VOS Output Offset Voltage RL=32Ω - 5 - mV S/N Signal to Noise Ratio PO=75mW, RL=32Ω , A_Weighting - 100 - dB Unless otherwise specified, these specifications apply over V DD=5V, VGND=0V and TA= -40 ~ 85 oC. Typical values are at TA=25oC.

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw5 Typical Operating Characteristics THD+N vs. Output Power THD+N vs. Output Power THD+N (%) Output Power (W) Output Power (W) THD+N (%) THD+N vs. Output Power THD+N vs. Output Power THD+N (%) Output Power (W) Output Power (W) THD+N (%) THD+N vs. Frequency THD+N vs. Frequency THD+N (%) THD+N (%) Frequency (Hz) Frequency (Hz) 0.01 0.1 0 3.50.5 1 1.5 2 2.5 3 VDD = 5V AV =18dB fin = 1kHz BTL Mode RL = 8Ω RL = 4Ω RL = 3Ω 0.01 0.1 0 240m40m 80m 120m 160m 200m VDD = 5V AV =12dB fin = 1kHz SE Mode RL = 32Ω RL = 16Ω 0.01 0.1 0 3.50.5 1 1.5 2 2.5 3 AV = 18dB AV = 6dB VDD = 5V fin =1kHz RL =3Ω BTL Mode 0.05 0.1 10m 5100m 1 fin = 20kHz fin= 20Hz fin= 1kHz VDD = 5V AV =18dB RL =3Ω BTL Mode 0.01 0.1 20 20k100 1k 10k VDD = 5V RL =3Ω PO = 1.8W BTL Mode AV = 18dB AV = 6dB 0.01 0.1 20 20k100 1k 10k PO = 0.9W PO = 1.8W VDD = 5V AV = 6dB RL =3Ω BTL Mode

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw6 Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power Output Power (W) Output Power (W) THD+N (%) THD+N (%) THD+N vs. Frequency THD+N vs. Frequency THD+N (%) THD+N (%) Frequency (Hz) Frequency (Hz) THD+N vs. Output Power THD+N vs. Output Power Output Power (W) Output Power (W) THD+N (%) THD+N (%) 0.01 0.1 10m 5100m 1 fin= 20kHz fin = 20Hz fin = 1kHz VDD = 5V AV =18dB RL =4Ω BTL Mode 0.01 0.1 20 20k100 1k 10k VDD = 5V RL=4Ω PO=1.5W BTL Mode AV = 18dB AV = 6dB 0.01 0.1 20 20k100 1k 10k VDD = 5V AV= 6dB RL=4Ω BTL Mode PO = 0.8W PO = 1.5W 0.01 0.1 0 3.50.5 1 1.5 2 2.5 3 AV = 18dB AV = 6dB VDD = 5V fin= 1kHz RL=8Ω BTL Mode 0.01 0.1 10m 5100m 1 fin = 20kHz fin = 20Hz fin = 1kHz VDD = 5V AV = 18dB RL=8Ω BTL Mode 0.01 0.1 0 3.50.5 1 1.5 2 2.5 3 AV = 18dB AV = 6dB VDD = 5V f =1kHz RL =4Ω BTL Mode

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw7 Typical Operating Characteristics (Cont.) THD+N (%) THD+N (%) THD+N vs. Frequency THD+N vs. Frequency THD+N (%) THD+N (%) Frequency (Hz) Frequency (Hz) THD+N vs. Output Power THD+N vs. Output Power Output Power (W) Output Power (W) THD+N (%) THD+N (%) THD+N vs. Frequency THD+N vs. Frequency Frequency (Hz) Frequency (Hz) 0.01 0.1 20 20k100 1k 10k PO = 0.5W VDD = 5V AV = 6dB RL=8Ω BTL Mode PO = 0.9W 0.01 0.1 20 20k100 1k 10k AV = 6dB AV = 18dB VDD=5V RL=8Ω PO=0.9W BTL Mode 0.01 0.1 0 240m40m 80m 120m 160m 200m VDD=5V fin=1kHz RL=16Ω SE Mode AV = 0dB AV = 12dB 0.01 0.1 10m 300m50m 100m 200m VDD=5V AV=12dB RL=16Ω CO=1000µF SE Mode fin = 20kHz fin = 1kHz fin = 20Hz 0.01 0.1 20 20k100 1k 10k VDD=5V RL=16Ω PO=125mW CO=1000µF SE Mode AV = 0dB AV = 12dB 0.01 0.1 20 20k100 1k 10k VDD=5V AV=0dB RL=16Ω CO=1000µF SE Mode PO = 125mW PO = 60mW

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw8 Typical Operating Characteristics (Cont.) THD+N (%) THD+N (%) Frequency Response Frequency Response THD+N (%) THD+N (%) Frequency (Hz) Frequency (Hz) THD+N vs. Output Power THD+N vs. Output Power Output Power (W) Output Power (W) Amplitude(dB) Amplitude(dB) THD+N vs. Frequency Frequency (Hz) THD+N vs. Frequency Frequency (Hz) Phase (Degrees) Phase (Degrees) 0.01 0.1 0 240m40m 80m 120m 160m 200m VDD=5V fin=1kHz RL=32Ω SE Mode AV = 0dB AV = 12dB 0.01 0.1 10m 300m50m 100m 200m VDD=5V AV=12dB RL=32Ω CO=1000µF SE Mode fin = 20Hz fin = 1kHz fin = 20kHz 0.01 0.1 20 20k100 1k 10k AV = 0dB AV = 14dB VDD=5V RL=32Ω PO=65mW CO=1000µF SE Mode 0.01 0.1 20 20k100 1k 10k PO = 65mW PO = 30mW VDD=5V AV=12dB RL=32Ω CO=1000µF SE Mode +60 +260 +100 +140 +180 +220 +20 +12 +16 10 200k100 1k 10k Phase( 6dB) Amplitude( 6dB) Amplitude( 14dB) Phase( 14dB) VDD=5V RL=4Ω PO=0.8W BTL Mode +60 +260 +100 +140 +180 +220 +20 +12 +16 10 200k100 1k 10k Amplitude( 6dB) Amplitude( 14dB) Phase( 14dB) Phase( 6dB) VDD=5V RL=8Ω PO=0.5W BTL Mode

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw9 Typical Operating Characteristics (Cont.) Crosstalk vs. Response Crosstalk vs. Response Frequency (Hz) Frequency (Hz) Crosstalk(dB) Crosstalk(dB) Crosstalk vs. Frequency Frequency (Hz) Crosstalk vs. Frequency Frequency (Hz) Frequency Response Frequency Response Frequency (Hz) Frequency (Hz) Amplitude(dB) Amplitude(dB) Crosstalk(dB) Crosstalk(dB) Phase (Degrees) Phase (Degrees) +60 +260 +100 +140 +180 +220 10 200k100 1k 10k Amplitude(0dB) Phase(0dB) Amplitude(12dB) Phase(12dB) +14 +10 VDD=5V RL=16Ω CO=1000µF PO=60mW SE Mode +60 +260 +100 +140 +180 +220 10 200k100 1k 10k Amplitude(12dB) Amplitude(0dB) Phase(12dB) Phase(0dB) +14 +10 VDD=5V RL=32Ω CO=1000µF PO=30mW SE Mode -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD=5V RL=8Ω PO=0.9W BTL Mode Right to Left Left to Right -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k Right to Left Left to Right VDD=5V RL=4Ω PO=1.5W BTL Mode -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k Right to Left Left to Right VDD=5V RL=16Ω CO=1000µF PO=125mW SE Mode -100 -80 -60 -40 -20 20 20k100 1k 10k -10 -30 -50 -70 -90 VDD=5V RL=32Ω CO=1000µF PO=65mW SE Mode Right to Left Left to Right

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw10 Typical Operating Characteristics (Cont.) Mute Attenuation vs. Frequency Shutdown Attenuation vs. Frequency Frequency (Hz) Frequency (Hz) Shutdown Attenuation(dB) Mute Attenuation(dB) PSRR vs. Frequency Frequency (Hz) PSRR vs. Frequency Frequency (Hz) Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency Frequency (Hz) Frequency (Hz) Output Noise Voltage(dB) Output Noise Voltage(dB) PSRR(dB) PSRR(dB) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD=5V RL=4Ω VIN=200mV AV=18dB BTL Mode -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD=5V RL=32Ω VIN=200mV AV=12dB SE Mode 100µ 10µ 20µ 20 20k100 1k 10k VDD=5V AV=6dB RL=4Ω BTL Mode A-weighting Filter BW<22kHz 100µ 10µ 20µ 20 20k100 1k 10k Filter BW<22kHz A-weighting VDD=5V AV=0dB RL=32Ω SE Mode -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD=5V RL=8Ω VIN=1Vrms AV=6dB BTL Mode -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD=5V RL=8Ω VIN=1Vrms AV=6dB BTL Mode

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw11 Typical Operating Characteristics (Cont.) Power Dissipation vs.Output Power Power Dissipation vs. Output Power Gain vs. Volume Voltage Supply Current vs. Supply Voltage DC Voltage (V) Supply Voltage(V) Supply Current (mA) Gain(dB) Power Dissipation(W) Power Dissipation(W) 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 BTL SE No Load Output Power (W) Output Power(mW) -80 -70 -60 -50 -40 -30 -20 -10 Up Down VDD=5V No Load BTL Mode 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 RL=3Ω RL=4Ω RL=8Ω VDD=5V BTL Mode 100 120 140 160 180 200 0 50 100 150 200 250 RL=8Ω RL=32Ω RL=16Ω VDD=5V SE Mode 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Output Power (W) Output Power vs. Supply Voltage RL=8Ω ,THD+N=1% RL=8Ω ,THD+N=10% RL=4Ω ,THD+N=1% RL=4Ω ,THD+N=10% RL=3Ω ,THD+N=1% RL=3Ω ,THD+N=10% Supply Voltage (V) BTL Mode AV=6dB

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw12 Pin Description PIN NO. NAME FUNCTION SHUTDOWN Shutdown control pin. Pulling low the voltage on this pin shuts off the IC. In shutdown mode, the IC only draws 1µA (typical) of supply current. 2 BYPASS Bypass capacitor connection pin for the bias voltage generator.

3 RINNN Right channel input terminal

4,5,12,13 GND Ground connection. Connect all of the GND pins to ground plane.

6 LINN Left channel input terminal

7 VOLUME DC voltage input pin for internal volume gain setting (DC Volume control). SE/BTL Output mode control input, high for SE output mode and low for BTL mode. 9 LOUTN Left channel negative output in BTL mode and high impedance in SE mode. 10,15 VDD Supply voltage input pin. Connect all of the VDD pins to supply voltage. 11 LOUTP Left channel positive output in BTL mode and SE mode. 14 ROUTP Right channel positive output in BTL mode and SE mode. 16 ROUTN Right channel negative output in BTL mode and high impedance in SE mode. Block Diagram Power and Depop circuit LOUTP LOUTN LINN SE/BTL SHUTDOWN BYPASS DC Volume Control VOLUME ROUTP RINN Bias Voltage Generator ROUTN GND VDD Shutdown SE/BTL Mode Selection circuit

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw13 Typical Application Circuit Ring Headphone Jack Sleeve Control Pin Tip SE/BTL Signal1 220µF 220 1kΩ R-CH Input VDD 100k Shutdown Signal L-CH Input VDD VDD GND 1000.1 100kΩ Shutdown LOUTP LOUTN LINN SE/BTL SHUTDOWN BYPASS Volume Control VOLUME ROUTP RINN ROUTN VDD 50kΩ 2.2 µF µF µF µF Ω Ω Ω µFµF Bias Voltage Generator SE/BTL Mode Selection circuit DC CCL CCR CiL CiR CS CBYPASS 1kΩ

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw14 DC Volume Control Table_BTL Mode Voltage Range (% of V DD ) Voltage Range (V DD =5V) Gain(dB) High(%) Low(%) Recommended (%) High(V) Low(V) Recommended (V)

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw16 SE/BTL Mode Selection Function (Cont.) The APA2070 has an internal stereo volume control that setting is the function of the DC voltage applied to the VOLUME input pin. The APA2070 volume control consists of 32 steps that are individually selected by a variable DC voltage level on the VOLUME control pin. The range of the steps, controlled by the DC voltage, are from 18dB to -80dB. Each gain step corresponds to a specific input voltage range, as shown in table. To minimize the effect of noise on the volume control pin, which can affect the se- lected gain level, hysteresis and clock delay are implemented. The amount of hysteresis corresponds to half of the step width, as shown in the volume control graph. DC Volume Control Function For the highest accuracy, the voltage shown in the ‘rec- ommended voltage’ column of the table is used to select a desired gain. This recommended voltage is exactly half- way between the two nearest transitions. The gain levels are 32 steps from 18dB to -40dB in BTL mode, and the last step at -80dB as mute mode. Function Description (Cont.) By switching the SHUTDOWN pin to low, the amplifier enters a low-current state, IDD<1µA. APA2070 is in shut- down mode. On normal operation, SHUTDOWN pin is pulled to high level to keep the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a defi- nite voltage to avoid unwanted state changing. In order to reduce power consumption while not in use, the APA2070 contains a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the SHUTDOWN pin. The trigger point between a logic high and logic low level is typically 2.0V. It would be better to switch between the ground and the supply VDD to provide maximum device performance. Shutdown Function DC Volume (V) Gain (dB) -80 -70 -60 -50 -40 -30 -20 -10 Backward Forward APA2070 DC Volume Control Curve (BTL) Figure 3: Gain setting vs. VOLUME pin voltage Thermal Protection The thermal protection circuit limits the junction tempera- ture of the APA2070. When the junction temperature ex- ceeds T J = +150 oC, a thermal sensor turns off the amplifier, allowing the devices to cool. The thermal sen- sor allows the amplifier to start-up after the junction tem- perature down about 125 oC. The thermal protection is designed with a 25 oC hysteresis to lower the average T J during continuous thermal overload conditions, which is increasing lifetime of the IC. Over-Current Protection In Figure 2, input SE/BTL operates as below: When the phonejack plug is inserted, the 1kΩ resistor is disconnected and the SE/BTL input is pulled high to en- able the SE mode. Meanwhile, the OUTN amplifier is shut down which turns the speaker to be mute. The OUTP amplifier then drives through the output capacitor into the headphone jack. When there is no headphone plugged into the system, the contact pin of the headphone jack is connected from the signal pin, and the voltage divider is set up by resistors 100kΩ and 1kΩ . Resistor 1kΩ then is pulled low the SE/BTL pin, enabling the BTL function. The APA2070 monitors the output current. When the cur- rent exceeds the current-limit threshold, the APA2070 turns off the output to prevent the IC from damages in over- current or short-circuit condition. When the over-current occurs in power amplifier, the output buffer’s current will be foldbacked to a low setting level, and it will release when over-current situation is no long existence. On the contrary, if the over-current period is long enough and the IC’s junction temperature reaches the thermal protection threshold, the IC will enter thermal protection mode.

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw17

Application Information

(3) (2) Input Resistance (Ri) The gain for each audio input of the APA2070 is set by the internal resistors (Ri and RF) of volume control amplifier in inverting configuration. BTL mode operation brings the factor of 2 in the gain equation due to the inverting amplifier mirroring the volt- age swing across the load. For varying gain settings, the APA2070 generates each input resistance on figure 4. The input resistance will affect the low frequency perfor- mance of audio signal. The minmum input resistance is 30kΩ when gain setting is 18dB and the resistance will ramp up when close loop gain below 18dB. The input resistance has wide variation (+/-10%) caused by pro- cess variation. 100 120 140 160 -40 -30 -20 -10 0 10 20 Gain(BTL) Ri(KΩ ) Ri vs. Gain(BTL) Figure 4: Input resistance vs. Gain setting (4) (5) Input Capacitor (Ci) In the typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri (30kΩ ) form a high-pass filter with the corner frequency determined in the follow- ing equation : The value of Ci must be considered carefully because it directly affects the low frequency performance of the circuit. Consider the example where Ri is 30kΩ and the specifi- cation calls for a flat bass response down to 50Hz. Equa- tion is reconfigured below : When varitation of input resistance (Ri) is considered, the Ci should is 0.1µF, so a value in the range of 0.047µF to 0.47µF would be chosen. A further consideration for this capacitor is the leakage path from the input source through the input network (Ri+RF, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tanta- lum or ceramic capacitor is the best choice. When polar- ized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at VDD/2. Please note that it is important to confirm the capacitor polarity in the application. Effective Bypass Capacitor (CBYPASS) A power amplifier, proper supply bypassing, is critical for low noise performance and high power supply rejection. The capacitor location on the BYPASS pin should be as close to the device as possible. The effect of a larger supply bypass capacitor is to improve PSRR due to increased half-supply stability. Two critical criteria of bypass capacitor (CBYPASS): 1st, it depends upon de- sired PSRR requirements and click -and-pop performance; 2nd, the leakage current of CBYPASS will induce the voltage drop of VBYPASS (voltage of BYPASS pin), and if the VBYPASS is less than 0.49VDD, the APA2070 will enter mute condition. The value of VBYPASS can be calculated as below: (6) Where ILeakage =Leakage current of C BYPASS Therefore, it is recommended that CBYPASS ’s leakage cur- rent should be no more than 0.4 µA for properly work of the APA2070. i F V R RA Gain SE −== i F R R-2Gain BTL ×= CFk302 iC ×Ω×π Ω×= 150k I-0.5VV LeakageDDBYPASS i )highpass(C Ck302 1F ×Ω×π=

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw18 Application Information (Cont.) (7) To avoid the start-up pop noise, the bypass voltage should rise slower than the input bias voltage and the relation- ship shown in equation should be maintained. The capacitor is fed from a 150k Ω resistor inside of the am plifier and the 150kΩ is the maximum input resi s- tance of (R i+RF). Bypass cap acitor, C BYPASS, values of 2.2µF to 10µF ceramic or tantalum low-ESR cap acitors are recommended for the best TH D+N and noise performance. The bypass capacitance also affects the start-up time. It is determined in the following equation: (8) (9) Output Coupling Capacitor (CC) In the typical single-supply SE configuration, an output coupling capacitor (CC) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high- pass filter governed by the equation. For example, a 330µF capacitor with an 8Ω speaker would attenuate low frequencies below 60.6Hz. The main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-fre- quency corner higher degrading the bass response. Large values of CC are required to pass low frequencies into the load. Effective Bypass Capacitor (CBYPASS) (Cont.) Power Supply Decoupling Capacitor (CS) The APA2070 is a high-performance CMOS audio ampli- fier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) is as low as possible. Power supply decoupling also pre- vents the oscillations caused by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different types of capacitors that target on different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1µF, is placed as close as possible to the device VDD lead works best. For filtering lower-frequency noise signals, it is recommended to place a large aluminum electrolytic capacitor of 10µF or greater near the audio power amplifier Optimizing Depop Circuitry Circuitry has been included in the APA2070 to minimize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a volt- age step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops (Refer to Effective Bypass Capacitance). The bypass voltage ramp up should be slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of CBYPASS can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of CBYPASS, turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relation- ship between the size of CBYPASS and the turn-on time. In a SE configuration, the output coupling capacitor (CC), is of particular concern. This capacitor discharges through the internal 10kΩ resistors. Depending on the size of CC, the time constant can be relatively large. To reduce transients in SE mode, an external 1kΩ resistor can be placed in parallel with the internal 10kΩ resistor. The tradeoff for using this resistor is an increase in quiescent current. In most cases, choos- ing a small value of Ci in the range of 0.33µF to 1µF, CBYPASS being equal to 4.7µF and an external 1kΩ resistor should be placed in parallel with the internal 10kΩ resis- tor should produce a virtually clickless and popless turn- on. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain, so it is advanta- geous to use low-gain configurations. Ω<<Ω X150kC )X150k C ( iBYPASS )X150k5X(C T BYPASSup start Ω= CL )highpass(C CR2 1F π=

Copyright  ANPEC Electronics Corp. ply to the power delivered to the load. the maximum draw on the power supply is almost 3W. supply voltage and speaker impedance for the application. **High peak voltages cause the THD+N to increase. Table 1. Efficiency vs. Output Power in 5-V/8Ω BTL Sys- conditions is 4 times as in SE mode.

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw20 Application Information (Cont.) Power Dissipation (Cont.) Once the power dissipation is greater than the maximum limit (PD,MAX), either the supply voltage (VDD) must be decreased, the load impedance (RL) must be increased or the ambient temperature should be reduced. Thermal Consideration Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. The first consideration to calculate maximum ambient temperatures is the numbers from the Power Dissipa- tion vs. Output Power graphs are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given θ JA, the maximum allow- able junction temperature (TJMAX), and the total internal dissipation (PD), the maximum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the APA2070 is 150°C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graphs. TAMax = TJMax -θ JAPD (16) The APA2070 is designed with a thermal shutdown pro- tection that turns the device off when the junction tem- perature surpasses 150°C to prevent damaging the IC. Layout Consideration Figure 5: APA 2070 Land Pattern Recommendation 1. All components should be placed close to the APA2070. For example, the input capacitor (Ci) should be close to APA2070’s input pins to avoid causing noise cou- pling to APA2070’s high impedance inputs; the decoupling capacitor (CS) should be placed by the APA2070’s power pin to decouple the power rail noise. 2. The output traces should be short, wide (>50mil), and symmetric. 3. The input trace should be short and symmetric. 4. The power trace width should be greater than 50mil. 5. The APA2070’s GND pin should be soldered on the ground plane of the PCB. 16mm 20mm3mm 4mm Ground plane for GND pin Via diameter =0.3mm x 24

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw21

Package Information

Note : 1. Followed from JEDEC MS-001AB 2. Dimension D, D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 10 mil. S YMB O L MIN. MAX. 5.33 0.38 0.36 0.56 1.14 1.78 0.20 0.35 18.6 20.31 0.13 2.92 3.81 A b c D E e eA MILLIMETERS A2 2.92 4.95

2.54 BSC

7.62 8.26 6.10 7.11 eB L 10.92

7.62 BSC

MIN. MAX. INCHES 0.210 0.015

0.100 BSC

0.300 BSC

0.115 0.195 0.014 0.022 0.045 0.070 0.008 0.014 0.732 0.800 0.005 0.300 0.325 0.240 0.280 0.430 0.115 0.150 D 0.38 c eA eB E A2A1 AL b b2 eD1

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw22 A L eB eAc E 0.38 SYMBOL MIN. MAX. 5.33 0.38 0.36 0.56 1.14 1.78 0.20 0.35 18.6 20.31 0.13 2.92 3.81 A b c D E e eA MILLIMETERS A2 2.92 4.95 7.62 8.26 6.10 7.11 eB L 10.92 MIN. MAX. INCHES 0.210 0.015 0.115 0.195 0.014 0.022 0.045 0.070 0.008 0.014 0.732 0.800 0.005 0.300 0.325 0.240 0.280 0.430 0.115 0.150 Note : 1. Followed from JEDEC MS-001AB 2. Dimension D, D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 10 mil. D

Copyright  ANPEC Electronics Corp. Rev. A.4 - Oct., 2010 APA2070 www.anpec.com.tw23 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds Average ramp-up rate (Tsmax to TP) 3 °C/second max. 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 183 °C 60-150 seconds 217 °C 60-150 seconds Peak package body Temperature (Tp)* See Classification Temp in table 1 See Classification Temp in table 2 Time (tP) within 5°C of the specified classification temperature (Tc) 20 seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. Time 25°C to peak temperature 6 minutes max. 8 minutes max. * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Classification Profile

Copyright  ANPEC Electronics Corp. Table 2. Pb-free Process – Classification Temperatures (Tc) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)