APA2057AQBI-TRG

APA2057A_09 ANPEC | Alldatasheet

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Technical content

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw1 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. 2.4W Stereo Audio Power Amplifier (with Gain Setting) & Capfree Headphone Driver APA2057A The APA2057A is a monolithic integrated circuit, which combines a stereo power amplifier and a stereo output capacitor-less headphone amplifier. The stereo power amplifier provides 19-steps gain setting for flexible application. The headphone amplifier is ground-refer- ence output, and doesn’t nee d the output capacitors for DC blocking. The advantages of eliminating the output capacitor are saving cost, PCB’s space, and component height. Both t he de-pop circuitry and the thermal shutdow n protection circuitry are integrated in the APA2057A, which reduces pops and clicks noise during power on/ off and in shutdown mode. Thermal shutdown protects the chip from being destroyed by over-temperature failure. To simplify the audio system design in notebook computer applications, th e APA2057A provides the in- ternal gain setting, and the se features can minimize components and PCB area. The APA2057A is available in both TSSOP-28P and TQFN5x5-28 packages. Both packages are character- ized by space saving and thermal efficiency. Features General Description

Applications

• Note Book PCs
• LCD Monitor
• Operating Voltage – HVDD= 3.0~3.6V – VDD= 4.5~5.5V
• No Output Capacitor at Headphone Amplifier Required
• Meeting VISTA Requirement
• Low Distortion AMP Mode – THD+N=56dB, at VDD = 5V, RL = 4W, PO=1.5W – THD+N=64dB, at VDD = 5V, RL = 8W, PO=0.9W HP Mode – THD+N=73dB, at HVDD=3.3V, RL=16W PO=125mW – THD+N=77dB, at HVDD=3.3V, RL=32W, PO=88mW – THD+N=85dB, at HVDD=3.3V, RL=10kW, VO=1.7Vrms
• Output Power at 1% THD+N – 1.9W, at VDD = 5V, AMP Mode, RL = 4W – 1.2W, at VDD = 5V, AMP Mode, RL = 8W
• at 10% THD+N – 2.4W at VDD = 5V, AMP Mode, RL = 4W – 1.5W at VDD = 5V, AMP Mode, RL = 8W
• Depop Circuitry Integrated
• Internal 19-Steps Gain Setting for Flexible Applica- tion
• Thermal Shutdown Protection and Over-Current Protection Circuitry
• High Supply Voltage Ripple Rejection
• Surface-Mount Packaging – TSSOP-28P (with Enhanced Thermal Pad) – TQFN5x5-28 (with Enhanced Thermal Pad)
• Lead Free and Green Devices Available (RoHS Compliant)

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw2 APA2057A Ordering and Marking Information Pin Configuration Absolute Maximum Ratings (Note 1) Symbol Parameter Rating Unit VDD Supply Voltage (PVDD, CVDD, VDD) V HVDD, Supply Voltage (HVDD) -0.3 to 6 VSS Supply Voltage (VSS) +0.3 to -6 V VSET, VAMP_EN, VHP_EN Input Voltage 0 to VDD+0.3V TA Operating Ambient Temperature Range -40 to 85 °C TJ Maximum Junction Temperature 150 °C (Over operating free-air temperature range unless otherwise noted.) Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). = Thermal Pad (connected the Thermal Pad to GND plane for better heat dissipation) INR_A 3 INR_H 4 LOUT- 9 LOUT+ 8 INL_A 5 PVDD 10 CVDD 11 CGND 13 APA2057A

15 CVSS

16 HVSS

17 HP_R

18 HP_L

21 ROUT-

19 HVDD

20 PVDD

22 ROUT+

23 PGND

24 HP_EN

25 BIAS

INL_H 6 PGND 7 CP- 14 CP+ 12

28 BEEP

27 AMP_EN

26 SET

(Top view) (TSSOP-28P) (Top view) (TQFN5x5-28) APA2057A

20 HP_EN

17 ROUT-

15 HVDD

16 PVDD

18 ROUT+

19 PGND

21 BIAS

24 BEEP

25 VDD

26 GND

27 INR_A

28 INR_H

22 SET

23 AMP_EN

INL_A 1 PVDD 6 CVDD 7 INL_H 2 CP- 10 CGND 9 CP+ 8 CVSS 11 HVSS 12 HP_R 13 HP_L 14 APA2057A Handling Code Temperature Range Package Code Package Code R : TSSOP-28P QB : TQFN5x5-28 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA2057A R : APA2057A XXXXX XXXXX - Date Code XXXXX - Date Code Assembly Material APA2057A QB : APA2057A XXXXX

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw3 APA2057A Absolute Maximum Ratings (Cont.) (Note 1) Symbol Parameter Rating Unit TSTG Storage Temperature Range -65 to +150 °C TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °C PD Power Dissipation Internally Limited W (Over operating free-air temperature range unless otherwise noted.) Note 1 : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Thermal Characteristics Symbol Parameter Typical Value Unit θ JA Thermal Resistance - Junction to Ambient (Note 2) TSSOP-28P TQFN5x5-28 oC/W Note 2 : 3.42 in2 printed circuit board with 2OZ trace and copper through 10 vias of 15mil diameter vias. The thermal pad on the TSSOP- 28P & TQFN-28 packages with solder on the printed circuit board. Symbol Parameter Range Unit VDD Supply Voltage 4.5 ~ 5.5 V HVDD Supply Voltage 3.0 ~ 3.6 V VIH High Level Threshold Voltage AMP_EN, HP_EN 2 ~ V VIL Low Level Threshold Voltage AMP_EN, HP_EN ~ 0.8 V for Amplifier ~ VDD-1 Vicm Common Mode Input Voltage for Headphone Amplifier ~ HVDD-1 V Shutdown ~ 0.8 Gain Setting 2 ~ 4.2 VSET Input Voltage Fix Gain 4.5 ~ V

Electrical Characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Supply Voltage 4.5 - 5.5 V HVDD Headphone Amplifier Supply Voltage 3.0 - 3.6 V IVDD VDD Supply Current - 17.5 29 IHVDD HVDD Supply Current Only Speaker mode, AMP_EN = HP_EN = 0V - 0.15 1 IVDD VDD Supply Current - 12 20 IHVDD HVDD Supply Current Only Headphone mode, HP_EN = AMP_EN = 5V - 3 5 IVDD VDD Supply Current - 20 35 IHVDD HVDD Supply Current All Enable, HP_EN=5V and AMP_EN = 0V - 3 5 mA VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted).

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw4 APA2057A Electrical Characteristics (Cont.) APA2057A Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD(HVDD) HVDD Shutdown Current - 50 90 ISD(VDD) VDD Shutdown Current SET = 0V - 1 10 µA IAMP_EN Input Current AMP_EN - 1 - µA IHP_EN Input Current HP_EN - 10 15 µA SPEAKER MODE THD+N =1%, fin =1kHz RL =4Ω RL =8Ω 1.0 1.9 1.2 PO Output Power THD+N =10%, fin =1kHz RL =4Ω RL =8Ω 1.3 2.4 1.5 W VOS Output Offset Voltage RL =8Ω , Gain =10.5dB - - 10 mV THD+N Total Harmonic Distortion Plus Noise fin =1kHz PO = 1.5W, RL =4Ω PO = 0.9W, RL =8Ω 0.15 0.06 - % fin =1kHz, CB=2.2µF, RL=8Ω , PO=0.92W - 80 - Crosstalk Channel Separation fin =1kHz, CB=2.2µF, RL =4Ω , PO=1.5W - 83 - dB PSRR Power Supply Rejection Ratio CB =2.2µF, RL =8Ω , fin =120Hz - 70 - dB S/N PO =0.8W, RL =8Ω , A-weighting Filter - 90 - dB Vn Noise Output Voltage Gain =10.5dB, RL =8Ω , CB =2.2µF - 80 - µV (rms) HEADPHONE MODE THD+N = 1%, fin =1kHz RL = 16Ω RL = 32Ω 100 160 120 Po Output Power THD+N = 10%, fin =1kHz RL =16Ω RL =32Ω 150 200 165 mW THD+N=10% - 2.9 - Vo Output Voltage Swing RL =10kΩ THD+N=1% - 2.4 - Vrms Vos Output Offset Voltage RL =32Ω -10 +10 mV THD+N Total Harmonic Distortion Plus Noise fin = 1kHz PO = 125mW, RL =16Ω PO = 88mW, RL =32Ω VO=1.7Vrms, RL=10kΩ 0.02 0.02 0.005 - % fin =1kHz, RL =16Ω , PO =125mW - 80 - fin =1kHz, RL =32Ω , PO =88mW - 85 - Crosstalk Channel Separation fin =1kHz, RL=10kΩ , VO =1.7Vrms - 105 - dB PSRR Power Supply Rejection Ratio CB = 2.2µF, RL=32Ω, fin =120Hz - 80 - dB VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted).

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw5 APA2057A Electrical Characteristics (Cont.) APA2057A Symbol Parameter Test Conditions Min. Typ. Max. Unit HEADPHONE MODE (CONT.) S/N With A-weighting Filter PO = 70mW, RL =32Ω VO =1.2Vrms, RL=10kΩ - dB Vn Noise Output Voltage CB =2.2µF - 30 - µV (rms) Rf Input Feedback Resistance 38 40 42 kΩ CHARGE PUMP Fosc Switching Frequency 460 540 620 kHz CVSS Charge Dump Output Voltage (CVSS) No load - -0.98 VDD - V Req Charge Pump Requirement Resistance - 9 12 Ω BEEP Vbeep Beep Trigger Level - 3 - VPP TRES Beep Response Time - 4 - ms ATTENUATION RL = 32Ω , VO = 1.1Vrms, fin = 1kHz - 115 - dB Att (HP_EN) HP Disable Attenuation RL = 10kΩ , VO = 1.1Vrms, fin = 1kHz - 85 - dB RL = 8Ω , VO = 2Vrms, fin = 1kHz - 112 - dB Att (AMP_EN) AMP Disable Attenuation RL = 4Ω , VO = 2Vrms, fin = 1kHz - 112 - dB Att_SD (HP_EN) Shutdown Active RL = 10kΩ on the Headphone Mode, VO = 1.1Vrms, fin = 1kHz - 90 - dB Att_SD(AMP_EN) Shutdown Active RL = 8Ω on the AMP Mode, VO = 1Vrms, fin = 1kHz - 100 - dB HEADPHONE TO SPEAKER CROSSTALK AMP_EN = 0V, RL = 8Ω Crosstalk Channel Separation HP_EN = 5V, RL = 16Ω , fin = 1kHz, PO = 125mW - 85 - dB SPEAKER TO HEADPHONE CROSSTALK HP_EN = 5V, RL = 10kΩ Crosstalk Channel Separation AMP_EN = 0V, RL = 4Ω , fin = 1kHz, PO = 1.5W - 80 - dB AMPLIFIER START-UP TIME Tstart-up Start-Up Time - 120 - msec VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted).

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw6 APA2057A Input Voltage (VSET) Gain (dB) Low (V) High (V) Hysteresis (mV) Recommended Voltage (V) -70 0 2.00 SD 0.00 -7 2.04 2.12 47 2.08 -5 2.15 2.24 36 2.20 -3 2.28 2.35 41 2.31 -1 2.39 2.47 41 2.43 1 2.51 2.58 35 2.54 3 2.62 2.70 41 2.66 4 2.74 2.81 48 2.78 5 2.86 2.92 43 2.89 6 2.97 3.04 47 3.01 7 3.09 3.15 45 3.12 8 3.21 3.27 54 3.24 9 3.33 3.39 59 3.36 10 3.45 3.51 64 3.48 11 3.56 3.62 53 3.59 12 3.68 3.73 59 3.70 13 3.80 3.85 66 3.82 14 3.92 3.96 69 3.94 15 4.02 4.07 64 4.05 16 4.15 4.17 76 4.16 10.5 4.26 5.00 94 5.00 Gain Setting Table _AMP Mode (VDD=5V)

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw7 APA2057A Recommend Resistance’s Value for Gain Setting Gain (dB) R1 (1%) R# (1%) -70 10k 0 -7 18k 13k -5 20k 16k -3 18k 16k -1 16k 15k 1 15k 16k 3 13k 15k 4 24k 30k 5 13k 18k 6 13k 20k 7 13k 22k 8 16k 30k 9 13k 27k 10 13k 30k 11 15k 39k 12 13k 39k 13 13k 43k 14 13k 50k 15 15k 68k 16 13k 68k 10.5 10k >90k

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw8 APA2057A THD+N (%) Output Power (W) Output Power (W) THD+N (%)Crosstalk (dB) THD+N (%) THD+N vs. Output Power Frequency (Hz) Frequency (Hz) THD+N vs. Output Power THD+N vs. Frequency Crosstalk vs. Frequency Output Noise Voltage (Vrms) Frequency (Hz) Output Noise Voltage vs. Frequency Gain (dB) Frequency Response Phase (deg) Frequency (Hz) Typical Operating Characteristics 0.05 0.1 0 30.5 1 1.5 2 2.5 VDD =5V fin=1kHz Cin=2.2µF BW<80kHz AMP mode RL=4ΩRL=8Ω 0.1 20 20k100 1k 10k VDD =5V RL=4Ω Cin=2.2µF PO=1.5W BW<80kHz AMP mode Right Channel Left Channel -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k Right to Left Left to Right VDD =5V RL=4 Cin=2.2µµuF PO=1.5W AMP mode Ω 100µ 10µ 20 20k100 1k 10k VDD =5V RL=4Ω Cin=2.2µF A-weighting AMP mode -5 +30 +10 +15 +20 +25 +11 +10 10 200k100 1k 10k 100k VDD =5V Cin =2.2µF RL=4Ω PO=0.2W AMP mode Gain Phase 0.1 0.01 50.1 1 2 VDD =5V RL=4Ω Cin=2.2µF BW<80kHz AMP mode fin=20kHz fin=20Hz fin=1kHz

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw9 APA2057A THD+N (%) Output Power (W) Frequency (Hz) THD+N (%)Output Noise Voltage (Vrms) Crosstalk (dB) THD+N vs. Output Power Frequency (Hz) Frequency (Hz) THD+N vs. Frequency Crosstalk vs. Frequency Output Noise Voltage vs. Frequency Gain (dB) Frequency (Hz) Frequency Response Crosstalk (dB) Crosstalk vs. Frequency Frequency (Hz) Phase (deg) Typical Operating Characteristics (Cont.) 0.05 0.1 0.01 50.1 1 VDD =5V RL=8Ω Cin=2.2µF BW<80kHz AMP mode fin=20Hzfin=20kHz fin=1kHz -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD =5V RL=8 Cin=2.2 F PO=0.92W AMP mode Right to Left Left to Right Ω µ 100µ 10µ 20 20k100 1k 10k VDD =5V RL=8Ω Cin=2.2µF A-weighting AMP mode -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD =5V RL=4Ohm (AMP) RL=10kΩ (HP) Cin=2.2µF (AMP) PO=1.5W(AMP) AMP (active) mode HP Mode Right(AMP) to Right(HP) Right(AMP) to Left(HP) Left(AMP) to Left(HP) Left(AMP) to Right(HP) 0.05 0.1 20 20k100 1k 10k VDD =5V RL=8Ω Cin=2.2µF PO=0.92W BW<80kHz AMP mode Right Channel Left Channel +30 +10 +15 +20 +25 +11 +10 10 200k100 1k 10k 100k VDD =5V Cin =2.2µF RL=8Ω PO=0.13W AMP mode Gain Phase

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw10 APA2057A AMP Attenuation (dB) Frequency (Hz) Frequency (Hz) AMP Attenuation (dB)Shutdown Attenuation (dB) Shutdown Attenuation (dB) AMP Attenuation vs. Frequency Frequency (Hz) Frequency (Hz) AMP Attenuation vs. Frequency Shutdown Attenuation vs. Frequency Shutdown Attenuation vs. Frequency Output Voltage (Vrms) Input Voltage (Vrms) Input Voltage vs. Output Voltage Output Voltage (Vrms) Input Voltage vs. Output Voltage Input Voltage (Vrms) Typical Operating Characteristics (Cont.) 3.5 0.5 1.5 2.5 VDD =5V RL=4Ω Cin=2.2µF fin=1kHz AMP mode 0.5 1.5 2.5 3.5 VDD =5V RL=8Ω Cin=2.2µF fin=1kHz AMP mode -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD =5V RL=4Ω Cin=2.2µF VO=2Vrms(fin=1kHz, AMP enable) AMP mode (disable) -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD =5V RL=8Ω Cin=2.2µF VO=2Vrms(fin=1kHz,AMP enable) AMP mode (disable) -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD =5V RL=4Ω Cin=2.2µF VO=1Vrms(fin=1kHz) Shutdown active AMP mode -120 -110 -100 20 20k100 1k 10k VDD =5V RL=8Ω Cin=2.2µF VO=1Vrms(fin=1kHz) Shutdown active AMP mode -90 -80 -70 -60 -50 -40 -30 -20 -10

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw11 APA2057A THD+N (%) Output Voltage (Volt) Output Power (W) THD+N (%)THD+N (%) THD+N (%) THD+N vs. Output Voltage Output Power (W) Frequency (Hz) THD+N vs. Output Power THD+N vs. Output Power THD+N vs. Frequency Crosstalk (dB) Frequency (Hz) Crosstalk vs. Frequency Output Noise Voltage (Vrms) Output Noise Voltage vs. Frequency Frequency (Hz) Typical Operating Characteristics (Cont.) 0.001 0.01 0.1 30.5 1 1.5 2 2.50 TT RL=10kΩ RL=300Ω RL=32Ω RL=16Ω VDD =5V HVDD=3.3V fin=1kHz Cin=3.3µF BW<80kHz HP mode 0.01 0.1 1m 300m10m 100m VDD =5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3.3µF BW<80kHz HP mode fin=20kHz fin=20Hz fin=1kHz 0.01 0.1 0 250m50m 100m 150m 200m VDD=5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3.3µF fin=1kHz BW<80kHz HP mode Stereo, in phase Stereo, 180O out of phase Mono -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k Right to Left Left to Right VDD=5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3.3µF PO=125mW HP mode 100µ 10µ 20 20k100 1k 10k VDD =5V HVDD =3.3V RL=16Ω Rin=39kΩ Cin=3.3µF A-weighting HP mode Right channel Left channel 0.005 0.01 0.1 20 20k100 1k 10k VDD =5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3.3µF PO=125mW HP mode BW<80kHz BW<22kHz

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw12 APA2057A Gain (dB) Frequency (Hz) Output Power (W) THD+N (%)THD+N (%) THD+N (%) Frequency Response Output Power (W) Frequency (Hz) THD+N vs. Output Power THD+N vs. Output Power THD+N vs. Frequency Crosstalk (dB) Frequency (Hz) Crosstalk vs. Frequency Output Noise Voltage (V) Output Noise Voltage vs. Frequency Frequency (Hz) Phase (deg) Typical Operating Characteristics (Cont.) +170 +190 +175 +180 +185 -0.2 +0.2 -0.1 +0.1 10 200k100 1k 10k 100k Gain Phase VDD=5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3.3µF PO=28mW HP mode 0.01 0.1 1m 200m10m 100m fin=20kHz fin=20Hz fin=1kHz VDD=5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF BW<80kHz HP mode 0.01 0.1 0 200m50m 100m 150m VDD=5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF fin=1kHz BW<80kHz HP mode Stereo, in phase Stereo, 180O out of phase Mono 0.001 0.01 0.1 20 20k100 1k 10k BW<80kHz BW<22kHz VDD=5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF PO=88mW HP mode -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD=5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF PO=88mW HP mode Right to Left Left to Right 100µ 10µ 20 20k100 1k 10k Right channel Left channel VDD =5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF A-weighting HP mode

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw13 APA2057A Gain (dB) Frequency (Hz) Output Voltage (Vrms) THD+N (%)Crosstalk (dB) THD+N (%) Frequency Response Frequency (Hz) Frequency (Hz) THD+N vs. Output Voltage THD+N vs. Frequency Crosstalk vs. Frequency Output Noise Voltage (Vrms) Frequency (Hz) Output Noise Voltage vs. Frequency Gain (dB) Frequency Response Frequency (Hz) Phase (deg) Phase (deg) Typical Operating Characteristics (Cont.) +170 +190 +175 +180 +185 -0.2 +0.2 -0.1 +0.1 10 200k100 1k 10k 100k VDD =5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF PO=13mW HP mode Gain Phase 0.001 0.01 0.1 0 30.5 1 1.5 2 2.5 fin=20Hz fin=20kHz fin=1kHz VDD=5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF BW<80kHz HP mode -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k Left to Right Right to Left VDD=5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF VO=1.7Vrms BW<80kHz HP mode +175 +195 +180 +185 +190 -0.4 +0.4 -0.2 +0.2 10 200k100 1k 10k 100k Gain Phase VDD =5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF VO=240mVrms HP mode 0.001 0.01 0.1 20 20k100 1k 10k Right Channel Left Channel VDD=5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF VO=1.7Vrms BW<80kHz HP mode 100µ 10µ 20 20k100 1k 10k VDD =5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF A-weighting HP mode Left channel Right channel

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw14 APA2057A THD+N (%) Output Voltage (Volt) Frequency (Hz) THD+N (%)Output Noise Voltage (Vrms) Crosstalk (dB) THD+N vs. Output Voltage Frequency (Hz) Frequency (Hz) THD+N vs. Frequency Crosstalk vs. Frequency Output Noise Voltage vs. Frequency Gain (dB) Frequency (Hz) Frequency Response Crosstalk (dB) Crosstalk vs. Frequency Frequency (Hz) Typical Operating Characteristics (Cont.) Phase (deg) 0.001 0.01 0.1 0 30.5 1 1.5 2 2.5 fin=20Hz fin=20kHz fin=1kHz VDD =5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF BW<80kHz HP mode -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD=5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF VO=1.7Vrms BW<80kHz HP mode Left to Right Right to Left 100µ 10µ 20 20k100 1k 10k VDD=5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF A-weighting HP mode Right channel Left channel +175 +195 +180 +185 +190 -0.4 +0.4 -0.2 +0.2 10 200k100 1k 10k 100k Gain Phase VDD=5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF VO=240mVrms HP mode 0.001 0.01 0.1 20 20k100 1k 10k VDD =5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF VO=1.7Vrms BW<80kHz HP mode Right channel Left channel -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD =5V HVDD=3.3V RL=16Ω (HP) RL=8Ω (AMP) Rin=39kΩ (HP) Cin=3.3µF (HP) PO=125mW(HP) AMP (active) mode HP Mode Right (HP) to Right (AMP)Left (HP) to Right (AMP) Right (HP) to Left (AMP)Left (HP) to Left (AMP)

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw15 APA2057A HP Attenuation (dB) Frequency (Hz) Frequency (Hz) HP Attenuation (dB)Shutdown Attenuation (dB) Shutdown Attenuation (dB) HP Attenuation vs. Frequency Frequency (Hz) Frequency (Hz) HP Attenuation vs. Frequency Shutdown Attenuation vs. Frequency Shutdown Attenuation vs. Frequency Output Voltage (Vrms) Input Voltage (Vrms) Input Voltage vs. Output Voltage Output Voltage (Vrms) Input Voltage vs. Output Voltage Input Voltage (Vrms) Typical Operating Characteristics (Cont.) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD =5V HVDD=3.3V RL=32Ω Cin=3.3µF VO=1Vrms(fin=1kHz) Shutdown active HP mode Left channel Right channel -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD =5V HVDD=3.3V RL=10kΩ Cin=3.3µF VO=1Vrms(fin=1kHz) Shutdown active HP mode Left channel Right channel 0.5 1.5 2.5 0 30.5 1 1.5 2 2.5 VDD =5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3µF fin=1kHz HP mode Stereo, in phase Mono -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD =5V HVDD=3.3V RL=10kΩ Cin=3.3µF VO=1Vrms(fin=1kHz HP enable) HP mode (disable) Left channelRight channel 2.5 0.5 1.5 0 2.50.5 1 1.5 2 Stereo, in phase Mono VDD =5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3µF fin=1kHz HP mode -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD =5V HVDD=3.3V RL=32Ω Cin=3.3µF VO=1Vrms(fin=1kHz HP enable) HP mode (disable) Right channel Left channel

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw16 APA2057A Output Voltage (Vrms) Input Voltage (Vrms) Input Voltage (Vrms) Output Voltage (Vrms) Input Voltage vs. Output Voltage Input Voltage vs. Output Voltage PSRR vs. Frequency PSRR vs. Frequency PSRR (dB) Frequency (Hz) PSRR vs. Frequency PSRR (dB) PSRR vs. Frequency Frequency (Hz) PSRR (dB) PSRR (dB) Frequency (Hz) Frequency (Hz) Typical Operating Characteristics (Cont.) 0.5 1.5 2.5 0 30.5 1 1.5 2 2.5 Stereo, in phase Mono VDD =5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3µF fin=1kHz HP mode 0.5 1.5 2.5 0 30.5 1 1.5 2 2.5 Mono & Stereo, in phase VDD =5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3µF fin=1kHz HP mode 20 20k100 1k 10k VDD =5V RL=8Ω Cin=2.2µF Vrr=200mVrms AMP mode Right channel Left channel -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Vrr: Ripple Voltage on VDD -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k Left channel Right channel VDD =5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF Vrr=200mVrms HP mode Vrr: Ripple Voltage on HVDD -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD =5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF Vrr=200mVrms HP mode Left channel Right channel Vrr: Ripple Voltage on HVDD -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k Right channel Left channel VDD=5V RL=4Ω Cin=2.2µF Vrr=200mVrms AMP mode Vrr: Ripple Voltage on VDD

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw17 APA2057A Supply Current (mA) Supply Voltage (Volt) Supply Voltage (Volt) Shutdown Current ( µA) Supply Current vs. Supply Voltage Shutdown Current vs. Supply Voltage Power Dissipation vs. Output Power Power Dissipation vs. Output Power Output Power vs. Load Resistance Output Power vs. Load Resistance & Charge Pump Capacitance Power Dissipation (W) Power Dissipation (mW) Output Power (W) Output Power (mW) Output Power (mW) Output Power (mW) Load Resistance (Ω ) Load Resistance (Ω ) Typical Operating Characteristics (Cont.) Amp mode HP mode No Load ISD(VDD) ISD(HVDD) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VDD =5V THD+N <1% AMP mode RL=8Ω RL=4Ω 0 50 100 150 200 RL=16Ω RL=32Ω VDD =5V HVDD=3.3V THD+N <1% HP mode 100 150 200 250 300 350 400 No Load HP Mode AMP Mode *HP Mode disable HVDD=3.3V IHVDD=0.15mA **AMP Mode disable VDD=5V IVDD=12mA 10 100 1000 Mono, THD+N=10% Mono, THD+N=1% VDD =5V HVDD=3.3V fin=1kHz BW<80kHZ HP mode 100 150 200 250 300 10 20 30 40 50 60 70 80 90 100 VDD =5V fin=1kHz BW<80kHZ HP mode CF=CCO=2.2µF THD+D=1%; Mono & Stereo, in phase CF=CCO=1µF THD+N=1%; Mono CF=CCO=1µF THD+N=1%; Stereo, in phase CF :Charge pump flying capacitor CCO:Charge pump output capacitor 100 150 200 250 300 350

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw18 APA2057A Input Resistance (kΩ )_AMP Mode Gain (dB)_AMP Mode Input Resistance vs. Amplifier's Gain Typical Operating Characteristics (Cont.) 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 35.0 37.5 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 VDD =5V fin=1kHz BW<80kHZ No Load AMP mode

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw19 APA2057A Operating Waveforms Output Transient at Shutdown ReleaseOutput Transient at Turn On AMP_Out ((Out+)-(Out-)) VDD HP_Out 5V/div 10mV/div 20mV/div SD HP_Out AMP_Out ((Out+)-(Out-)) 5V/div 10mV/div 20mV/div 20ms/div 20ms/div Output Transient at Turn Off Output Transient at Shutdown Active VDD HP_Out AMP_Out ((Out+)-(Out-)) 5V/div 10mV/div 20mV/div AMP_Out ((Out+)-(Out-)) HP_Out 5V/div 10mV/div 20mV/div SD 200ms/div 20ms/div

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw20 APA2057A PIN NO. TSSOP-28 TQFN5x5-28 NAME FUNCTION 1 25 VDD Power supply for control section 2 26 GND Ground 3 27 INR_A Right channel input terminal for speaker amplifier 4 28 INR_H Right channel input terminal for headphone driver 5 1 INL_A Left channel input terminal for speaker amplifier 6 2 INL_H Left channel input terminal for headphone driver 7,23 3,19 PGND Power ground 8 4 LOUT+ Left channel positive output for speaker 9 5 LOUT- Left channel negative output for speaker 10,20 6,16 PVDD Power amplifier power supply 11 7 CVDD Charge pump power supply 12 8 CP+ Charge pump flying capacitor positive connection 13 9 CGND Charge pump ground 14 10 CP- Charge pump flying capacitor negative connection 15 11 CVSS Charge pump output, connect to the “HVSS” 16 12 HVSS Headphone amplifier negative power supply 17 13 HP_R Right channel output for headphone 18 14 HP_L Left channel output for headphone 19 15 HV DD Headphone amplifier positive power supply 21 17 ROUT- Right channel negative output for speaker 22 18 ROUT+ Right channel positive output for speaker 24 20 HP_EN Headphone driver enable pin, pull high to enable headphone mode 25 21 BIAS Bias voltage generator 26 22 SET It has 19 steps gain setting control from 2.0~4.2V; pull high to 5V is 10.5dB fix gain and pull low to 0V, the APA2057A enter shutdown mode. ISD = 80µA 27 23 AMP_EN Speaker driver enable pin, pull low to enable speaker mode 28 24 BEEP PC BEEP Trigger signal input Pin Description

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw21 APA2057A Block Diagram Charge Pump SPK EN HP EN INR_A INL_A INR_H INL_H SET BIAS CP+ CP- CVSS HP_R HP_L AMP_EN HP_EN SET HVSS *40kW *40kW HVDD Power Mamagement PVDD VDD CVDD Internal gain setting CGND PGND GND ROUT- ROUT+ LOUT- LOUT+ * The internal Rf's value has 10% variation by process Rf(HP_R) Rf(HP_L) BEEP BEEP detect

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw22 APA2057A Typical Application Circuit Ring Headphone Jack Sleeve Tip R_CH R_ch for AMP L_ch for AMP R_ch for HP 39kΩ 2.2µF 2.2µF 4 Ω Charge Pump SPK EN HP EN INR_A INL_A INR_H INL_H SET BIAS CP+ CP- HP_R HP_L AMP_EN HP_EN SET VSS *40kW *40kW HVDD Power Mamagement PVDD VDD CVDD Internal gain setting CGND PGND GND ROUT- ROUT+ 2.2µF 3.3µF L_ch for HP 39kΩ3.3µF 1µF 1µF L_CH 4 Ω LOUT- LOUT+ 1µF 0.1µF 0.1µF 10µF 0.1µF Ci(AMP_R) Ci(AMP_L) Ci(HP_R) Ci(HP_L) Ri(HP_R) Ri(HP_L) Rf(HP_R) Rf(HP_L) CCPB CCPF CCPO 10nF VDD(5V) 10kΩ R#Shutdown R#: For the gain setting of speaker driver that you need, refer to the Gain Setting Table s recommended voltage, and setting this voltage at SET pin s voltage =5R#/(R#+10k). R1<=25kΩ . VDD(5V) VDD(5V) HVDD(3.3V) VSS 510kΩ 0.47nF Recommended for de-pop CB Pull-high HP_EN to enable headohone driver CS(VDD) CS(PVDD) CS(HVDD) SET BEEP Detect BEEP 0.47µF

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw25 APA2057A HP Mode Gain Setting Table for Reference Ri(HP),external (kΩ ) *Rf(HP),internal (kΩ ) HP OUT (V/V) HP Gain(dB) 62 40 0.65 -3.8 50 40 0.80 -1.9 39 40 1.03 0.2 30 40 1.33 2.5 24 40 1.67 4.4 20 40 2.00 6.0 *The internal Rf's value has 10% variation by process. When the input resistance variation is considered, the C i is 1.6µF, so a value in the range of 2.2 µF to 3.3µF would be chosen. A further consideration for this capacitor is the leakage path from the input source through the input network (R i+Rf, C i) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifiers’ input becaue the DC level of the amplifiers’ input is held at VDD/2. Please note that it (2) is important to confirm the capacitor polarity in the application. Note: The headphone dirver’s input is ground reference, so please check the C i(HP)’s polarized at design. Effective Bias Capacitor, CB As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as possible. The effect of a larger bypass capacitor is improved PSRR due to increased 1.8V bias voltage stability. Typical appli- cations employ a 5V regulator with 2.2 µF and a 0.1 µF bypass capacitor, which aids in supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA2057A. The selection of bypass capacitors, espe- cially CB, is dependent upon desired PSRR requirements and click-and-pop performance. Power Supply Decoupling, Cs The APA2057A is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) is as low as possible. Power supply decoupling also prevents the oscillations being caused by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different types of capacitor that target on different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent- series-resistance (ESR) ceramic capacitor, typically 0.1µF, is placed as close as possible to the device V DD lead works best (the pin1 (VDD) and pin2 (GND)’s capaci- tor must short less than 1cm). For filtering lower-frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater is placed near the audio power amplifier is recommended. Shutdown Function In order to reduce power consumption while not in use, the APA2057A contains a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the SET pin. The trigger point between a logic high and logic Application Information (Cont.) Input Capacitor, Ci In the typical application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, C i and the minimum input impedance R i from a high-pass filter with the corner frequency are determined by the following equation: The value of C i must be considered carefully because it directly affects the low frequency performance of the circuit. Consider the example where R i is 10k Ω and the specification calls for a flat bass response down to 10Hz. Equation is reconfigured as below: For headphone driver, the internal feedback resistor is 40kΩ (Rf(HP) external, 10% variation by process), therefore, the headphone driver’s gain is set by the input resistor (Ri(HP) external), the Table 1 lists the reference gain set- tings with external resistor for headphone driver (HP Mode). Table 1: Gain Setting Table for Reference Gain Setting (Cont.) )CR(2 1 =(highpass) F ii(MIN) C (1) Fc)R(2 1 =C i i π

Copyright  ANPEC Electronics Corp. both of equations depending on the mode of operation. speaker impedance for the application. conditions is 4 times as in SE mode. by the operational amplifier’s offset. ance is 100kΩ on PCBEEP input pin. equations are the basis for calculating amplifier efficiency. Table 2. Efficiency vs. Output Power in 5-V/8W Differential

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw27 APA2057A Thermal Consideration Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. In the Power Dissipation vs. Output Power graph , the APA2057A is operating at a 5V supply and a 4Ω speaker that 2W output power peaks are available. The vertical axis gives the information of power dissipation (PD) in the IC with respect to each output driving power (P O) on the horizontal axis. This is valuable information when attempting to estimate the heat dissipation of the IC requirements for the ampli- fier system. Using the power dissipation curves for a 5V/4 Ω system, the internal dissipation in the APA2057A and maximum ambient temperatures is shown in Table 3. Application Information (Cont.) For TSSOP-28 package with thermal pad, the thermal resistance (θ JA) is equal to 45 oC/W. Since the maximum junction temperature (T J,MAX ) of APA2057A is 150°C and the ambient temperature (T A) is defined by the power system design, the maximum power dissipation that the IC package is able to handle can be obtained from equation10. Once the power dissipation is greater than the maximum limit (PD,MAX), either the sup- ply voltage (VDD) must be decreased, the load impedance (RL) must be increased or the ambient temperature should be reduced. Thermal Pad Consideration The thermal pad must be connected to the ground. The package w ith thermal pad of the APA2057A re- quires sp ecial attention on ther mal design. If the ther- mal design issues are not properly addressed, the APA2057A 4Ω will go into thermal shutdown when driving a 4Ω load. The thermal pad on the bottom of the APA2057A should be soldered down to a copper pad on the circuit board. Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on the top surface of the circuit board, 8 to 10 vias of 15 mil or smaller in diameter should be used to ther- mally couple the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to conduct heat away from the thermal pad should be as large as practical. If the ambient temperature is higher than 25 °C, a larger copper plane or forced-air cooling will be required to keep the APA2057A junction temperature below the thermal shutdown temperature (150 °C). In higher ambient temperature, higher airflow rate and/or larger copper area will be required to keep the IC out of thermal shutdown. See Demo Board Circuit Layout as an example for PCB layout. dissipation from equation 9, assuming a 5V-power sup- ply and an 8 Ω load, must not be greater than the power dissipation that results from the equation 9: (10) JA AMAXJ, MAXD, T - T = P θ Power Dissipation (Cont.) 15 mil 12mil Via diameter =25mil X4Via diameter =15mil X10 Ground plane for ThermalPAD 70 mil 70 mil180 mil 120 mil 240 mil Exposed for thermal PAD connected Figure 5: TSSOP-28P Layout Recommendation Max. TA (°C) Peak output power (W) Average output power (W) Power dissipation (W/channel) With thermal pad 2 1.95 1.25 37 2 1.17 1.25 37 2 0.74 1.19 43 2 0.43 1.05 55 2 0.19 0.8 78 Table 3: APA2057A Power information, 5V/4Ω , Stereo, Differential mode

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw28 APA2057A Thermal Consideration (Cont.) Table 3 shows that for some applications, no airflow is required to keep junction temperatures in the specified range. The APA2057A is designed with a thermal shut- down protection that turns the device off when the junc- tion temperature surpasses 150 °C to prevent IC from damage. The information in table 3 was calculated for maximum listen volume with limited distortion. When the output level is reduced, the numbers in the table change significantly. Also, using 8 Ω speakers will dramatically increase the thermal performance by increasing ampli- fier efficiency. Application Information (Cont.) 150 - 45(0.8x2) = 78 °C (with thermal pad) NOTE: Internal dissipation of 0.8W is estimated for a 2W system with 15-dB headroom per channel. P - T = T DJAMaxJ,MaxA, θ (11) This parameter is measured with the recommended cop- per heat sink pattern on a 2-layer PCB, 23cm 2 in 5. 7mmx4mm in PCB, 2oz. Copper, 100mm2 coverage. Air- flow 0 CFM the maximum ambient temperature depends on the heat sink ability of the PCB system. To calculate maximum ambient temperatures, first con- sideration is that the numbers from the dissipation graphs are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given θ JA, the maximum allowable junction temperature (TJ,Max), and the total intemal dissipation (PD), the maxi- mum ambient temperature can be calculated with the following equation. The maximum recommended junc- tion temperature for the APA2057A is 150°C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graph. Package qJA TSSOP-28 45°C/W TQFN -28 43°C/W Table 4: Thermal resistance Table

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw29 APA2057A

Package Information

Note : 1. Followed from JEDEC MO-153 AET. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. S Y M B O L MIN. MAX. 1.20 0.05 0.09 0.20 9.60 9.80 0.15 A c D E e L MILLIMETERS b 0.19 0.30

0.65 BSC

0.45 0.75

0.026 BSC

MIN. MAX. INCHES 0.047 0.002 0.007 0.012 0.004 0.008 0.378 0.386 0.169 0.177 0.018 0.030 0.006 A2 0.80 1.05 4.30 4.50E1 0.031 0.041 4.50D1 0.177 E2 2.50 0.098 6.00 3.50 0.236 0.138 INCHES 8o 0o 8o0o 0VIEW A 0.25 SEATING PLANE GAUGE PLANE SEE VIEW A E b c A e A1 L E2EXPOS ED PAD D 6.20 6.60 0.244 0.260

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw30 APA2057A 0.70 0.150 0.028 0.002

0.50 BSC

SYMBOL MIN. MAX. 0.80 0.00 0.18 0.30 3.50 3.80 0.05 3.50 A b D E e L MILLIMETERS A3 0.20 REF TQFN5x5-28 0.35 0.45 3.80

0.008 REF

MIN. MAX. INCHES 0.031 0.000 0.007 0.012 0.138 0.150 0.138 0.014 0.018

0.020 BSC

0.20 0.008K 4.90 5.10 0.193 0.201 4.90 5.10 0.193 0.201 Note : 1. Followed from JEDEC MO-220 WHHD-3. D Pin 1 E b A Pin 1 Corner e KL

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw31 APA2057A Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 TSSOP-28P Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 TQFN5x5-28 (mm) Carrier Tape & Reel Dimensions Package Type Unit Quantity TSSOP- 28P Tape & Reel 2000 TQFN5x5-28 Tape & Reel 2500 Devices Per Unit A AB W F T P0OD0 B SECTION B-B SECTION A-A OD1 H A d

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw32 APA2057A TSSOP-28P Taping Direction Information TQFN5x5-28 USER DIRECTION OF FEED USER DIRECTION OF FEED

Copyright  ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 www.anpec.com.tw33 APA2057A Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds Average ramp-up rate (Tsmax to TP) 3 °C/second max. 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 183 °C 60-150 seconds 217 °C 60-150 seconds Peak package body Temperature (Tp)* See Classification Temp in table 1 See Classification Temp in table 2 Time (tP) within 5°C of the specified classification temperature (Tc) 20 seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. Time 25°C to peak temperature 6 minutes max. 8 minutes max. * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.

Copyright  ANPEC Electronics Corp. Table 2. Pb-free Process – Classification Temperatures (Tc) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)