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Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw1 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Stereo 2.6W Audio Amplifier (With Gain Control) APA2030/2031 APA2030/1 is a monolithic integrated circuit, which pro- vides internal gain control, and a stereo bridged audio power amplifiers capable of producing 2.6W (1.9W) into 3Ω with less than 10% (1.0%) THD+N. By controlling the two gain setting pins, Gain0 and Gain1, the amplifier can provide 6dB, 10dB, 15.6dB, and 21.6dB gain settings. The advantage of internal gain setting can be less com- ponents and PCB area. Both of the depop circuitry and the thermal shutdown protection circuitry are integrated in APA2030/1, that reduces pops and clicks noise during power up or shutdown mode operation. It also improves the power off pop noise and protects the chip from being destroyed by over temperature and short current failure. To simplify the audio system design, APA2030 combines a stereo bridge-tied loads (BTL) mode for speaker drive and a stereo single-end (SE) mode for headphone drive into a single chip, where both modes are easily switched by the SE/BTL input control pin signal. In addition, the multiple input selections are used for portable audio system. The APA2031 eliminates both input selection and single-end (SE) mode function to simplify the design and save the PCB space. Features General Description

Applications

  • Notebook PCs
  • LCD Monitor
  • Low Operating Current with 6mA
  • Improved Depop Circuitry to Eliminate Turn-On Transients in Outputs
  • High PSRR
  • Internal Gain Control, Eliminate External Components
  • 2.6W Per Channel Output Power into 3W Load at 5V, BTL Mode
  • Multiple Input Modes Allowable Selected by HP/LINE Pin (APA2030)
  • Two Output Modes Allowable with BTL and SE Modes Selected by SE/BTL Pin (for APA2030 only)
  • Low Current Consumption in Shutdown Mode (50mA)
  • Short Circuit Protection
  • TSSOP-24P (APA2030), TSSOP-20P, and TQFN3x3- 16 (APA2031) with Thermal Pad Packages.
  • Lead Free and Green Devices Available (RoHS Compliant) Pin Configuration = ThermalPad (connected the ThermalPad to GND plane for better heat dissipation) TSSOP-24P (Top View) LOUT+ 4 LOUT- 9

21 ROUT+

16 ROUT-

23 RLINEIN

20 RHPIN

15 SE/BTL

22 SHUTDOWNGAIN1 3

24 GND

13 GND

19 VDD

18 PVDDPVDD 7

14 PCBEEP

17 HP/LINE

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw2 APA2030/2031 Ordering and Marking Information Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration (Cont.) APA2030 Handling Code Temperature Range Package Code Package Code R : TSSOP-24P (APA2030) / TSSOP-20P (APA2031) QB : TQFN3x3-16 (APA2031) Operating Ambient Temperature Range I : - 40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA2030 R : XXXXX - Date Code Assembly Material APA2031 APA2030 XXXXX APA2031 R : XXXXX - Date CodeAPA2031 XXXXX APA2031 QB : XXXXX - Date Code APA 2031 XXXXX LOUT+ 4 LIN+ 9

17 RIN-

19 SHUTDOWN

16 VDD

11 GND

18 ROUT+GAIN1 3

20 GND

15 PVDD

14 ROUT-RIN+ 7

(Top View) = ThermalPad (connected the ThermalPad to GND plane for better heat dissipation) APA2031 TQFN3X3-16 (Top View)

5 LOUT+

6 LIN-

7 PVDD

8 RIN+

10 BYPASS

12 LOUT-

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw3 APA2030/2031 Absolute Maximum Ratings (Note 1) Symbol Parameter Rating Unit Supply Voltage Range, VDD, PVDD -0.3V to 6V V Input Voltage Range at SE/BTL, HP/LINE, SHUTDOWN, -0.3V to VDD V TA Operating Ambient Temperature Range -40 oC to 85 oC oC TJ Maximum Junction Temperature Internal Limited TSTG Storage Temperature Range -65 oC to 150 oC oC TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC oC PD Power dissipation Internal Limited (Over operating free-air temperature range unless otherwise noted.) Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter Typical Value Unit θ JA Thermal Resistance from Junction to Ambient in Free Air (Note 2) TSSOP-24P TSSOP-20P TQFN3x3-16 oC/W Note 2 : θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. * 5 in2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias. The thermal pad on the TSSOP_P and TQFN3x3-16 packages with solder on the printed circuit board. Recommended Operating Conditions Symbol Parameter Range Unit VDD Supply Voltage 4.5V to 5.5V V

Electrical Characteristics

(VDD=5V, -20°C<TA<85°C, unless otherwise noted.) APA2030 / 2031 Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Supply Voltage 3.3 - 5.5 V SE/BTL = 0V - 6 12 mA IDD Supply Current SE/BTL = 5V - 4 8 mA ISD Supply Current in Shutdown Mode SHUTDOWN = 0V - 50 300 µA SHUTDOWN, GAIN0, GAIN1 2 - - V VIH High Level Threshold Voltage SE/BTL, HP/LINE 4 - - V SHUTDOWN, GAIN0, GAIN1 - - 0.8 V VIL Low level Threshold Voltage SE/BTL, HP/LINE - - 3 V

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw4 APA2030/2031 Electrical Characteristics (Cont.) (VDD=5V, -20°C<TA<85°C, unless otherwise noted.) APA2030/2031 Symbol Parameter Test Conditions Min. Typ. Max. Unit II Input Current SHUTDOWN, SE/BTL, HP/LINE, GAIN0, GAIN1 - 5 - nA VICM Common Mode Input Voltage VDD-1.0 - - V VOS Output Differential Voltage - 5 - mV PC-BEEP Trigger Level - 1 - Vp.p RBYPASS BYPASS Equivalent Resistance - 250 - kΩ APA2030 / 2031 Symbol Parameter Test Conditions Min. Typ. Max. Unit THD+N=10%, fin=1kHz, RL=3Ω - 2.6 - W THD+N =10%, fin=1kHz, RL=4Ω - 2.3 - W THD+N =10%, fin=1kHz, RL=8Ω - 1.5 - W THD+N =1%, fin=1kHz, RL=3Ω - 1.9 - W THD+N =1%, fin=1kHz, RL=4Ω - 1.7 - W PO Maximum Output Power THD+N =1%, fin=1kHz, RL=8Ω 1 1.1 - W PO=1.1W, RL=4Ω fin=1kHz - 0.05 - % THD+N Total Harmonic Distortion Plus Noise PO=0.7W, RL=8Ω , fin=1kHz - 0.04 - % PSRR Power Ripple Rejection Ratio VIN=0.2Vrms, RL=8Ω , CB=0.47µF, fin =120Hz - 85 - dB Crosstalk Channel Separation fin =1kHz, CB=0.47µF, - 95 - dB HP/LINE Input Separation fin =1kHz, CB=0.47µF, - 80 - dB S/N Signal to Noise Ratio PO=1.1W, RL=8Ω , A_weighting - 105 - dB Operating Characteristics, BTL mode VDD=5V, TA=25°C, RL=4W, Gain=6dB, (Unless otherwise noted) APA2030 Symbol Parameter Test Conditions Min. Typ. Max. Unit THD+N=10%, fin=1kHz, RL=32Ω - 110 - mW PO Maximum Output Power THD+N =1%, fin=1kHz, RL=32Ω - 90 - mW THD+N Total Harmonic Distortion Plus Noise PO=75mW, RL=32Ω , fin=1kHz - 0.03 - % PSRR Power Ripple Rejection Ratio VIN=0.2Vrms, RL=32Ω , CB=0.47µF, fin =120, - 55 - dB SE/BTL Attenuation - 80 - dB Operating Characteristics, SE mode ( for APA2030 only) VDD=5V, TA=25°C, RL=32W, Gain=4, 1dB, (Unless otherwise noted)

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw5 APA2030/2031 Electrical Characteristics (Cont.) APA2030 Symbol Parameter Test Conditions Min. Typ. Max. Unit Crosstalk Channel Separation fin =1kHz, CB=0.47µF, - 65 - dB HP/LINE Input Separation fin =1kHz, CB=0.47µF, BTL - 80 - dB S/N Signal to Noise Ratio PO=75mW, RL=32Ω , A_weighting - 100 - dB Operating Characteristics, SE mode ( for APA2030 only) VDD=5V, TA=25°C, RL=32W, Gain=4, 1dB, (Unless otherwise noted)

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw6 APA2030/2031 THD+N (%) Output Power (W) Output Power (mW) THD+N (%)Crosstalk (dB) THD+N (%) THD+N vs. Output Power Output Power (W) Output Power (W) THD+N vs. Output Power THD+N vs. Output Power Crosstalk vs. Output Power THD+N (%) Output Power (W) THD+N vs. Output Power THD+N (%) THD+N vs. Output Power Output Power (W) Typical Operating Characteristics 0.01 0.1 0 30.5 1 1.5 2 2.5 VDD=5V AV=6dB fin=1kHz BTL RL=8Ω RL=4Ω RL=3Ω 0.01 0.1 10m 5100m 1 VDD=5V AV=6dB RL=3Ω BTL fin=15kHz fin=1kHz fin=30Hz 0.01 0.1 10m 5100m 1 2 VDD=5V AV=15.6dB RL=3Ω BTL fin=15kHz fin=1kHz fin=30Hz 0.01 0.1 10m 5100m 1 2 VDD=5V AV=15.6dB RL=4Ω BTL fin=15kHz fin=1kHz fin=30Hz 0.01 0.1 0 25050 100 150 200 VDD=5V AV=4.1dB fin=kHz COUT=330µF SE RL=32Ω RL=16Ω 0.01 0.1 10m 5100m 1 2 VDD=5V AV=6dB RL=4Ω BTL fin=15kHz fin=1kHz fin=30Hz

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw7 APA2030/2031 THD+N (%) Output Power (W) Output Power (W) THD+N (%)THD+N (%) THD+N (%) THD+N vs. Output Power Output Power (W) Output Power (W) THD+N vs. Output Power THD+N vs. Output Power THD+N vs. Output Power THD+N (%) Frequency (Hz) THD+N vs. Frequency THD+N (%) THD+N vs. Frequency Frequency (Hz) Typical Operating Characteristics (Cont.) 0.01 0.1 10m 5100m 1 2 VDD=5V AV=6dB RL=8Ω BTL fin=15kHz fin=1kHz fin=30Hz 0.01 0.1 10m 5100m 1 2 VDD=5V AV=15.6dB RL=8Ω BTL fin=15kHz fin=1kHz fin=30Hz 0.01 0.1 10m 300m50m 100m 200m VDD=5V AV=4.1dB RL=16Ω COUT=1000µF BTL fin=15kHz fin=1kHz fin=30Hz 0.01 0.1 10m 300m50m 100m 200m VDD=5V AV=4.1dB RL=32Ω COUT=1000µf BTL fin=15kHz fin=1kHz fin=30Hz 0.01 0.1 20 20k100 1k 10k VDD=5V AV=6dB RL=3Ω BTL PO=1.75W PO=1W 0.01 0.1 20 20k100 1k 10k VDD=5V PO=1.75W RL=3Ω BTL AV=15.6dB AV=6dB

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw8 APA2030/2031 THD+N (%) Frequency (Hz) Frequency (Hz) THD+N (%)THD+N (%) THD+N (%) THD+N vs. Frequency Frequency (Hz) Frequency (Hz) THD+N vs. Frequency THD+N vs. Frequency THD+N vs. Frequency THD+N (%) Frequency (Hz) THD+N vs. Frequency THD+N (%) THD+N vs. Frequency Frequency (Hz) Typical Operating Characteristics (Cont.) 0.01 0.1 20 20k100 1k 10k VDD=5V AV=6dB RL=4Ω BTL PO=1.5W PO=0.75W 0.01 0.1 20 20k100 1k 10k VDD=5V PO=1.5W RL=4Ω BTL AV=15.6dB AV=6dB 0.01 0.1 20 20k100 1k 10k VDD=5V AV=6dB RL=8Ω BTL PO=1W PO=0.5W 0.01 0.1 20 20k100 1k 10k VDD=5V AV=4.1dB RL=16Ω COUT=1000µF SE PO=75mW PO=150mW 0.01 0.1 20 20k100 1k 10k VDD=5V AV=4.1dB RL=32Ω COUT=1000µF SE PO=25mW PO=75mW 0.01 0.1 20 20k100 1k 10k VDD=5V PO=1W RL=8Ω BTL AV=6dB AV=15.6dB

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw9 APA2030/2031 Gain (dB) Frequency (Hz) Frequency (Hz) Gain (dB)Gain (dB) Gain (dB) Frequency Response Frequency (Hz) Frequency (Hz) Frequency Response Frequency Response Frequency Response Crosstalk (dB) Frequency (Hz) Crosstalk vs. Frequency Output Noise Voltage (Vrms) Crosstalk vs. Frequency Frequency (Hz) Typical Operating Characteristics (Cont.) Phase (deg) Phase (deg) Phase (deg) Phase (deg) +120 +240 +130 +140 +150 +160 +170 +180 +190 +200 +210 +220 +230 -10 10 200k100 1k 10k 100k VDD=5V RL=4Ω AV=6dB PO=1W BTL Gain Phase +120 +270 +130 +140 +150 +160 +170 +180 +190 +200 +210 +220 +230 +240 +250 +260 +20 +10 +12 +14 +16 +18 10 200k100 1k 10k 100k VDD=5V RL=4Ω AV=15.6dB PO=1W BTL Gain Phase +120 +270 +130 +140 +150 +160 +170 +180 +190 +200 +210 +220 +230 +240 +250 +260 +10 10 200k100 1k 10k 100k VDD=5V RL=8Ω AV=10dB PO=0.5W BTL Gain Phase +100 +300 +120 +140 +160 +180 +200 +220 +240 +260 +280 10 200k100 1k 10k 100k VDD=5V RL=32Ω AV=4.1dB VIN=1V SE Gain Phase -140 -120 -100 -80 -60 -40 -20 20 20k100 1k 10k T TT VDD=5V RL=4Ω AV=6dB PO=1.5W BTL Left to Right Right to Left -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD=5V RL=32Ω AV=4.1dB VIN=1V COUT=330µF SE Left to Right Right to Left

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw10 APA2030/2031 PSRR(dB) Frequency (Hz) Frequency (Hz) PSRR(dB)Output Noise Voltage (µV) Output Noise Voltage (µV) PSRR vs. Frequency Frequency (Hz) Frequency (Hz) PSRR vs. Frequency Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency Supply Current (mA) Supply Voltage (V) Supply Current vs. Supply Voltage Power Dissipation (W) Power Dissipation vs. Output Power Output Power (W) Typical Operating Characteristics (Cont.) No Load BTL SE 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VDD=5V BTL RL=3Ω RL=4Ω RL=8Ω -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD=5V RL=4Ω CB=0.47µF BTL -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k VDD=5V RL=32Ω CB=0.47µF SE 100 20 20k100 1k 10k VDD=5V RL=32Ω AV=4.1dB SE A-Weighting Filter BW<22kHz 100 20 20k100 1k 10k VDD=5V RL=4Ω AV=6dB BTL A-Weighting Filter BW<22kHz

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw11 APA2030/2031 Power Dissipation (mW) Output Power (mW) Power Dissipation vs. Output Power Typical Operating Characteristics (Cont.) 100 120 140 160 180 200 0 50 100 150 200 250 300 VDD=5V SE RL=32Ω RL=16Ω RL=8Ω Pin Description PIN TSSOP-24P NO. NAME CONFIG. FUNCTION 1,12,13,24 GND - Ground connection, connected to thermal pad. 2 GAIN0 I/P Input signal for internal gain setting. 3 GAIN1 I/P Input signal for internal gain setting. 4 LOUT+ O/P Left channel positive output in BTL mode and SE mode. 5 LLINEIN I/P Left channel line input terminal, selected when HP/LINE is held low. 23 RLINEIN I/P Right channel line input terminal, selected when HP/LINE is held low. 6 LHPIN O/P Left channel headphone input terminal, selected when HP/LINE is held high. 7,18 PVDD - Supply voltage only for power amplifier. 8 RIN+ I/P Right channel positive signal input when differential signal is accepted. 9 LOUT- O/P Left channel negative output in BTL mode and high impedance in SE mode. 10 LIN+ I/P Left channel positive signal input when differential signal is accepted. 11 BYPASS - Bypass voltage. 14 PCBEEP I/P PC-beep signal input. 15 SE/BTL I/P Output mode control input pin, high for SE output mode and low for BTL mode. 16 ROUT- O/P Right channel negative output in BTL mode and high impedance in SE mode. 17 HP/LINE I/P Multi-input selection input, headphone mode when held high, line-in mode when held low. 19 VDD - Supply voltage for internal circuit excepting power amplifier. 20 RHPIN I/P Right channel headphone input terminal, selected when HP/LINE is held high. 21 ROUT+ O/P Right channel positive output in BTL mode and SE mode. 22 SHUTDOWN I/P It will be into shutdown mode when pull low. 23 RLINEIN I/P Right channel line input terminal, selected when HP/LINE is held low. APA2030

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw12 APA2030/2031 Pin Description (Cont.) APA2031 PIN NO. TSSOP-20P TQFN3x3-16 NAME CONFIG. FUNCTION 1,11,13,20 2,11 GND - Ground connection, connected to thermal pad. 2 3 GAIN0 I/P Input signal for internal gain setting. 3 4 GAIN1 I/P Input signal for internal gain setting. 4 5 LOUT+ O/P Left channel positive output. 5 6 LIN- I/P Left channel negative audio signal input. 6,15 7 PVDD - Supply voltage only for power amplifier. 7 8 RIN+ I/P Right channel positive audio signal input. 8 12 LOUT- O/P Left channel negative output. 9 9 LIN+ I/P Left channel positive audio signal input. 10 10 BYPASS - Bypass voltage. 12 - NC - No connection. 14 13 ROUT- O/P Right channel negative output. 16 14 VDD - Supply voltage for internal circuit excepting power amplifier. 17 15 RIN- I/P Right channel negative audio signal input. 18 16 ROUT+ O/P Right channel positive output. 19 1 SHUTDOWN I/P It will be into shutdown mode when pull low. HP/ LINE SE/BTL SHUTDOWN PCBEEP Operating mode X X L Disable Shutdown mode L L H Disable Line input, BTL out H L H Disable HP input, BTL out L H H Disable Line input, SE out H H H Disable HP input, SE out X X X Enable PC-BEEP input, BTL out Control Input Table ( for APA2030 only) GAIN0 GAIN1 Ri Rf AV 0 0 90kΩ 90kΩ 6dB 0 1 69kΩ 111kΩ 10dB 1 0 42kΩ 138kΩ 15.6dB 1 1 25.7kΩ 154.3kΩ 21.6dB Gain Setting Table (for both APA2030 and APA2031)

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw13 APA2030/2031 Block Diagram Shutdown ckt HP/LINE MUX MUX SE/BTL LOUT+ LOUT- ROUT+ ROUT- LLINEIN RLINEIN LHPIN RHPIN HP/LINE SE/BTL SHUTDOWN BYPASS PC-BEEP ckt PCBEEP Vbias Gain selectable Vbias LIN+ RIN+ GIAN1 GAIN0 APA2030_Block

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw14 APA2030/2031 Typical Application Circuit (for APA2030 using SE input signal) 4Ω Ring Headphone Jack Sleeve Control Pin Tip SE/BTL Signal 0.47µF 0.47µF 220µF 220µF 1kΩ 1kΩ R-LINE R-HP VDD 100kΩ Shutdown Signal Shutdown ckt HP/LINE MUX MUX SE/BTL LOUT+ LOUT- ROUT+ ROUT LLINEIN RLINEIN LHPIN RHPIN HP/LINE SE/BTL BYPASS PC-BEEP ckt PCBEEP Vbias Gain selectable Vbias LIN+ RIN+ 0.47µF BEEP Signal 0.47µF 0.47µFL-LINE L-HP 0.47µF VDD PVDDGND 0.47µF 0.47µF GAIN0 GAIN1 100µF0.1µF APA2030AppCk t SHUTDOWN HP/LINE Control Signal 100kΩ SE/BTL Signal VDD APA2030

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw15 APA2030/2031 APA2031 Typical Application Circuit (Cont.) (for APA2031 using SE input signal) Shutdown Signal Shutdown ckt LOUT+ LOUT- ROUT+ ROUT- LIN- RIN- SHUTDOWN BYPASS Vbias Gain selectable Vbias LIN+ RIN+ L-INPUT 0.47 µF VDD VDD PVDDGND 0.47µF GAIN0 GAIN1 0.47µF 0.47µF 0.47 µF R-INPUT 100 µF0.1µF

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw17 APA2030/2031 Application Information (Cont.) the OUT- amplifier is shutdown and causes the speaker to mute. And then, the OUT+ amplifier drives through the output capacitor (CO) into the headphone jack. Output SE/BTL Operation (for APA2030 only) (Cont.) When there is no headphone plugged into the system, the contact pin of the headphone jack is connected from the signal pin, the voltage divider is set up by resistors 100kΩ and 1kΩ . Resistor 1kΩ then pulls low the SE/BTL pin, enabling the BTL function. Input HP/LINE Operation (for APA2030 only) APA2030 amplifier has two separated inputs for each of the left and right stereo channels. An internal multiplexer selects which input will be connected to the amplifier based on the state of the HP/LINE pin on the IC.

  • To select the line inputs, set HP/LINE pin tied to low level
  • To enable the headphone inputs, set HP/ LINE pin tied to high level Refer to the application circuit, the voltage divider of 100kΩ and 1kΩ sets the voltage at the HP/LINE pin to be approximately 50mV when there are no headphones plugged into the system. This logic low voltage at the HP/LINE pin enables the APA2030 and places it LINE input mode operation. When a set of headphones is plugged into the system, the contact pin of the headphone jack is disconnected from the signal pin, interrupting the voltage divider set up by resistors 100 kΩ . Resistor 100 kΩ then pulls-up the HP/LINE pin, enabling the headphone input function. Differential Input Operation The APA2030/1 can accept the differential input signal and improve the CMRR (Common Mode Rejection Ratio). For example, when applying differential input signals to APA2031, connect positive input signals to the IN+ (LIN+ and RIN+) of APA2031 and negative input signals to the IN- (LIN- and RIN-) of APA2031. When input signals are single-end, just connect IN+ (LIN+ and RIN+) to ground via a capacitor. Input Resistance, Ri The APA2030/1 provides four gain setting decided by GAIN0 and GAIN1 input pins in differential mode and it becomes 4.1dB fixed gain when SE mode is selected (for APA2030). In Table 1, according to the BTL operation, internal resistors Ri and Rf set the gain for each audio input of the APA2030/1. GAIN0 GAIN1 Ri Rf SE/BTL AV 0 0 90kΩ 90kΩ 0 6dB 0 1 69kΩ 111kΩ 0 10dB 1 0 42kΩ 138kΩ 0 15.6dB 1 1 25.7kΩ 154.3kΩ 0 21.6dB X X 69kΩ 111kΩ 1 4.1dB Table 1: The close loop gain setting resistance Ri/Rf BTL mode operation brings about the factor 2 in the gain equation due to the inverting amplifier mirroring the volt- age swing across the load. The input resistance has wide variation (+/-10%) caused by manufacturing. Input Capacitor, Ci In the typical application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri form a high-pass filter with the corner frequency determined in the following equation: The value of Ci must be considered carefully because it directly affects the low frequency performance of the circuit. Consider the example where Ri is 90 kΩ when 6dB gain is set and the specification calls for a flat bass response down to 40Hz. The equation is reconfigured as below: 1C ci i When the variation of input resistance (R i) is considered, the value of Ci is 0.04µF. Therefore, a value in the range from 0.1µF to 1.0µF would be chosen. 1f i(min)i )highpass(c ×π=

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw18 APA2030/2031 Application Information (Cont.) Input Capacitor, Ci (Cont.) A further consideration for this capacitor is the leakage path from the input source through the input network (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic ca- pacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifiers’ input in most applications becasue the DC level of the amplifiers’ inputs is held at VDD/2. Please note that it is important to confirm the capacitor polarity in the application. Effective Bypass Capacitor, Cbypass As to any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitor located on both the bypass and power sup- ply pins should be as close to the device as possible. The effect of a larger half supply bypass cap acitor im- proves PSRR due to increased half-supply stability. Typi- cal applications employ a 5V regulator with 1.0 µF and a 0.1µF bypass capacitors which aid in supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA2030/1. The selection of bypass capacitors, especially C B, is thus dependent upon de- sired PSRR requirements, click and pop performance. To avoid the start-up pop noise occurred, the bypass volt- age should rise slower than the input bias voltage and the relationship shown in equation should be maintained. The capacitor is fed from a 250k Ω source inside the amplifier. Bypass capacitor, C B, values of 3.3 µF to 10µF ceramic or tantalum low-ESR capacitors are recom- mended for the best THD+N and noise performance. The bypass capacitance also affects the start-up time. It is determined in the following equation: Output Coupling Capacitor, Cc (for APA2030 only) In the typical single-supply SE configuration, an output coupling capacitor (Cc) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high- pass filter governed by the following equation. For example, a 330 µF capacitor with an 8 Ω speaker would attenuate low frequencies below 60.6Hz. Large values of C C are required to pass low frequencies into the load. Power Supply Decoupling, CS The APA2030/1 is a high-performance CMOS audio am- plifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) is as low as possible. Power supply decoupling also prevents the oscillations being caused by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two differ- ent types of capacitors that targets on different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1µF placed as close as possible to the device VDD lead works best. For filtering lower-frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near the audio power amplifier is recommended. Shutdown Function In order to reduce power consumption when not in use, the APA2030/1 contains a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the SHUTDOWN pin. The trigger point between a logic high and logic low level is typically 2.0V. It is better to switch between the ground and the supply VDD to provide maxi- mum device performance. 1f cL )highpass(c k250C ibypass Ω×<<Ω×

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw19 APA2030/2031 Application Information (Cont.) Shutdown Function (Cont.) By switching the SHUTDOWN pin to low, the amplifier enters a low-current state, I DD<50mA. The APA2030 is in shutdown mode, except PC-BEEP detect circuit. On nor- mal operating, SHUTDOWN pin is pulled to high level to keep the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a definite voltage to avoid unwanted state changing. PC-BEEP Detection ( for APA2030 only) The APA2030 integrates a PC-BEEP detect circuit for NOTEBOOK PC using. Over 1Vpp amplitude PC-BEEP signal with the rising time/falling time under 1µs/V should be provided to trigger the APA2030 into PC-BEEP mode. The input impedance is 100kΩ and the bias voltage on PC-BEEP input pin is 2.5V. Therefore, the voltage level of PC-BEEP signal should be higher than 3V and lower than 2V to into PCBEEP mode correctly. When PC-BEEP signal drives to PC-BEEP input pin, the PC-BEEP mode will be active. When chip in the PC-BEEP mode, the APA2030 will be forced to be in BTL mode and the internal gain is fixed as -10dB. The PC-BEEP signal turns to be the amplifier input signal and plays on the speaker without coupling capacitor. If the amplifier is in the shutdown mode, it will be out of shutdown mode whenever PC-BEEP mode enabled. The APA2030 will return to previous setting when it is out of PC-BEEP mode. Optimizing Depop Circuitry Circuitry has been included in the APA2030/1 to minimize the amount of popping noise at power-up and when com- ing out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to elimi- nate clicks and pops, all capacitors must be fully dis- charged before turn-on. Rapid on/off switching of the de- vice or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops. (Refer to Effective Bypass Capacitance) The bypass voltage should rise slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of CB can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of CB, turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship be- tween the size of CB and the turn-on time. In a SE (for APA2030) configuration, the output coupling capacitor, CC, is of particular concern. This capacitor dis- charges through the internal 10kΩ resistors. Depending on the size of CC, the time constant can be relatively large. To reduce transients in SE mode, an external 1kΩ resis- tor can be placed in parallel with the internal 10kΩ resistor. The tradeoff for using this resistor is an increase in qui- escent current. In the cases, choosing a small value of C i in the range of 0.33µF to 1µF, CB being equal to 0.47µF and an external 1kΩ resistor should be placed in parallel with the inter- nal 10k Ω resistor, and it should produce a virtually clickless and popless turn-on. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. Hence, it is ad- vantageous to use low-gain configurations. BTL Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power sup- ply to the power delivered to the load. The following equa- tions are the basis for calculating amplifier efficiency. PEfficiency SUP O Where Efficiency of a BTL configuration R V2VIVP VrmsV VV R rmsVrmsVP L P DD)AVG(DDDDSUP P o L PP L oo O π ×=×= ×=×= V R V2V )R2 VV( P P DD P L P DD L PP SUP O π=

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw20 APA2030/2031 Po (W) Efficiency (%) IDD(A) VPP(V) PD (W) Application Information (Cont.) BTL Amplifier Efficiency (Cont.) Table 2 calculates efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system with 8Ω loads and a 5V supply, the maximum draw on the power supply is almost 3W. **High peak voltages cause the THD+N to increase. Table 2: Efficiency vs. Output Power in 5V/8W BTL Sys- tems A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to the utmost advantage when possible. Note that in equation, VDD is in the dominator. This indicates that as VDD goes down, efficiency goes up. In other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. Power Dissipation Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. In equation11, it states that the maximum power dissipa- tion point for a SE mode operates at a given supply volt- age and drives a specified load. In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus, the maximum power dis- sipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. Since the APA2030/1 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both of equations depending on the mode of operation. Even with this substantial increase in power dissipation, the APA2030/1 does not require extra heatsink. The power dissipation from equation12, assuming a 5V-power sup- ply and an 8W load, must not be greater than the power dissipation that results from the equation 13: For TSSOP-24P (APA2030), TSSOP-20P and TQFN3x3- 16 (APA2031) packages with and without thermal pad, the thermal resistance ( θ JA) is equal to 45 oC/W, 48 oC/W and 55oC/W respectively. Since the maximum junction temperature (TJ,MAX) of APA2030/1 is 150oC and the ambient temperature (TA) is defined by the power system design, the maximum power dissipation which the IC package is able to handle can be obtained from equation12. Once the power dissipation is greater than the maximum limit (PD,MAX), either the supply voltage (VDD) must be decreased, the load imped- ance (RL) must be increased or the ambient temperature should be reduced. Thermal Pad Consideration The thermal pad must be connected to the ground. The package with thermal pad of the APA2030/1 requires spe- cial attention on thermal design. If the thermal design issues are not properly addressed, the APA2030/1 4 Ω will go into thermal shutdown when driving a 4 Ω load. The thermal pad on the bottom of the APA2030/1 should be soldered down to a copper pad on the circuit board. Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on the top surface of the circuit board, 8 to 10 vias of 13 mil or smaller in diameter should be used to thermally couple the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder filled. The copper plane is used to conduct heat away from the thermal pad should be as large as practical. VP :mode SE 2DD D.MAX π V4P :mode BLT 2DD D.MAX π AMAX.J D.MAX θ If the ambient temperature is higher than 25°C, a larger copper plane or forced-air cooling will be required to keep the APA2030/1 junction temperature below the thermal shutdown temperature (150°C).

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw21 APA2030/2031 Application Information (Cont.) Thermal Pad Consideration (Cont.) In higher ambient temperature, higher airflow rate and/or larger copper area will be required to keep the IC out of thermal shutdown. Thermal Consideration Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. To calculate maximum ambient temperatures, first con- sideration is that the numbers from the Power Dissipa- tion vs. Output Power graphs (Page 9 and 10 ) are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given θ JA, the maximum allowable junction temperature (T J,MAX), and the total internal dissipation (P D), the maximum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the APA2030/1 is 150oC. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graphs. (Page 9 and 10) 150 - 45(0.8x2) = 78oC (TSSOP-24P) 150 - 48(0.8x2) = 73.2oC (TSSOP-20P) 150 - 55(0.8x2) = 62oC (TQFN3x3-16) The APA2030/1 is designed with a thermal shutdown pro- tection that turns the device off when the junction tem- perature surpasses 150 oC to prevent the IC from damages. Recommended Minimum Footprint 0.35mm 0.65mm Via diameter =0.3mm X8 Via diameter =0.3mm X10 Ground plane for ThermalPAD 1.7mm 1.7mm4.7mm 3mm 4.5mm Exposed for thermal PAD connected TSSOP-24P 0.35mm 0.65mm Via diameter =0.3mm X8Via diameter =0.3mm X6 Ground plane for ThermalPAD 1.7mm 1.7mm4.7mm 3mm Exposed for thermal PAD connected 4.0mm TSSOP-20P

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw22 APA2030/2031 Application Information (Cont.) Recommended Minimum Footprint 0.5mm 0.24mm 0.508mm 0.162mm 1.66mm 3mm * Just Recommend 3mm 1.66 mm 0.5mm * Via diameter = 0.3mm X 5

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw23 APA2030/2031

Package Information

TSSOP-24P (APA2030) Note : 1. Followed from JEDEC MO-153 ADT. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. S Y M B O L MIN. MAX. 1.20 0.05 0.09 0.20 7.70 7.90 0.15 A c D E e L MILLIMETERS b 0.19 0.30

0.65 BSC

0.45 0.75

0.026 BSC

MIN. MAX. INCHES 0.047 0.002 0.007 0.012 0.004 0.008 0.303 0.311 0.169 0.177 0.018 0.030 0.006 A2 0.80 1.05 4.30 4.50E1 0.031 0.041 3.50D1 0.138 E2 2.50 0.098 5.00 3.50 0.197 0.138 INCHES 8o 0o 8o0o 0VIEW A 0.25 SEATING PLANE GAUGE PLANE SEE VIEW A E b c A e A1 L E2EXPOSED PAD D 6.20 6.60 0.244 0.260

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw24 APA2030/2031 TSSOP-20P (APA2031) Note : 1. Follow JEDEC MO-153 ACT. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. 0VIEW A 0.25 SEATING PLANE GAUGE PLANE SEE VIEW A E b c A e L E2EXPOSE D PAD D SYMBOL MIN. MAX. 1.20 0.05 0.09 0.20 6.40 6.60 0.15 A c D E e L MILLIMETERS b 0.19 0.30 0.45 0.75 MIN. MAX. INCHES 0.047 0.002 0.007 0.012 0.004 0.008 0.252 0.260 0.169 0.177 0.018 0.030 0.006 A2 0.80 1.05 4.30 4.50E1 0.031 0.041 3.00D1 0.118 E2 2.50 0.098 4.50 3.50 0.177 0.138 INCHES 8o 0o 8o0o 6.20 6.40 0.244 0.260

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw25 APA2030/2031 TQFN3x3-16 (APA2031) Note : Follow JEDEC MO-220 WEED-4. D E Pin 1 A b e Pin 1 Corner k S Y M B O L MIN. MAX. 0.80 0.00 0.18 0.30 1.50 1.80 0.05 1.50 A b D E e L MILLIMETERS A3 0.20 REF TQFN3x3-16 0.30 0.50 1.80

0.008 REF

MIN. MAX. INCHES 0.031 0.000 0.007 0.012 0.059 0.071 0.059 0.012 0.020 0.70 0.071 0.028 0.002 0.50 BSC 0.020 BSC K 0.20 0.008 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw26 APA2030/2031 Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 TSSOP-24P Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 TSSOP-20P Application A H T1 C d D W E1 F 330±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 TQFN3x3-16 (mm) Carrier Tape & Reel Dimensions A AB W F T P0OD0 B SECTION B-B SECTION A-A OD1 H A d

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw27 APA2030/2031 Package Type Unit Quantity TSSOP-24P Tape & Reel 2000 TSSOP-20P Tape & Reel 2000 TQFN3x3-16 Tape & Reel 3000 Taping Direction Information TSSOP-20P USER DIRECTION OF FEED TSSOP-24P USER DIRECTION OF FEED Devices Per Unit

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw28 APA2030/2031 Classification Profile Taping Direction Information TQFN3x3-16 USER DIRECTION OF FEED

Copyright  ANPEC Electronics Corp. (Tsmax to TP) 3 °C/second max. 3°C/second max. Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. Time 25°C to peak temperature 6 minutes max. 8 minutes max.

  • Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.

** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 2. Pb-free Process – Classification Temperatures (Tc) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

Copyright  ANPEC Electronics Corp. Rev. A.10 - Aug., 2013 www.anpec.com.tw30 APA2030/2031 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838