APA0715 ANPEC | Alldatasheet

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Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw1 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. 3W Mono Fully Differential Audio Power Amplifier APA0715 The APA0715 is a Mono, fully differential Class-AB audio amplifier which can operate with supply voltage from 2.4V to 5V and is available in a MSOP8, MSOP8P, or TDFN3x3- 8 package. High PSRR and fully differential architecture increase im- munity to noise and RF rectification. In addition to these features, a short startup time and small package size make the APA0715 an ideal choice for Mobil Phones and Portable Devices . The APA0715 also integrates the de-pop circuitry that re- duces the pops and click noises during power on/off and shutdown mode operation. Both Thermal and over-cur- rent protections are integrated to avoid the IC being de- stroyed by over temperature and short-circuit. The APA0715 is capable of driving 3W at 5V into 3Ω speaker. Features General Description

Applications

  • Mobil Phones
  • Portable Devices
  • Operating Voltage: 2.4V~5.5V
  • Fully Differential Class-AB Amplifier
  • High PSRR and Excellent RF Rectification Immunity
  • Low Crosstalk
  • 3W Output Power into 3W Load at VDD=5V
  • Thermal and Over-Current Protections
  • Low Supply Current :1.5mA Typical
  • Space Saving Package -MSOP-8 -MSOP-8P -TDFN3x3-8
  • Lead Free and Green Devices Available (RoHS Compliant) Simplified Application Circuit Pin Configuration BYPASS 2 7 GND INP 3 INN 4

6 VDD

5 OUTP

8 OUTNSD 1

7 GND

8 OUTN

=Thermal Pad (connected the Thermal Pad to GND plane for better heat dissipation) APA0715 Input Speaker LINN LINP LOUTP LOUTN

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw2 APA0715 Symbol Parameter Rating Unit VDD Supply Voltage -0.3 to 6 V Input Voltage (INN, INP, SD to GND) -0.3 to 6 V VIN Input Voltage (OUTN, OUTP to GND) -0.3 to VDD +0.3 V TJ Maximum Junction Temperature 150 ο C TSTG Storage Temperature Range -65 to +150 ο C TSDR Maximum Soldering Temperature Range, 10 Seconds 260 ο C PD Power Dissipation Internally Limited W Ordering and Marking Information Absolute Maximum Ratings (Note 1) Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD- 020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. APA0715 Handling Code Temperature Range Package Code XXXXX - Date Code Assembly Material APA0715 X : APA0715 QB : APA0715 XA : XXXXX - Date Code XXXXX - Date Code A0715 XXX XX APA 0715 XXXXX Package Code X : MSOP-8 XA : MSOP-8P QB : TDFN3x3-8 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device A0715 XXX XX

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw3 APA0715 Symbol Parameter Range Unit VDD Supply Voltage 2.4 ~ 5.5 V VIH High Level Threshold Voltage SD 1.8 ~ VDD V VIL Low Level Threshold Voltage SD 0 ~ 0.35 V VIC Common Mode Input Voltage 0.5 ~ VDD-0.5 Operating Ambient Temperature Range -40 ~ 85 ο C Operating Junction Temperature Range -40 ~ 125 ο C Speaker Resistance 3 ~ Ω Thermal Characteristics (Note 2,3) Symbol Parameter Typical Value Unit θ JA Thermal Resistance -Junction to Ambient MSOP-8 MSOP-8P TDFN3x3-8 200 ο C /W θ JC Thermal Resistance -Junction to Case MSOP-8P TDFN3x3-8 ο C /W Recommended Operating Conditions APA0715 Symbol Parameter Test Conditions Min. Typ. Max. Unit IDD Supply Current - 1.5 3 mA ISD Shutdown Current SD = 0V - - 5 µA II Input Current SD - 0.1 - µA TSTART-UP Start-Up Time from End of Shutdown Cb=0.22µF - 50 - ms RSD Resistance from Shutdown to GND 90 100 110 kΩ VDD=5V, TA=25°C RL = 3Ω - 2.4 - RL = 4Ω - 2.1 - THD+N = 1% RL = 8Ω 1 1.3 - RL = 3Ω - 3 - RL = 4Ω - 2.6 - PO Output Power THD+N = 10% fin = 1kHz RL = 8Ω - 1.6 - W THD+N Total Harmonic Distortion Pulse Noise fin = 1kHz RL = 8Ω PSRR Power Supply Rejection Ratio Cb= 0.22µF, RL = 8Ω , VRR=0.2VPP, fin = 217Hz - 75 - dB

Electrical Characteristics

VDD=5V, GND=0V, AV=1V/V, TA= 25oC (unless otherwise noted) Note 2: Please refer to “ Layout Recommendation”, the Thermal Pad on the bottom of the IC should soldered directly to the PCB’s ThermalPad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz copper thickness . Note 3: The case temperature is measured at the center of the Thermal Pad on the underside of the MSOP-8P and TDFN3x3-8 package.

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw4 APA0715 Electrical Characteristics (Cont.) VDD=5V, GND=0V, TA= 25o C (unless otherwise noted) APA0715 Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD=5V, TA=25°C (CONT.) CMRR Common-Mode Rejection Ratio Cb= 0.22µF, RL = 8Ω , VIC=0.2VPP, fin = 217Hz - 85 - dB S/N Signal to Noise Ratio With A-weighting Filter PO = 1.3W, RL = 8Ω - 112 - dB VOS Output Offset Voltage RL = 8Ω - 5 20 mV Vn Noise Output Voltage Cb= 0.22µF, With A-weighting Filter - 8 - µV (rms) VDD=3.6V, TA=25°C RL = 3Ω - 1.2 - RL = 4Ω - 1 - THD+N = 1% RL = 8Ω - 0.65 - RL = 3Ω - 1.5 - RL = 4Ω - 1.3 - PO Output Power THD+N = 10% fin = 1kHz RL = 8Ω - 0.8 - W THD+N Total Harmonic Distortion Pulse Noise fin = 1kHz RL = 8Ω PSRR Power Supply Rejection Ratio Cb= 0.22µF, RL = 8Ω , VRR=0.2VPP, fin = 217Hz - 85 - CMRR Common-Mode Rejection Ratio Cb= 0.22µF, RL = 8Ω , VIC=0.2VPP, fin = 217Hz - 75 - S/N Signal to Noise Ratio With A-weighting Filter PO = 0.65W, RL = 8Ω - 110 - dB VOS Output Offset Voltage RL = 8Ω - 5 20 mV Vn Noise Output Voltage Cb= 0.22µF, With A-weighting Filter - 7 - µV (rms) VDD=2.4V, TA=25°C RL = 3Ω - 0. 5 - RL = 4Ω - 0.45 - THD+N = 1% RL = 8Ω - 0.3 - RL = 3Ω - 0.7 - RL = 4Ω - 0.6 - PO Output Power THD+N = 10% fin = 1kHz RL = 8Ω - 0.35 - W THD+N Total Harmonic Distortion Pulse Noise fin = 1kHz PO = 0.2W, RL = 8Ω - 0.08 - % PSRR Power Supply Rejection Ratio Cb= 0.22µF, RL = 8Ω , VRR=0.2VPP, fin = 217Hz - 80 - CMRR Common-Mode Rejection Ratio Cb= 0.22µF, RL = 8Ω , VIC=0.2VPP, fin = 217Hz - 65 - S/N Signal to Noise Ratio With A-weighting Filter PO = 0.3W, RL = 8Ω - 106 - dB VOS Output Offset Voltage RL = 8Ω - 5 20 mV Vn Noise Output Voltage Cb= 0.22µF, With A-weighting Filter - 7 - µV (rms)

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw5 APA0715 Typical Operating Characteristics 10m 5100m 1 THD+N (%) Output Power (W) THD+N vs. Output Power VDD=2.4V VDD=3.6V VDD=5.0V RL=3Ω fin=1kHz Ci=0.22µF AV=1V/V BW<80kHz 0.01 0.1 20 20k100 1k 10k THD+N vs. Frequency Frequency (Hz) THD+N (%) PO=25mW PO=450mW PO=250mW VDD=3.6V RL=8Ω Ci=0.22µF AV=1V/V BW<80kHz 0.01 0.1 0.01 0.1 10m 3100m 1 THD+N (%) Output Power (W) THD+N vs. Output Power VDD=2.4V VDD=3.6V VDD=5.0V RL=8Ω fin=1kHz Ci=0.22µF AV=1V/V BW<80kHz 20 20k100 1k 10k THD+N vs. Frequency Frequency (Hz) THD+N (%) PO=0.9W PO=25mW VDD=5.0V RL=8Ω Ci=0.22µF AV=1V/V BW<80kHz PO=250mW 0.01 0.1 20 20k100 1k 10k THD+N vs. Frequency Frequency (Hz) THD+N (%) PO=75mW PO=15mW VDD=2.4V RL=8Ω Ci=0.22µF AV=12dB BW<80kHz PO=350mW 0.01 0.1 10m 5100m 1 THD+N (%) Output Power (W) THD+N vs. Output Power VDD=2.4V VDD=3.6V VDD=5.0V RL=4Ω fin=1kHz Ci=0.22µF AV=1V/V BW<80kHz 0.01 0.1

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw6 APA0715 Typical Operating Characteristics (Cont.) RL=8Ω ,THD+N=10% RL=3Ω ,THD+N=1% RL=4Ω ,THD+N=10% RL=3Ω ,THD+N=10% RL=8Ω ,THD+N=1% 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Output Power (W) Supply Volume (V) Output Power vs. Supply Voltage fin=1kHz AV=1V/V RL=4Ω ,THD+N=1% 3 8 13 18 23 28 32 Output Power vs. Load Resistance Output Power (W) Load Resistance (Ω ) fin=1kHz AV=1V/V VDD=2.4V,THD+N=10% VDD=2.4V,THD+N=1% VDD=3.6V,THD+N=1% VDD=3.6V,THD+N=10% VDD=5V,THD+N=10% VDD=5V,THD+N=1% 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Power Dissipation vs. Output Power Output Power (W) Power Dissipation (W) VDD=5V fin=1kHz AV=1V/V RL=3Ω RL=4Ω RL=8Ω 0.0 0.5 1.0 1.5 2.0 Power Dissipation vs. Output Power VDD=3.6V fin=1kHz AV=1V/V RL=3Ω RL=4Ω RL=8Ω Output Power (W) Power Dissipation (W) 0.0 0.2 0.4 0.6 0.8 1.0 VDD=5V fin=1kHz AV=1V/V RL=8Ω RL=4Ω RL=3Ω Supply Current vs. Output Power Supply Current (A) Output Power (W) 0.0 0.2 0.4 0.6 0.8 1.0 RL=8Ω RL=4Ω RL=3Ω Supply Current vs. Output Power Supply Current (A) Output Power (W) VDD=3.6V fin=1kHz AV=1V/V 0.2 0.4 0.6 0.8 0.0

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw7 APA0715 Typical Operating Characteristics (Cont.) 20 20k100 1k 10k Output Noise Voltage vs. Frequency Output Noise Voltage (Vrms) Frequency (Hz) VDD=5.0V RL=8Ω AV=1V/V Ci=0.22µF A-Weighting 50u 10u 20u 30u 40u 20 20k100 1k 10k Output Noise Voltage vs. Frequency Output Noise Voltage (Vrms) Frequency (Hz) VDD=3.6V RL=8Ω AV=1V/V Ci=0.22µF A-Weighting 50u 10u 20u 30u 40u 20 20k100 1k 10k Output Noise Voltage vs. Frequency Output Noise Voltage (Vrms) Frequency (Hz) VDD=2.4V RL=8Ω AV=1V/V Ci=0.22µF A-Weighting 50u 10u 20u 30u 40u 20 20k100 1k 10k Frequency (Hz) PSRR vs. Frequency Power Supply Rejection Ratio (dB) RL=8Ω AV=1V/V Cb=0.47µF Ci=2.2µF Inputs ac-Grounded VDD=2.4V VDD=3.6V VDD=5.0V -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k T Frequency (Hz) PSRR vs. Frequency Power Supply Rejection Ratio (dB) RL=8Ω AV=1V/V Cb=0.47µF Ci=2.2µF Inputs Floating VDD=2.4VVDD=3.6V VDD=5.0V -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k100 1k 10k R Frequency (Hz) PSRR vs. Frequency Power Supply Rejection Ratio (dB) VDD=3.6V RL=8Ω AV=1V/V Ci=2.2µF Inputs ac-Grounded Cb=0.47µF Cb=0.1µF Cb=0.01µF Cb=1µF -100 -90 -80 -70 -60 -50 -40 -30 -20 -10

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw8 APA0715 Typical Operating Characteristics (Cont.) 20 20k100 1k 10k CMRR vs. Frequency Common Mode Rejection Ratio (dB) Frequency (Hz) RL=8Ω AV=1V/V Vin=0.2VPP Ci=0.22µF VDD=2.4VVDD=3.6V VDD=5.0V -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Voltage Common Mode Rejection Ratio (dB) Common Mode Input Voltage RL=8Ω AV=1V/V Vin=0.2VPP Ci=0.22µF VDD=2.4VVDD=3.6V VDD=5.0V -80 -70 -60 -50 -40 -30 -20 -10 10 200k100 1k 10k Frequency Response Frequency (Hz) Gain (dB) Phase (deg) VDD=5.0V AV=1V/V RL=8Ω Ci=0.22µF Gain Phase +60 +260 +100 +140 +180 +220 10 200k100 1k 10k Frequency Response Frequency (Hz) Gain (dB) Phase (deg) Gain Phase VDD=3.6V AV=1V/V RL=8Ω Ci=0.22µF +60 +260 +100 +140 +180 +220 10 200k100 1k 10k Frequency Response Gain (dB) Phase (deg) Gain Phase VDD=2.4V AV=1V/V RL=8Ω Ci=0.22µF +60 +260 +100 +140 +180 +220 Frequency (Hz) Supply Voltage (V) Supply Current (mA) Supply Current vs. Supply Voltage 0.0 0.5 1.5 2.0 2.5 3.0 2.4 3.5 4.5 5.5 1.0 3.0 4.0 5.0 AV=1V/V No Load

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw9 APA0715 Typical Operating Characteristics (Cont.) Supply Voltage (dBV) Output Voltage (dBV) Frequency (Hz) GSM Power Supply Rejection vs. Frequency -160 -120 -80 -40 0 2k400 800 1.2k 1.6k-160 -120 -80 -40 Start-up Time vs. Bypass Capacitor 120 150 Bypass Capacitor (µF) Start-up Time (ms) VDD=5.0V AV=1V/V No Load

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw10 APA0715 Operating Waveforms GSM Power Supply Rejection vs. Time Power On VDD VROUT Power Off VDD VROUT CH1: VDD, 100mV/Div, DC, VDD Offset =5.0V CH2: VROUT, 20mV/Div, DC TIME: 2ms/Div VDD VROUT CH1: VDD, 2V/Div, DC CH2: VROUT, 50mV/Div, DC TIME: 20ms/Div CH1: VDD, 2V/Div, DC CH2: VROUT, 50mV/Div, DC TIME: 50ms/Div Shutdown Release

2 VROUTN

CH1: VRSD, 2V/Div, DC CH2: VROUTN, 2V/Div, DC TIME: 20ms/Div

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw11 APA0715 Operating Waveforms (Cont.) Pin Description PIN NO. NAME I/O/P FUNCTION SD I Shutdown mode control signal input, place left channel speaker amplifier in shutdown mode when held low.

2 BYPASS P Bypass voltage input pin

3 INP I The non-inverting input of amplifier. INP is via a capacitor to Gnd for single-end (SE) input signal. 4 INN I The inverting input of amplifier. INN is used as audio input terminal, typically. 5 ROUTP O The positive output terminal of speaker amplifier.

6 VDD P Supply voltage input pin

7 GND P Ground connection for circuitry. 8 LOUTN O The negative output terminal of speaker amplifier. Shutdown CH1: VRSD, 2V/Div, DC CH2: VROUTN, 2V/Div, DC TIME: 20ms/Div VROUTN VRSD

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw12 APA0715 Block Diagram OUTP LINP LINN BYPASS Bias and Control Circuitrys SD OUTN

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw13 APA0715 Typical Application Circuits Single-ended input mode Input 0.22µF 0.22µF SHUTDOWN Control VDD 0.1µF 10µF Ci1 Ci2

2 BYPASSSD 1

10kΩ 10kΩ 10kΩ 10kΩ Cb Cs1 Cs2 RSD 100kΩ 0.22µF

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw14 APA0715 Typical Application Circuits (Cont.) Differential input mode Input 0.22µF 0.22µF SHUTDOWN Control VDD 0.1µF 10µF Ci1 Ci2 10kΩ 10kΩ 10kΩ 10kΩ Cb Cs1 Cs2 RSD 100kΩ 0.22µF

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw15 APA0715 Function Description Fully Differential Amplifier The power amplifiers are fully differential amplifiers with differential inputs and outputs. The fully differential ampli- fier has some advantages versus traditional amplifiers. First, don’t need the input coupling capacitors because the common-mode feedback compensates the input bias. The inputs can be biased from 0.5V to VDD-0.5V, and the outputs are still biased at mid-supply of the power amplifier. If the inputs are biased out of the input range, the coupling capacitors are required. Second, the fully differential amplifier has outstanding immunity against supply voltage ripple (217Hz) cuased by the GSM RF trans- mitters’ signal which is better than the typical audio amplifier. Shutdown Function The over-temperature circuit limits the junction tempera- ture of the APA0715. When the junction temperature ex- ceeds TJ = +150oC, a thermal sensor turns off the amplifiers, allowing the device to cool. The thermal sen- sor allows the amplifiers to start-up after the junction tem- perature cools down to about 125 oC. The thermal protec- tion is designed with a 25 oC hysteresis to lower the aver- age TJ during continuous thermal overload conditions, increasing lifetime of the IC. Thermal Protection Over-Current Protection The APA0715 monitors the output buffers’ current. When the over-current occurs, the output buffers’ current will be reduced and limited to a fold-back current level. The power amplifier will go back to normal operation until the over-current situation has been removed. In addition, if the over-current period is long enough and the IC’s junction temperature reaches the thermal protection threshold, the IC enters thermal protection mode. In order to reduce power consumption while not in use, the APA0715 contains a shutdown function to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when logic low is placed on the SD pin for APA0715. The trigger point between a logic high and logic low level is typically 1.8V. It is best to switch between the ground and the supply voltage VDD to pro- vide maximum device performance. By switching the SD pin to a low level, the amplifier enters a low-consump- tion-current state, IDD for APA0715 is in shutdown mode. Under normal operating, APA0715’s SD pin should pull to a high level to keep the IC out of the shutdown mode. The SD pin should be tied to a definite voltage to avoid unwanted state changing.

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw16 APA0715 Effective Bypass Capacitor (CBYPASS) The BYPASS pin sets the VDD/2 for internal reference by voltage divider. Adding capacitors at this pin to filter the noise and regulator the mid-supply rail will increase the PSRR and noise performance. The capacitors should be as close to the device as possible. The effect of a larger bypass capacitor will im- prove PSRR due to increased supply stability. The bypass capacitance also affects to the start time. The large capacitors will increase the start time when device in shutdown. Optimizing Depop Circuitry Circuitry has been included in the APA0715 to minimize the amount of popping noise at power-up and when com- ing out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to elimi- nate clicks and pops, all capacitors must be fully dis- charged before turn-on. Rapid on/off switching of the de- vice or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops. The bypass voltage ramp up should be slower than input bias voltage. Although the BYPASS pin current source cannot be modified, the size of C BYPASS can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of C BYPASS, turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship between the size of C BYPASS and the turn-on time. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. Hence, it is ad- vantageous to use low-gain configurations. Power Supply Decoupling Capacitor (Cs) The APA0715 is a high-performance CMOS audio ampli- fier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) is This leakage current creates a DC offset voltage at the input of the amplifier. The offset reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier

Application Information

Input Resistance (Ri) and Feedback Resistance (Rf) The gain for the APA0715 is set by the external input re- sistors (Ri) and external feedback resistors (R f). i fV R RA = (1) Ri and R f should range from 1k Ω to 100k Ω . Ri is 10k Ω recommended. For the performance of a fully differential amplifier, it’s better to select matching input resistors R i1 and R i2 . Therefore, 1% tolerance resistors are recommended. If the input resistors are not matched, the CMRR and PSRR performance are worse than using matching devices. Input Capacitor (Ci) When the APA0715 is driven by a differential input source, the input capacitor may not be required. In the single-ended input application, an input capacitor, Ci, is required to allow the amplifier to bias the input sig- nal to the proper DC level for optimum operation. In this case, Ci and the input resistance Ri form a high-pass filter with the corner frequency determined in the following equation: ii )C(highpass CR2 1F π= (2) The value of Ci must be considered carefully because it directly affects the low frequency performance of the circuit. Consider the example where Ri is 10kΩ and the specifi- cation that calls for a flat bass response down to 100Hz. The equation is reconfigured as below: ci i FR2 1C π= (3) When the input resistance variation is considered, the Ci is 0.16µF. Therefore, a value in the range of 0.22µF to 0.47µF would be chosen. A further consideration for this capacitor is the leakage path from the input source through the input network (Ri + Rf, Ci) to the load. input in most applications because the DC level of the amplifiers’ inputs are held at VDD/2. Please note that it is important to confirm the capacitor polarity in the application.

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw17 APA0715 RL (W) PO (W) Efficiency (%) IDD(A) PD (W) PSUP (W) 1 61.5 0.33 0.63 1.63 8 2 62.4 0.66 1.21 3.21 4 1 38.7 0.52 1.58 2.58 2 55.1 0.74 1.63 3.63 3 3 66.8 0.92 1.49 4.49 Application Information (Cont.) Table 1: Efficiency vs. Output Power in 5-V Differential Amplifier Syetems Layout Recommendation 1. All components should be placed close to the APA0715. For example, the input capacitor (Ci) should be close to APA0715’s input pins to avoid causing noise cou- pling to APA0715’s high impedance inputs; the decoupling capacitor (Cs) should be placed by the APA0715’s power pin to decouple the power rail noise. 2. The output traces should be short, wide ( >50mil), and symmetric. 3. The input trace should be short and symmetric. 4. The power trace width should greater than 50mil. 5. The MSOP-8P and DFN3x3-8 Thermal PAD should be soldered on PCB, and the ground plane needs sol- dered mask (to avoid short circuit) except the Thermal PAD area. A final point to remember about linear amplifiers (either SE or Differential) is how to manipulate the terms in the efficiency equation to an utmost advantage when possible. Note that in equation, VDD is in the denominator. This indi- cates that as VDD goes down, efficiency goes up. In other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. Table 1 calculates efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in nearly flat in- ternal power dissipation over the normal operating range. Note that the internal dissipation at full output power is The optimum decoupling is achieved by using two differ- ent types of capacitors that target on different types of noises on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series- resistance (ESR) ceramic capacitor, typically 0.1µF, is placed as close as possible to the de- vice VDD lead works best. For filtering lower frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near the audio power amplifier is recommended. Fully Differential Amplifier Efficiency The traditional class AB power amplifier efficiency can be calculated starts out as being equal to the ratio of power from the power supply to the power delivered to the load. The following equations are the basis for calculating the amplifier efficiency. where: So the Efficiency (η ) is: as low as possible. Power supply decoupling also pre- vents the oscillations being caused by long lead length between the amplifier and the speaker. Power Supply Decoupling Capacitor (Cs) (Cont.) SUP O P P )( Efficiency =η L P L Orms O V R V P == VV P Orms = L PPDD AVGDDDDSUP R V2VXIV P π= ＝）（ L P AVG)DD R 2V I π=（ DD LO DD P R2P V )( Efficiency ππ=η ＝ (4) (5) (6) less than the dissipation in the half power range. Calcu- lating the efficiency for a specific system is the key to proper power supply design. For a Mono 1W audio sys- tem with 8Ω loads and a 5V supply, the maximum draw on the power supply is almost 1.63W.

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw18 APA0715 1.4mm 1.85mm 0.38mm Figure 1:TDFN3X3-8 Land Pattern Recommendation 3.3mm 0.65mm 0.7mm Ground plane for Thermal PAD Solder Mask to Prevent Short Circuit ThermalVia diameter 0.3mm X 5 1.95mm Application Information (Cont.) Layout Recommendation (Cont.)

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw19 APA0715

Package Information

A VIEW A 0.25 GAUGE PLANE SEATING PLANE D e SEE VIEW A E b c SYMBOL MIN. MAX. 1.10 0.00 0.22 0.38 0.08 0.23 0.15 A b c D E e L MILLIMETERS A2 0.75 0.95

0.65 BSC

0.40 0.80

0.026 BSC

MIN. MAX. INCHES 0.043 0.000 0.030 0.037 0.009 0.015 0.003 0.009 0.016 0.031 0.006 0° 8° 0° 8° 4.70 5.10 2.90 3.10 2.90 3.10 0.114 0.122 0.185 0.201 0.114 0.122 Note: 1. Follow JEDEC MO-187 AA. 2. Dimension“D”does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension“E1”does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 5 mil per side.

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw20 APA0715 MSOP-8P A VIEW A 0.25 SEATING PLANE GAUGE PLANE D e SEE VIEW A E b c E2EXPOSED PAD S YMB OL MIN. MAX. 1.10 0.00 0.22 0.38 0.08 0.23 0.15 A b c D E e L MILLIMETERS A2 0.75 0.95 0.40 0.80 MIN. MAX. INCHES 0.043 0.000 0.030 0.037 0.009 0.015 0.003 0.009 0.016 0.031 0.006 1.50 2.50 0.059 0.098 1.50 2.50 0.059 0.098 0° 8° 0° 8° 2.90 3.10 2.90 3.10 4.70 5.10 0.114 0.122 0.185 0.201 0.114 0.122 Note: 1. Follow JEDEC MO-187 AA-T 2. Dimension “D”does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not flash or protrusions. 3. Dimension “E1” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 6 mil per side.

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw21 APA0715 A A3 b D E Pin 1 Pin 1 Corner e L K SYMBOL MIN. MAX. 0.80 0.00 0.25 0.35 1.90 2.40 0.05 1.40 A b D E e L MILLIMETERS A3 0.20 REF TDFN3*3-8 0.30 0.50 1.75

0.008 REF

MIN. MAX. INCHES 0.031 0.000 0.010 0.014 0.075 0.094 0.055 0.012 0.020 0.70 0.069 0.028 0.002 0.65 BSC 0.026 BSC 0.20 0.008K 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw22 APA0715 Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 MSOP-8(P) Application A H T1 C d D W E1 F -0.00 13.0+0.50 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 TDFN3x3-8 (mm) Carrier Tape & Reel Dimensions A AB W F T P0OD0 B SECTION B-B SECTION A-A OD1 H A d Package Type Unit Quantity MOSP-8(P) Tape & Reel 3000 TDFN3x3-8 Tape & Reel 3000 Devices Per Unit

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw23 APA0715 Taping Dircetion Information MSOP-8(P) TDFN3x3-8 USER DIRECTION OF FEED USER DIRECTION OF FEED

Copyright  ANPEC Electronics Corp. Rev. A.1 - Dec., 2008 www.anpec.com.tw24 APA0715 Test item Method Description SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C PCT JESD-22-B,A102 168 Hrs, 100%RH, 121°C TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V Latch-Up JESD 78 10ms, 1tr > 100mA Reflow Condition (IR/Convection or VPR Reflow) t 25 C to Peak tp Ramp-up tL Ramp-down ts Preheat Tsmax Tsmin TL TP Temperature Time Critical Zone TL to TP Reliability Test Program Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average ramp-up rate (TL to TP) 3°C/second max. 3°C/second max. Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds Time maintained above: - Temperature (TL) - Time (tL) 183°C 60-150 seconds 217°C 60-150 seconds Peak/Classification Temperature (Tp) See table 1 See table 2 Time within 5°C of actual Peak Temperature (tp) 10-30 seconds 20-40 seconds Ramp-down Rate 6°C/second max. 6°C/second max. Time 25°C to Peak Temperature 6 minutes max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. Classification Reflow Profiles

Copyright  ANPEC Electronics Corp. Table 2. Pb-free Process – Package Classification Reflow Temperatures Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures