APA0711KI-TR

APA0710 ANPEC | Alldatasheet

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Technical content

1.1W Mono Low-Voltage Audio Power Amplifier Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw1 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. The APA0710 is a bridged-tied load (BTL) or singled- ended (SE) audio power amplifier developed especially for low-voltage applications where internal speakers and external earphone operation are required. The APA0711 is a only BTL audio power amplifier developed especially for low-voltage applications where internal speakers are required. Operating with a 5V supply, the APA0710/1 can deliver 1.1W of continuous power into a BTL 8Ω load at 10% THD+N throughout voice band frequencies. Although this device is characterized out to 20kHz,its operation is optimized for narrow band applications such as wireless communications. The BTL configuration eliminates the need for external coupling capacitors on the output in most applications, which is particularly important for small battery-powered equipment. A unique feature of the APA0710 is that it allows the amplifier to switch from BTL to SE on the fly when an earphone drive is required. This eliminates complicated mechanical switching or auxiliary devices just to drive the external load. This device features a shutdown mode for power-sensitive applications with special depop circuitry to eliminate speaker noise when exiting shutdown mode. The APA0710/1 are available in an 8-pin SOP and 8-pin MSOP-P with enhanced thermal pad.

• Operating Voltage : 2.6V-5.5V
• APA0710 Compatible with TPA711 APA0711 Compatible with TPA751
• Bridge-Tied Load (BTL) or Single-Ended (SE) Modes Operation (for APA0710 only)
• Supply Current – IDD=1.3mA at VDD=5V ,BTL mode – IDD=0.9mA at VDD=3.3V ,BTL mode
• Low Shutdown Current – IDD=0.1µA
• Low Distortion – 630mW, at VDD=5V, BTL, RL=8Ω THD+N=0.15% – 280mW, at VDD=3.3V, BTL, RL=8Ω THD+N=0.15%
• Output Power at 1% THD+N – 900mW, at VDD=5V, BTL, RL=8Ω – 400mW, at VDD=3.3V, BTL, RL=8Ω at 10% THD+N – 1.1W at VDD=5V, BTL, RL=8Ω – 480mW at VDD=3.3V, BTL, RL=8Ω
• Depop Circuitry Integrated
• Thermal Shutdown Protection and Over Current Protection Circuitry
• High supply voltage ripple rejection
• Surface-Mount Packaging – 8 pin MSOP-P (with enhanced thermal pad) power package available – SOP-8 package
• Lead Free Available (RoHS Compliant) Features General Description

Applications

• Mobil Phones
• PDAs
• Digital Camera
• Portable Electronic Devices

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw2 Ordering and Marking Information APA0710/1 Handling Code Temp. Range Package Code Package Code K : SOP-8 XA : MSOP-8-P Temp. Range I : -40 to 85 C Handling Code TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device APA0710/1 K : APA0710/1 XXXXX XXXXX - Date Code XXXXX - Date Code Lead Free Code APA0710/1 XA : A0710/1 XXX XX Pin Description SOP-8 4 5 8Shutdown Bypass SE/BTL VO+ GND VDD IN VO- APA0710 SOP-8 4 5 8Shutdown Bypass IN+ VO+ GND VDD IN- VO- APA0711 4 5 8Shutdown Bypass IN+ VO+ GND VDD IN- VO- 4 5 8Shutdown Bypass SE/BTL VO+ GND VDD IN VO- NC = No internal connection = Thermal Pad (connected to GND plane for better heat dissipation) MSOP-8-P APA0710 APA0711 MSOP-8-P Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw3 Block Diagram C B CI RI VDD CsVDD /2 Bypass Shutdown1 Vo+ Vo- GND IN- Bias Control RF Audio Input VDD APA0711 From System Control IN+ CB CI RI VDD Cs CC VDD /2 Bypass Shutdown SE/BTL Vo+ Vo- GND IN Bias Control RF Audio Input VDD From System Control From HP Jack APA0710

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw4 Symbol Parameter Test Conditions Min. Max. Unit VDD Supply Voltage 2.6 5.5 V Shutdown, Shutdown 2.2 VIH High-Level Voltage SE/BTL 0.9VDD V Shutdown, Shutdown 0.4 VIL Low-Level Voltage SE/BTL 0.9VDD-1 V Recommended Operating Conditions Thermal Characteristics Symbol Parameter Value Unit RTHJA Thermal Resistance from Junction to Ambient in Free Air MSOP-8-P* SOP -8 160 °C/W Symbol Parameter Rating Unit VDD Supply Voltage -0.3 to 6 V VIN Input Voltage Range, Shutdown, SE/BTL -0.3 to VDD+0.3 V TA Operating Ambient Temperature Range -40 to 85 °C TJ Maximum Junction Temperature Internally Limited*1 TSTG Storage Temperature Range -65 to +150 °C TS Soldering Temperature, 10 seconds 260 °C VESD Electrostatic Discharge -2000 to 2000*2 V PD Power Dissipation Internally Limited W Note: 1.APA0710/1 integrated internal thermal shutdown protection when junction temperature ramp up to 170°C 2.Human body model: C=100pF, R=1500Ω , 3 positives pulses plus 3 negative pulses 3.Machine model: C=200pF, L=0.5µF, 3 positive pulses plus 3 negative pulses Absolute Maximum Ratings (Over operating free-air temperature range unless otherwise noted.) * 3.42in2 printed circuit board with 20z trace and copper through 6 vias of 12mil diameter vias. The thermal pad on the MSOP-8-P package with solder on the printed circuit board.

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw5 APA0710/1 Symbol Parameter Test Conditions Min. Typ. Max. Unit VOO Output Offset Voltage RL = 8Ω , RF = 10kΩ 20 mV BTL mode, RF = 10kΩ 0.9 1.8 IDD Supply Current SE mode, RF = 10kΩ 0.55 1.1 mA IDD(SD) Supply Current, Shutdown Mode RF = 10kΩ 0.1 2 µA Shutdown, VI = VDD 1 Shutdown, VI = VDD 1 |IH| SE/BTL, VI = VDD 1 µA Shutdown, VI = 0V 1 Shutdown, VI = 0V 1 |IL| SE/BTL, VI = 0V 1 µA Operating characteristic, V DD = 3.3V, TA = 25°C, RL = 8W THD = 1%, BTL mode, RL = 8Ω 400 PO Output Power (Note 1) THD = 1%, SE mode, RL = 32Ω 40 mW THD+N Total Harmonic Distortion Plus Noise (Note 1) PO = 280mW, BTL mode, RL = 8Ω 0.15 % Bom Maximum Output Power Bandwidth Gain = 2, THD+N = 2% 20 kHz B1 Unity-Gain Bandwidth Open Loop 2 MHz CB = 1µF, BTL mode, RL = 8Ω 74 PSRR Power Supply Rejection Ratio (Note1) CB = 1µF, SE mode, RL = 8Ω 61 dB Vn Noise Output Voltage Gain = 1, CB = 0.1µF 28 µV(rms) TWU Wake-up time CB = 1µF 380 ms

Electrical Characteristics

Electrical Characteristics at Specified Free - Air Temperature VDD = 3.3V, TA = 25°C (unless otherwise noted) VDD= 5V, TA= 25°C (unless otherwise noted) APA0710/1 Symbol Parameter Test Conditions Min. Typ. Max. Unit VOO Output Offset Voltage RL = 8Ω , RF = 10kΩ 20 mV BTL mode, RF = 10kΩ 1.3 2.6 IDD Supply Current SE mode, RF = 10kΩ 0.75 1.5 mA IDD(SD) Supply Current , Shutdown Mode RF = 10kΩ 0.1 2 µA

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw6 APA0710/1 Symbol Parameter Test Conditions Min. Typ. Max. Unit Shutdown, VI = VDD 1 Shutdown, VI = VDD 1 |IH| SE/BTL, VI = VDD 1 µA Shutdown, VI = 0V 1 Shutdown, VI = 0V 1 |IL| SE/BTL, VI = 0V 1 µA Operating characteristic, VDD = 5V, TA = 25°C, RL = 8W THD = 1%, BTL mode, RL = 8Ω 900 PO Output Power ( Note 1) THD = 1%, SE mode, RL = 32Ω 94 mW THD+N Total Harmonic Distortion Plus Noise (Note 1) PO = 630mW, BTL mode, RL = 8Ω 0.15 % Bom Maximum Output Power Bandwidth Gain = 2, THD+N = 2% 20 kHz B1 Unity-Gain Bandwidth Open Loop 2 MHz CB = 1µF, BTL mode, RL = 8Ω 74 PSRR Power Supply Rejection Ratio (Note1) CB = 1µF, SE mode, RL = 8Ω 61 dB Vn Noise Output Voltage Gain = 1, CB = 0.1µF 28 µV(rms) Twu Wake-up time CB = 1µF 400 ms Electrical Characteristics(Cont.) Electrical Characteristics at Specified Free - Air Temperature (Cont.) VDD= 5V, TA= 25°C (unless otherwise noted) Note1 : Output power is measured at the output terminals of device at f=1KHz. Pin Name No I/O Description Shutdown 1 I Shutdown mode control signal input, place entire IC in shutdown mode when held high. Bypass 2 I Bypass pin SE/BTL 3 I When SE/BTL is held low, the APA0710 is in BTL mode. When SE/BTL is held high, the APA0710 is in SE mode IN 4 I In is the audio input terminal VO+ 5 O VO+ is the positive output for BTL and SE modes VDD 6 Supply voltage input pin GND 7 Ground connection for circuitry VO- 8 O VO- is the negative output in BTL mode and a high -impedance output in SE mode Pin Description APA0710

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw7 Pin Description Pin Name No I/O Description Shutdown 1 I Shutdown mode control signal input, place entire IC in shutdown mode when held low. Bypass 2 I Bypass pin IN+ 3 I IN+ is the non-inverting input. IN+ is typically tied to the Bypass terminal. IN- 4 I IN- is the inverting input. IN- is typically used as the audio input terminal. VO+ 5 O VO+ is the positive BTL output. VDD 6 Supply voltage input pin. GND 7 Ground connection for circuitry. VO- 8 O VO- is the negative BTL output. APA0711 CB 1µF CI 0.47 µF RI From System Control VDD CsCC 330 µF VDD /2 Bypass Shutdown SE/BTL 10 kΩ 100 kΩ 100 kΩ 1 k Ω Vo+ Vo- GND IN 0.1 µF Bias Control RF 10 k Ω VDD Audio Input VDD 1µF Typical Application Circuit for APA0710 Application

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw8 _CB 1µF CI 0.47 µF RI From System Control VDD CsVDD/2 Bypass Shutdown IN+ 10kΩ Vo+ Vo- GND IN- Bias Control RF 10 kΩ Audio Input- VDD 1µF Audio Input+ CI 0.47 µF 10kΩ RI RF 10 kΩ Typical Application Circuit (Cont.) for APA0711 Differential Input Application CB 1µF CI 0.47 µF RI From System Control VDD CsVDD/2 Bypass Shutdown IN+ 10kΩ Vo+ Vo- GND IN- Bias Control RF 10 kΩ Audio Input VDD 1µF for APA0711 Application

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw9 -100 -80 -60 -40 -20 20k10k1k10020 -100 -80 -60 -40 -20 20k10k1k10020 200 400 600 800 1000 1200 1400 1600 2.5 3 3.5 4 4.5 5 5.5 -100 -80 -60 -40 -20 20 20k100 1k 10k T Typical Characteristics PSRR vs. Frequency PSRR vs. Frequency Ripple Rejection Ration (dB) Ripple Rejection Ration (dB) Frequency (Hz) Frequency (Hz) No-Capacitor CB=0.1µFCB=1µF VDD=3.3V RL=8Ω SE VDD=5V RL=8Ω SE CB=1µF CB=0.1µF No-Capacitor PSRR vs. Frequency Frequency (Hz) Ripple Rejection Ration (dB) RL=8Ω CB=1µF BTL VDD=3.3V VDD=5V Supply Current vs. Supply Voltage Supply Voltage(V) Supply Current (µA) RF=10kΩ BTL(SE/BTL=0.1VDD) SE(SE/BTL=0.9VDD) CB=2.2µF CB=2.2µF

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw10 Typical Characteristics (Cont.) 0.08 0.09 0.1 0.11 0.12 2.5 3 3.5 4 4.5 5 5.5 200 400 600 800 1000 1200 2.5 3 3.5 4 4.5 5 5.5 100 150 200 250 300 350 400 2.5 3 3.5 4 4.5 5 5.5 100 200 300 400 500 600 700 800 900 1000 8 16 24 32 40 48 56 64 Supply Current vs. Supply Voltage Supply Voltage(V) Supply Current (uA) RF=10kΩ Supply Voltage(V) Output Power (mW) THD+N=1% f=1kHz BTL RL=8Ω RL=32Ω Output Power vs. Supply Voltage Supply Voltage(V) Output Power (mW) Output Power vs. Supply Voltage RL=32Ω RL=8Ω THD+N=1% f=1kHz SE Output Power (mW) Load Resistance(Ω ) Output Power vs. Load Resistance THD+N=1% f=1kHz BTL VDD=5V VDD=3.3V

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw11 100 150 200 250 300 350 8 16 24 32 40 48 56 64 0.01 0.1 20 20k100 1k 10k 0.01 0.1 0.01 0.1 20 20k100 1k 10k THD+N vs. Frequency Typical Characteristics (Cont.) Frequency (Hz) VDD=3.3V Po=250mW RL=8Ω BTL AV=-20V/V AV=-10V/V AV=-2V/V VDD=3.3V f=1kHz AV=-2V/V BTL RL=8Ω THD+N vs. Output Power Output Power (W) VDD=3.3V RL=8Ω AV=-2V/V BTL Po=125mW Po=50mW Po=250mW THD+N vs. Frequency Frequency (Hz) Load Resistance(Ω ) Output Power (mW) Output Power vs. Load Resistance THD+N=1% f=1kHz SE VDD=5V VDD=3.3V THD+N (%)THD+N (%) THD+N (%)

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw12 0.01 0.1 20 20k100 1k 10k RR 0.01 0.1 0.01 10.1 THD+N vs. Frequency Frequency (Hz) VDD=5V RL=8Ω AV=-2V/V BTL Po=50mW Po=700mW Po=350mW 0.01 0.1 Output Power (W) THD+N vs. Output Power RL=8Ω 0.01 0.1 20 20k100 1k 10k VDD=5V f=1kHz AV=-2V/V BTL THD+N vs. Frequency Frequency (Hz) VDD=5V Po=700mW RL=8Ω BTL AV=-20V/V AV=-10V/V AV=-2V/V Typical Characteristics (Cont.) THD+N vs. Output Power Output Power (W) VDD=3.3V RL=8Ω CB=1µF AV=-2V/V BTL f=10kHz f=20kHz f=1kHz f=20Hz THD+N (%) THD+N (%) THD+N (%) THD+N (%)

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw13 0.001 0.1 20 100 1k 10k 20k 0.001 0.01 0.1 20 20k100 1k 10k R 0.001 0.01 0.1 0.01 0.1 0.01 10.1 THD+N vs. Output Power Output Power (W) f=10kHz f=20kHz f=1kHz f=20Hz VDD=5V RL=8Ω CB=1µF AV=2V/V BTL Typical Characteristics (Cont.) AV=-5V/V AV=-10V/V AV=-1V/V VDD=3.3V Po=30mW RL=32Ω SE THD+N vs. Frequency Frequency (Hz) THD+N vs. Frequency Frequency (Hz) Po=10mW Po=15mW Po=30mW VDD=3.3V RL=32Ω AV=-1V/V SE VDD=3.3V f=1kHz RL=32Ω AV=-1V/V SE Output Power (W) THD+N vs. Output Power THD+N (%) THD+N (%) THD+N (%) THD+N (%)

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw14 0.001 0.01 0.1 0.002 0.10.01 T T TT T TT TT TTT TT T T T T TTTTTTTTTTTTTTTTTTTTTTTTTTT T 0.001 0.01 0.1 20 20k100 1k 10k 0.001 0.01 0.1 20 20k100 1k 10k RRRRR AV=-5V/V AV=-10V/V AV=-1V/V VDD=5V Po=60mW RL=32Ω SE THD+N vs. Frequency THD+N (%) Frequency (Hz) 0.01 0.1 VDD=5V f=1kHz RL=32Ω AV=-1V/V SE Output Power (W) THD+N (%) THD+N vs. Output Power Po=15mW Po=30mW Po=60mW VDD=5V RL=32Ω AV=-1V/V SE THD+N vs. Frequency THD+N (%) Frequency (Hz) Typical Characteristics (Cont.) THD+N vs. Output Power THD+N (%) VDD=3.3V RL=32Ω AV=-1V/V SE f=20Hz f=20kHz f=1kHz f=10kHz Output Power (W)

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw15 Typical Characteristics (Cont.) 0.01 0.1 0.002 0.20.01 0.1 T THD+N vs. Output Power Output Power (W) VDD=5V RL=32Ω AV=-1V/V SE f=20kHz f=20Hz f=10kHz f=1kHz 0.01 0.1 20 20k100 1k 10k VDD=3.3V Po=0.1mW RL=10kΩ SE AV=-2V/V AV=-1V/V AV=-5V/V THD+N vs. Frequency Frequency (Hz) THD+N (%) THD+N (%) 0.01 0.1 20 20k100 1k 10k Frequency (Hz) THD+N vs. Frequency THD+N (%) Po=0.1mW Po=0.05mW Po=0.13mW 0.01 0.1 50 20075 100 125 150 175 VDD=3.3V f=1kHz RL=10kΩ AV=-1V/V SE Output Power (µW) THD+N vs. Output Power THD+N (%) VDD=3.3V RL=10kΩ AV=-1V/V SE

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw16 0.01 0.1 50 500100 200 300 400 Typical Characteristics (Cont.) THD+N vs. Output Power Output Power (µW) THD+N (%) f=20Hz f=10kHz f=20kHz f=1kHz 0.001 0.01 0.1 20 20k100 1k 10k TTTTT THD+N vs. Frequency Frequency (Hz) THD+N (%) AV=-5V/V AV=-2V/V AV=-1V/V 0.001 0.01 0.1 20 20k100 1k 10k Frequency (Hz) THD+N vs. Frequency THD+N (%) VDD=5V RL=10kΩ AV=-1V/V SE Po=0.2mW Po=0.1mW Po=0.3mW 0.001 0.01 0.1 50 500100 150 200 250 300 350 400 450 Output Power (µW) THD+N (%) THD+N vs. Output Power VDD=5V f=1kHz RL=10kΩ AV=-1V/V SE VDD=5V Po=0.3mW RL=10kΩ SE VDD=3.3V RL=10kΩ AV=-1V/V SE

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw17 10 100k100 1k 10k +20 +60 +100 +140 +180 +220 +28 +12 +16 +20 +24 +20 +60 +100 +140 +180 +220 +28 +12 +16 +20 +24 10 100k100 1k 10k0.001 0.01 0.1 10 500100 Typical Characteristics (Cont.) THD+N vs. Output Power Output Power (µW) THD+N (%) f=20Hz f=20kHz f=10kHz f=1kHz VDD=5V RL=10kΩ AV=-1V/V SE Close Loop Gain (dB) Phase(°) Close Loop Gain (dB) Phase(°) Close Loop Gain and Phase vs. Frequency Close Loop Gain and Phase vs. Frequency Frequency (Hz) Frequency (Hz) +300 +20 +60 +100 +140 +180 +220 +260 -10 +10 10 100k100 1k 10k Phase(°) Close Loop Gain (dB) Close Loop Gain and Phase vs. Frequency Frequency (Hz) Phase Gain VDD=3.3V RL=8Ω AV=-4V/V Po=250mW BTL Gain Phase Phase Gain VDD=3.3V RL=32Ω AV=-2V/V Po=30mW SE VDD=5V RL=8Ω AV=-4V/V Po=700mW BTL

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw18 100 150 200 250 300 350 0 200 400 600 +300 +20 +60 +100 +140 +180 +220 +260 -10 +10 10 100k100 1k 10k Typical Characteristics (Cont.) Close Loop Gain and Phase vs. Frequency Frequency (Hz) Close Loop Gain (dB) Phase(°) 100 20 20k100 1k 10k Noise Floor vs. Frequency Frequency (Hz) Noise Floor (µVrms) 100 20 20k100 1k 10k Frequency (Hz) Noise Floor (µVrms) Noise Floor vs. Frequency Phase Gain VDD=5V RL=32Ω AV=-2V/V Po=60mW SE RL= 32Ω, SE RL= 8Ω, BTL VDD=3.3V BW=22Hz to 22kHz AV=-1V/V VDD=5V BW=22Hz to 22kHz AV=-1V/V Power Dissipation vs. Output Power Output Power (mW) Power Dissipation (mW) RL=8Ω RL=32Ω VDD=3.3V BTL RL= 8Ω, BTL RL= 32Ω, SE

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw19 100 0 50 100 150 100 120 140 160 180 200 0 50 100 150 200 250 300 100 200 300 400 500 600 700 800 0 200 400 600 800 1000 Typical Characteristics (Cont.) Power Dissipation vs. Output Power Output Power (mW) Power Dissipation (mW) VDD=3.3V SE RL=8Ω RL=32Ω Power Dissipation vs. Output Power Output Power (mW) Power Dissipation (mW) VDD=5V BTL RL=8Ω RL=32Ω VDD=5V SE RL=8Ω RL=32Ω Output Power (mW) Power Dissipation vs. Output Power Power Dissipation (mW)

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw20 Application Descriptions BTL Operation Vbias Vo + Vo - RL OP1 OP2 Figure1: APA0710/1 power amplifier internal configuration The power amplifier OP1 gain is setting by external gain setting, while the second amplifier OP2 is internally fixed in a unity-gain, inverting configuration. Figure 1 shows that the output of OP1 is connected to the input to OP2, which results in the output signals of with both amplifiers with identical in magnitude, but out of phase 180°. Consequently, the differential gain for each channel is 2X (Gain of SE mode). By driving the load differentially through outputs Vo+ and Vo-, an amplifier configuration commonly referred to as bridged mode is established. BTL mode operation is different from the classical single-ended SE amplifier configuration where one side of its load is connected to ground. A BTL amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive to the load, thus doubling the output swing for a specified supply voltage. Four times the output power is possible as compared to a SE amplifier under the same conditions. A BTL configuration, such as the one used in APA0710, also creates a second advantage over SE amplifiers. Since the differential outputs, Vo+, Vo- are biased at half- (1)CLIFI CR C)R(R 80kCbypass 1 << × O supply, no need DC voltage exists across the load. This eliminates the need for an output coupling capacitor which is required in a single supply, SE configuration. Single-Ended Operation Consider the single-supply SE configuration shown Application Circuit. A coupling capacitor is required to block the DC offset voltage from reaching the load. These capacitors can be quite large (approximately 33µF to 1000µF) so they tend to be expensive, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system (refer to the Output Coupling Capacitor). The rules described still hold with the addition of the following relationship : Output SE/BTL Operation (for APA0710 only) The ability of the APA0710 to easily switch between BTL and SE modes is one of its most important costs saving features. This feature eliminates the requirement for an additional headphone amplifier in applications where internal speakers are driven in BTL mode but external headphone or speakers must be accommodated. Internal to the APA0710, two separate amplifiers drive Vo+ and Vo- (see Figure 2). The SE/BTL input controls the operation of the follower amplifier that drives Vo-.

• When SE/BTL is held low, the OP2 is turn on and the APA0710 is in the BTL mode.
• When SE/BTL is held high, the OP2 is in a high output impedance state, which configures the APA0710 as SE driver from Vo+. IDD is reduced by approximately one-half in SE mode. Control of the SE/BTL input can be a logic-level TTL

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw21 In Figure 2, input SE/BTL operates as follows : When the phonejack plug is inserted, the 1kΩ resistor is disconnected and the SE/BTL input is pulled high and enables the SE mode. When this input goes high level, the Vo- amplifier is shutdown causing the speaker to mute. The Vo+ amplifier then drives through the output capacitor (CC) into the headphone jack. When there is no headphone plugged into the system, the contact pin of the headphone jack is connected from the signal pin, the voltage divider set up by resistors 100kΩ and 1kΩ . Resistor 1kΩ then pulls low the SE/BTL pin, enabling the BTL function. Input Capacitor, Ci In the typical application an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri form a high-pass filter with the corner frequency determined in the follow equation : Application Descriptions (Cont.) Control Pin 1kΩ VDD 100kΩ SE/BTL Headphone Jack 100kΩ vo+ Figure 2: SE/BTL input selection by phonejack plug FC(highpass)= 1 2π RiCi (2) The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the example where Ri is 100kΩ and the specification calls for a flat bass response down to 40Hz. Equation is reconfigured as follow : Ci= 1 2π RifC (3) source or a resistor divider network or the mono head- phone jack with switch pin as shown in Application Circuit. Output SE/BTL Operation (for APA0710 only) Consider to input resistance variation, the Ci is 0.04µF so one would likely choose a value in the range of 0.1µF to 1.0µF. A further consideration for this capacitor is the leakage path from the input source through the input network (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at VDD/2, which is likely higher that the source DC level. Please note that it is important to confirm the capacitor polarity in the application. Effective Bypass Capacitor, Cbypass As other power amplifiers, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitors located on the bypass and power supply pins should be as close to the device as possible. The effect of a larger half supply bypass capacitor will improve PSRR due to increased half- supply stability. Typical application employ a 5V regulator with 1.0µF and a 0.1µF bypass as supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA0710/1. The selection of

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw22 Effective Bypass Capacitor, Cbypass (Cont.) << (4) Application Descriptions (Cont.) The bypass capacitor is fed from a 80kΩ resistor inside the amplifier. Bypass capacitor, Cbypass, values of 0.1µF to 2.2µF ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance. The bypass capacitance also effects to the start up time. It is determined in the following equation : Tstart up = 5 x (Cbypass x 80kΩ ) (5) Output Coupling Capacitor, Cc (for APA0710 only) In the typical single-supply (SE) configuration on a APA0710, an output coupling capacitor (Cc) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by equation. FC(highpass)= 1 2π RLCC (6) For example, a 330µF capacitor with an 8Ω speaker would attenuate low frequencies below 60.6Hz. The main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-frequency corner higher degrading the bass response. Large values of CC are required to pass low frequencies into the load. IFI C)R(R ×+O80kCbypass bypass capacitors, especially Cbypass, is thus dependent upon desired PSRR requirements, click and pop performance. To avoid start-up pop noise occurred, the bypass voltage should rise slower than the input bias voltage and the relationship shown in equation (4) should be maintained. Power Supply Decoupling, Cs The APA0710/1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different type capacitors that target on different type of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1µF placed as close as possible to the device VDD lead works best. For filtering lower- frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near the audio power amplifier is recommended. Optimizing Depop Circuitry Circuitry has been included in the APA0710/1 to minimize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops (refer to Effective Bypass Capacitance). The bypass voltage rise up should be slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of Cbypass can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of Cbypass, turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship between the

Copyright  ANPEC Electronics Corp. size of Cbypass and the turn-on time. size of CC, the time constant can be relatively large. should produce a virtually clickless and popless turn-on. advantageous to use low-gain configurations. logic low on the Shutdown pin for APA0711. voltage to avoid unwanted state changes. *High peak voltages cause the THD to increase. Table 1. Efficiency Vs Output Power in 3.3V/8Ω BTL for three different output power levels when load is 8Ω .

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw24 Application Descriptions (Cont.) power supply is almost 1.5W. A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in equation10, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up. In other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. Power Dissipation Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. In equation11 states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving a specified load. In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus the maximum power dissipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. BTL Amplifier Efficiency (Cont.) SE mode : PD,MAX= (11)VDD 2π RL BTL mode : PD,MAX= (12)4VDD 2π RL Since the APA0710/1 is a mono channel power amplifier, the maximum internal power dissipation is equal to the both of equations depending on the mode of operation. Even with this substantial increase in power dissipation, the APA0710/1 does not require extra heatsink. The power dissipation from equation12, assuming a 5V-power supply and an 8Ω load, must not be greater than the power dissipation that results from the equation13 : TJ,MAX - TA θ JA PD,MAX= (13) For MSOP-8-P package with and SOP-8 without thermal pad, the thermal resistance (θ JA) is equal to 50ο C/W and 160ο C/W, respectively. Since the maximum junction temperature (TJ,MAX) of APA0710/1 are 170ο C and the ambient temperature (TA) is defined by the power system design, the maximum power dissipation which the IC package is able to handle can be obtained from equation13. Once the power dissipation is greater than the maximum limit (PD,MAX), either the supply voltage (VDD) must be decreased, the load impedance (RL) must be increased or the ambient temperature should be reduced. Thermal Pad Considerations The thermal pad must be connected to ground. The package with thermal pad of the APA0710/1 requires special attention on thermal design. If the thermal design issues are not properly addressed, the APA0710/1 8Ω will go into thermal shutdown when driving a 8Ω load. The thermal pad on the bottom of the APA0710/1 should be soldered down to a copper pad on the circuit board. Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on the top surface of the circuit board, 6 to 10 vias of 12 mil or smaller in diameter should be used to thermally couple the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to conduct heat away from the thermal pad should be as large as practical. If the ambient temperature is higher than 25°C, a larger copper plane or forced-air cooling will be required to keep the APA0710/1 junction temperature below the thermal shutdown temperature (170°C). In higher ambient temperature, higher airflow rate and/or larger copper area will be required to keep the IC out of thermal shutdown.

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw25 Millimeters Inches Dim Min. Max. Min. Max. A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 H 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 e1 0.33 0.51 0.013 0.020 e2 1.27BSC 0.50BSC φ 1 0° 8° 0° 8° SOP-8 pin ( Reference JEDEC Registration MS-012) HE e1 e2 0.015X45 D AA1 0.004max. L Packaging Information

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw26 Packaging Information Millimeters Inches Dim Min. Max. Min. Max. A1 0.06 0.15 0.002 0.006 A2 0.86 TYP 0.34 TYP A3 0.25 0.4 0.01 0.0126 C 0.13 0.23 0.005 0.009 e 0.65 TYP 0.0256 TYP e1 2.90 3.1 0.114 0.122 E 4.8 5.0 0.189 0.197 E1 2.90 3.1 0.114 0.122 D1 2.146 REF 0.0845 REF H1 1.740 REF 0.0685 REF L 0.9 1.0 0.036 0.039 L1 0.45 0.65 0.018 0.026 φ 6° 6° MSOP-8-P A2A1 L 0.25 GAUGE PLANE C E1E e

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw27 t 25 C to Peak tp Ramp-up tL Ramp-down ts Preheat Tsmax Tsmin TL TP Temperature Time Critical Zone TL to T P Physical Specifications Terminal Material Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb) , 100%Sn Lead Solderability Meets EIA Specification RSI86 -91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) Classificatin Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average ramp-up rate (TL to TP) 3°C/second max. 3°C/second max. Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds Time maintained above: - Temperature (TL) - Time (tL) 183°C 60-150 seconds 217°C 60-150 seconds Peak/Classificatioon Temperature (Tp) See table 1 See table 2 Time within 5°C of actual Peak Temperature (tp) 10-30 seconds 20-40 seconds Ramp-down Rate 6°C/second max. 6°C/second max. Time 25°C to Peak Temperature 6 minutes max. 8 minutes max. Notes: All temperatures refer to topside of the package .Measured on the body surface.

Copyright  ANPEC Electronics Corp. Table 2. Pb -free Process – Package Classification Reflow Temperatures including the stated classification temperature (this means Peak reflow temperature +0 °C. For example 260 °C+0 °C) at the rated MSL level. Table 1. SnPb Entectic Process – Package Peak Reflow Temperature s

Copyright  ANPEC Electronics Corp. Rev. A.5 - Oct., 2005 APA0710/0711 www.anpec.com.tw29 Application A B C J T1 T2 W P E 330±1 62 ± 1.5 12.75 + F D D1 Po P1 Ao Bo Ko t M/SOP-8 (mm) Application Carrier Width Cover Tape Width Devices Per Reel SOP- 8 12 9.3 2500 MSOP- 8 12 9.3 3000 Cover Tape Dimensions Customer Service Carrier Tape & Reel Dimensions(Cont.) A J B C Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369