ANY88

ATTINY48 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• High Performance, Low Power AVR® 8-Bit Microcontroller  Advanced RISC Architecture – 123 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation  High Endurance Non-volatile Memory Segments – 4K/8K Bytes of In-System Self-Programmable Flash program memory(ATtiny48/88) – 64/64 Bytes EEPR OM (ATtiny48/88) – 256/512 Bytes Internal SRAM (ATtiny48/88) – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C / 100 years at 25°C – Optional Boot Code Section with Indepentent Lock Bits  In-System Programming by On-chip Boot Program  True Read-While-Write Operation – Programming Lock for Software Security  Peripheral Features – One 8-bit Timer/Counter with Se parate Prescaler and Compare Mode – One 16-bit Timer/Counter with Presc aler, and Compare and Capture Modes – 8-channel 10-bit ADC in 32-lead TQFP and 32-pad QFN/MLF package – 6-channel 10-bit ADC in 28-pin PDIP and 28-pad QFN/MLF package – Master/Slave SPI Serial Interface – Byte-oriented 2-wire Se rial Interface (Philips I 2C Compatible) – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change  Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI Port – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Three Sleep Modes: Idle, ADC Noise Reduction and Power-down  I/O and Packages – 28 Programmable I/O Lines in 32-lead TQFP and 32-pad QFN/MLF package – 24 Programmable I/O Lines in 28-pin PDIP and 28-pad QFN/MLF package – 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF  Operating Voltage: –1 . 8 – 5.5V  Temperature Range: –- 4 0°C to +85°C  Speed Grade: –0 – 12 MHz @ 4.5 – 5.5V  Low Power Consumption – Active Mode: 1 MHz, 1.8V: 240µA – Power-down Mode: 0.1µA at 1.8V 8-bit Microcontroller with 4/8K Bytes In-System Programmable Flash ATtiny48/88 Preliminary Summary Rev. 8008BS–AVR–06/08

8008BS–AVR–06/08 ATtiny48/88 1. Pin Configurations Figure 1-1. Pinout of ATtiny48/88 (PCINT19/INT1) PD3 (PCINT20/T0) PD4 (PCINT26) PA2 VCC GND (PCINT27) PA3 (PCINT6/CLKI) PB6 (PCINT7) PB7 PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) PA1 (ADC7/PCINT25) GND PC7 (PCINT15) PA0 (ADC6/PCINT24) AVCC PB5 (SCK/PCINT5) (PCINT21/T1) PD5 (PCINT22/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3/MOSI) PB3 (PCINT4/MISO) PB4 PD2 (INT0/PCINT18) PD1 (PCINT17) PD0 (PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) TQFP Top View (PCINT14/RESET) PC6 (PCINT16) PD0 (PCINT17) PD1 (PCINT18/INT0) PD2 (PCINT19/INT1) PD3 (PCINT20/T0) PD4 VCC GND (PCINT6/CLKI) PB6 (PCINT7) PB7 (PCINT21/T1) PD5 (PCINT22/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) GND PC7 (PCINT15) AVCC PB5 (SCK/PCINT5) PB4 (MISO/PCINT4) PB3 (MOSI/PCINT3) PB2 (SS/OC1B/PCINT2) PB1 (OC1A/PCINT1) PDIP

32 MLF Top View

(PCINT19/INT1) PD3 (PCINT20/T0) PD4 (PCINT26) PA2 VCC GND (PCINT27) PA3 (PCINT6/CLKI) PB6 (PCINT7) PB7 PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) PA1 (ADC7/PCINT25) GND PC7 (PCINT15) PA0 (ADC6/PCINT24) AVCC PB5 (SCK/PCINT5) (PCINT21/T1) PD5 (PCINT22/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3/MOSI) PB3 (PCINT4/MISO) PB4 PD2 (INT0/PCINT18) PD1 (PCINT17) PD0 (PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) NOTE: Bottom pad should be soldered to ground.

28 MLF Top View

(PCINT19/INT1) PD3 (PCINT20/T0) PD4 VCC GND (PCINT6/CLKI) PB6 (PCINT7) PB7 (PCINT21/T1) PD5 (PCINT22/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3//MOSI) PB3 (PCINT4/MISO) PB4 PD2 (INT0/PCINT18) PD1 (PCINT17) PD0 (PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) GND PC7 (PCI NT15) AVCC PB5 (SCK/PCINT5) NOTE: Bottom pad should be soldered to ground.

8008BS–AVR–06/08 ATtiny48/88

1.1 Pin Descriptions

1.1.1 VCC

Digital supply voltage.

1.1.2 GND

Ground.

1.1.3 Port A (PA3:0) (in 32-lead TQFP and 32-pad QFN/MLF packages, only)

Port A is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) in 32- lead TQFP and 32-pad QFN/MLF package. The PA3..0 output buffers have symmetrical drive characteristics with both high sink and source capab ility. As inputs, Port A pins that are exter- nally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri- stated when a reset condition becomes active, even if the clock is not running.

1.1.4 Port B (PB7:0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pi ns that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the internal clock operating circuit. The various special features of Port B are elaborated in “Alternate Functions of Port B” on page 64 and “System Clock and Clock Options” on page 25.

1.1.5 Port C (PC7, PC5:0)

Port C is a 8-bit bi-directional I/O port with inte rnal pull-up resistors (selected for each bit). The PC7 and PC5..0 output buffers have symmetrical drive characteristics with both high sink and source capability. As inpu ts, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pi ns are tri-stated when a reset condition becomes active, even if the clock is not running.

1.1.6 PC6/RESET

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char- acteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a reset input. A low level on this pin for longer than the minimum pulse wid th will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 22-3 on page 201. Shorter pulses are not guaranteed to generate a reset. The various special features of Port C are elaborated in “Alternate Functions of Port C” on page 67.

1.1.7 Port D (PD7:0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PD7..4 output buffers have symmetrical drive char acteristics with both high sink and source capabilities, while the PD3..0 output buffers have stronger sink capabilities. As inputs, Port D

8008BS–AVR–06/08 ATtiny48/88 pins that are externally pulled low will source current if th e pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of Port D are elaborated in “Alternate Functions of Port D” on page 70.

1.1.8 AV CC

AVCC is the supply voltage pin for the A/D converter and a selection of I/O pins. This pin should be externally connected to V CC even if the ADC is not used. If the ADC is used, it is recom- mended this pin is connected to V CC through a low-pass filter, as described in “Analog Noise Canceling Techniques” on page 163. The following pins receive their supply voltage from AV CC: PC7, PC5:0 and (in 32-lead pack- ages) PA1:0. All other I/O pins take their supply voltage from VCC.

8008BS–AVR–06/08 ATtiny48/88 2. Overview The ATtiny48/88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional CISC microcontrollers. PORT C (8)PORT B (8)PORT D (8) 16bit T/C 18bit T/C 0 A/D Conv. Internal Bandgap Analog Comp. SPI TWI SRAMFlash EEPROM Watchdog Oscillator Watchdog Timer Oscillator Circuits / Clock Generation Power Supervision POR / BOD & RESET VCC GND Program Logic debugWIRE DATABUS RESET CLKI CPU PORT A (4)

8008BS–AVR–06/08 ATtiny48/88 The ATtiny48/88 provides the following features : 4/8K bytes of In-System Programmable Flash, 64/64 bytes EEPROM, 256/512 byte s SRAM, 24 general purpose I/O lines (28 I/Os in 32-lead TQFP and 32-pad QFN/MLF packages), 32 general purpose working registers, two flexible Timer/Counters with compare modes, internal and external interrupts, a byte-oriented 2-wire serial interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in 32-lead TQFP and 32- pad QFN/MLF packages), a programmable Watchdog Ti mer with internal oscillator, and three software selectable power saving modes. Idle mode stops the CPU while allowing Timer/Coun- ters, 2-wire serial interface, SPI port, and inte rrupt system to continue functioning. Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. ADC No ise Reduction mode stops the CPU and all I/O modules except ADC, and helps to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro- gram running on the AVR core. The Boot program can use any interface to download the application program in the Flash memory. By combining an 8-bit RISC CPU with In-System Self- Programmable Flash on a monolithic chip, the Atmel ATtiny48/88 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny48/88 AVR is supported by a full suite of program and syst em development tools including: C compilers, macro assemblers, program debugger/simulators and evaluation kits.

2.2 Comparison Between ATtiny48 and ATtiny88

The ATtiny48 and ATtiny88 differ only in memory sizes. Table 2-1 summarizes the different memory sizes for the two devices. Table 2-1. Memory Size Summary Device Flash EEPROM RAM ATtiny48 4K Bytes 64 Bytes 256 Bytes ATtiny88 8K Bytes 64 Bytes 512 Bytes

8008BS–AVR–06/08 ATtiny48/88 3. About

3.1 Resources

A comprehensive set of development tools, app lication notes and datasheets are available for download at http://www.atmel.com/avr.

3.2 About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen- tation for more details. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructio ns that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

3.3 Data Retention

Reliability Qualification results show that the pr ojected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

3.4 Disclaimer

Typical values contained in this datasheet ar e based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

8008BS–AVR–06/08 ATtiny48/88 4. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

8008BS–AVR–06/08 ATtiny48/88 (0xBE) TWHSR – – – – – – –T W H S 1 5 2 (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 –1 5 2 (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –T W I E 1 4 9 (0xBB) TWDR 2-wire Serial Interface Data Register 151 (0xBA) TWAR TWA6 TWA5 TWA4 TW A3 TWA2 TWA1 TWA0 TWGCE 151 (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 –T W P S 1 T W P S 0 1 5 0 (0xB8) TWBR 2-wire Serial Interface Bit Rate Register 149 (0xB7) Reserved (0x8B) OCR1BH Timer/Counter1 – Output Compare Register B High Byte 108 (0x8A) OCR1BL Timer/Counter1 – Output Compare Register B Low Byte 108 (0x89) OCR1AH Timer/Counter1 – Output Compare Register A High Byte 108 (0x88) OCR1AL Timer/Counter1 – Output Compare Register A Low Byte 108 (0x87) ICR1H Timer/Counter1 – Input Capture Register High Byte 109 (0x86) ICR1L Timer/Counter1 – Input Capture Register Low Byte 109 (0x85) TCNT1H Timer/Counter1 – Counter Register High Byte 108 (0x84) TCNT1L Timer/Counter1 – Counter Register Low Byte 108 (0x82) TCCR1C FOC1A FOC1B – – – – – –1 0 7 (0x81) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 106 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – –W G M 1 1 W G M 1 0 1 0 4 (0x7F) DIDR1 – – – – – – AIN1D AIN0D 155 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 171 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

8008BS–AVR–06/08 ATtiny48/88 (0x7C) ADMUX – REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 167 (0x7B) ADCSRB –A C M E – – – ADTS2 ADTS1 ADTS0 170 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 168 (0x79) ADCH ADC Data Register High byte 169 (0x78) ADCL ADC Data Register Low byte 169 (0x77) Reserved (0x6F) TIMSK1 – –I C I E 1 – – OCIE1B OCIE1A TOIE1 109 (0x6E) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 82 (0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 54 (0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 P CINT12 PCINT11 PCINT10 PCINT9 PCINT8 54 (0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PC INT4 PCINT3 PCINT2 PCINT1 PCINT0 54 (0x6A) PCMSK3 – – - - PCINT27 PCINT26 PCINT25 PCINT24 54 (0x69) EICRA – – – –I S C 1 1 I S C 1 0 I S C 0 1 I S C 0 0 5 0 (0x68) PCICR – – – – PCIE3 PCIE2 PCIE1 PCIE0 52 (0x66) OSCCAL Oscillator Calibration Register 30 (0x64) PRR PRTWI –P R T I M 0 – PRTIM1 PRSPI –P R A D C 3 5 (0x61) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 31 (0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 44 0x3F (0x5F) SREG I T H S V N Z C 9 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 12 0x37 (0x57) SPMCSR – – – CTPB RFLB PGWRT PGERS SELFPRGEN 179 0x36 (0x56) Reserved – – – – – 0x35 (0x55) MCUCR – BPDS BPDSE PUD – – – – 0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF 44 0x33 (0x53) SMCR – – – – –S M 1 S M 0S E 3 6 0x31 (0x51) DWDR debugWire Data Register 173 0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 154 0x2E (0x4E) SPDR SPI Data Register 122 0x2D (0x4D) SPSR SPIF WCOL – – – – – SPI2X 121 0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 120 0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 24 0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 24 0x28 (0x48) OCR0B Timer/Counter0 Output Compare Register B 82 0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A 81 0x26 (0x46) TCNT0 Timer/Counter0 (8-bit) 81 0x25 (0x45) TCCR0A – – – – CTC0 CS02 CS01 CS00 80 0x23 (0x43) GTCCR TSM – – – – – – PSRSYNC 112 0x21 (0x41) EEARL EEPROM Address Register Low Byte 22 0x20 (0x40) EEDR EEPROM Data Register 22 0x1F (0x3F) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 22 0x1E (0x3E) GPIOR0 General Purpose I/O Register 0 24 0x1D (0x3D) EIMSK – – – – – –I N T 1 I N T 0 5 1 0x1C (0x3C) EIFR – – – – – – INTF1 INTF0 52 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

8008BS–AVR–06/08 ATtiny48/88 Note: 1. For compatibility with future devices, reserved bits s hould be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 – 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical o ne to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 – 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATtiny48/88 is a com- plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 – 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 0x1B (0x3B) PCIFR – – – – PCIF3 PCIF2 PCIF1 PCIF0 53 0x16 (0x36) TIFR1 – –I C F 1 – – OCF1B OCF1A TOV1 110 0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TOV0 82 0x12 (0x32) PORTCR BBMD BBMC BBMB BBMA PUDD PUDC PUDB PUDA 72 0x0E (0x2E) PORTA – – – – PORTA3 PORTA2 PORTA1 PORTA0 74 0x0D (0x2D) DDRA – – – – DDA3 DDA2 DDA1 DDA0 74 0x0C (0x2C) PINA – – – – PINA3 PINA2 PINA1 PINA0 74 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD 5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 74 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 74 0x09 (0x29) PIND PIND7 PIND6 PI ND5 PIND4 PIND3 PIND2 PIND1 PIND0 74 0x08 (0x28) PORTC PORTC7 PORTC6 PORTC 5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 73 0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 73 0x06 (0x26) PINC PINC7 PINC6 PI NC5 PINC4 PINC3 PINC2 PINC1 PINC0 74 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB 5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 73 0x04 (0x24) DDRB DDB7 DDB6 DDB 5 DDB4 DDB3 DDB2 DDB1 DDB0 73 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 73 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

8008BS–AVR–06/08 ATtiny48/88 5. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 BRANCH INSTRUCTIONS RJMP k Relative Jump PC ← PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC ← Z None 2 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 ICALL Indirect Call to (Z) PC ← ZN o n e 3 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1N o n e 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0N o n e 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0) ←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

8008BS–AVR–06/08 ATtiny48/88 ROR Rd Rotate Right Through Carry Rd(7) ←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← TN o n e 1 SEC Set Carry C ← 1C 1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1N 1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1Z 1 CLZ Clear Ze ro Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1I 1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1S 1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Twos Complement Overflow. V ← 1V 1 CLV Clear Twos Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1T 1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1H 1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd ← Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd ← KN o n e 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 SPM Store Program Memory (Z) ← R1:R0 None - IN Rd, P In Port Rd ← PN o n e 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A Mnemonics Operands Description Operation Flags #Clocks

8008BS–AVR–06/08 ATtiny48/88 6. Ordering Information

6.1 ATtiny48

Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering infor mation and minimum quantities. 2. Pb-free packaging alternative, complies to the European Direc tive for Restriction of Hazardous Substances (RoHS direc- tive).Also Halide free and fully Green. 3. Maximum frequency. See Figure 22-1 on page 200. Speed (MHz) Power Supply Ordering Code Package (1) Operational Range 12 (3) 1.8 – 5.5 ATtiny48-AU ATtiny48-MMU ATtiny48-MU ATtiny48-PU 32A 28M1 32M1-A 28P3 Industrial (-40 °C to 85°C) Package Type 32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

8008BS–AVR–06/08 ATtiny48/88

6.2 ATtiny88

Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering infor mation and minimum quantities. 2. Pb-free packaging alternative, complies to the European Direc tive for Restriction of Hazardous Substances (RoHS direc- tive).Also Halide free and fully Green. 3. Maximum frequency. See Figure 22-1 on page 200. Speed (MHz) Power Supply Ordering Code Package (1) Operational Range 12 (3) 1.8 – 5.5 ATtiny88-AU ATtiny88-MMU ATtiny88-MU ATtiny88-PU 32A 28M1 32M1-A 28P3 Industrial (-40 °C to 85°C) Package Type 32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

8008BS–AVR–06/08 ATtiny48/88 7. Packaging Information 7.1 32A

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B32A 10/5/2001 PIN 1 IDENTIFIER 0˚~7˚ PIN 1 L C A1 A2 A D e E1 E B Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 8.75 9.00 9.25 D1 6.90 7.00 7.10 Note 2 E 8.75 9.00 9.25 E1 6.90 7.00 7.10 Note 2 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e 0.80 TYP COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE

8008BS–AVR–06/08 ATtiny48/88 7.2 28M1 San Jose, CA 95131 TITLE DRAWING NO. R REV. A28M1 9/7/06 28M1, 28-pad, 4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm, 2.4 mm Exposed Pad, Micro Lead Frame Package (MLF) SIDE VIEW Pin 1 ID BOTTOM VIEW TOP VIEW Note: The terminal #1 ID is a Laser-marked Feature. D E e K C A y L b

0.45 COMMON DIMENSIONS

(Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.17 0.22 0.27 C 0.20 REF D 3.95 4.00 4.05 D2 2. 35 2.40 2.45 E 3.95 4.00 4.05 E2 2. 35 2.40 2.45 e 0.45 L 0. 35 0.40 0.45 y 0.00 – 0.0 8 K 0.20 – – R 0.20

8008BS–AVR–06/08 ATtiny48/88 7.3 28P3 San Jose, CA 95131 TITLE DRAWING NO. R REV. 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) B28P3 09/28/01 PIN B REF E C L SEATING PLANE A 0º ~ 15º D e eB (4 PLACES) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 4.5724 A1 0.508 – – D 34.544 – 34.798 Note 1 E 7.620 – 8.255 E1 7.112 – 7.493 Note 1 B 0.381 – 0.533 B1 1.143 – 1.397 B2 0.762 – 1.143 L 3.175 – 3.429 C 0.203 – 0.356 eB – – 10.160 e 2.540 TYP Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

8008BS–AVR–06/08 ATtiny48/88 7.4 32M1-A San Jose, CA 95131 TITLE DRAWING NO. R REV. 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, E32M1-A 5/25/06 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D E1 E eb A 0.08 C L P P A 0. 80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A 3 0.20 REF b 0.1 8 0.23 0.30 D D2 2.95 3.10 3.25 4.90 5.00 5.10 4.70 4.75 4. 80 4.70 4.75 4. 80 4.90 5.00 5.10 E E2 2.95 3.10 3.25 e 0.50 B SC L 0. 30 0.40 0.50 P – – 0.60 – – 12 o Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. TOP VIEW SIDE VIEW BOTTOM VIEW Pin 1 ID Pin #1 Notch (0.20 R) K 0.20 – – K K

8008BS–AVR–06/08 ATtiny48/88 8. Errata

8.1 Errata ATtiny48

No errata.

8.2 Errata ATtiny88

No errata.

8008BS–AVR–06/08 ATtiny48/88 9. Datasheet Revision History Please note that page references in this section refer to the current revision of this document. 9.1 Rev. 8008B - 06/08 9.2 Rev. 8008A - 06/08 1. Updated introduction of “I/O-Ports” on page 55. 2. Updated “DC Characteristics(1)” on page 198. 3. Added “Typical Charateristics” on page 212. 1. Initial revision.

8008BS–AVR–06/08 Headquarters International Atmel Corporation San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza

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