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CAN Serial Communications Controller December 20, 2012 IA211080504-07 http://www.innovasic.com Customer Support: Page 1 of 58 (888) 824-4184 IA82527 Serial Communications Controller—CAN Protocol Data Sheet
CAN Serial Communications Controller December 20, 2012 IA211080504-07 http://www.innovasic.com Customer Support: Page 2 of 58 (888) 824-4184 Copyright 2013 by Innovasic Semiconductor, Inc. Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
MILES™ is a trademark Innovasic Semiconductor, Inc. Intel is a registered trademark of Intel Corporation
CAN Serial Communications Controller December 20, 2012 IA211080504-07 http://www.innovasic.com Customer Support: Page 3 of 58 (888) 824-4184 TABLE OF CONTENTS
CAN Serial Communications Controller December 20, 2012 IA211080504-07 http://www.innovasic.com Customer Support: Page 6 of 58 (888) 824-4184 1. Introduction The Innovasic Semiconductor IA82527 Controller Area Network (CAN) Serial Communications Controller is a form, fit, and function replacement for the original Intel® 82527 Serial Communications Controller. These devices are produced using Innovasic’s Managed IC Lifetime Extension System (MILES™). This cloning technology, which produces replacement ICs beyond simple emulations, ensures complete compatibility with the original device, including any “undocumented features.” Additionally, MILES™ captures the clone design in such a way that production of the clone can continue even as silicon technology advances. The IA82527 Serial Communications Controller replaces the obsolete Intel 82527 device, allowing users to retain existing board designs, software compilers/assemblers, and emulation tools, thereby avoiding expensive redesign efforts.
1.1 General Description
CAN protocol uses a multi-master CSMA/CR (Carrier Sense, Multiple Access with Collision Resolution) bus to transfer message objects between network nodes. The IA82527 support CAN Specification 2.0 Part A and B, standard and extended message frames, and has the capability to transmit, receive, and perform message filtering on standard and extended message frames. The IA82527 can store 15 message objects of 8-byte data length. Each message object can be configured as either transmit or receive except for message object 15, which is receive-only. Message object 15 also provides a special acceptance mask designed to filter message identifiers that are received. The IA82527 also provides a programmable acceptance mask that allows users to globally mask any identifier bits of the incoming message. This global mask can be used for both standard and extended message frames. The IA82527 is capable of operating at 5.0 or 3.3 volts. This datasheet discusses both modes of operation. Where applicable, characteristics specific to either 3.3 or 5.0 volt operation are identified separately throughout this datasheet. The IA82527 is manufactured in a reliable 5-volt process technology and is available in 44-lead PLCC or PQFP RoHS packages for the automotive temperature range (-40°C to 125°C).
CAN Serial Communications Controller December 20, 2012 IA211080504-07 http://www.innovasic.com Customer Support: Page 7 of 58 (888) 824-4184
1.2 Features
The primary features of the IA82527 are as follows:
- CAN Protocol Support – Specification 2.0, Part A and Part B – Standard ID Data and Remote Frames – Extended ID Data and Remote Frames
- CAN Bus Interface – Configurable Input Comparator – Configurable Output Driver – Programmable Bit Rate
- Global Mask, Programmable – Standard Message Identifier – Extended Message Identifier
- Message Objects – 14 Transmit/Receive Buffers – 1 Double Buffered Receive Buffer with Programmable Mask
- Flexible Status Interface
- CPU Interface Options – 16-Bit Multiplexed Intel Architecture – 8-Bit Multiplexed Intel Architecture – 8-Bit Multiplexed Non-Intel Architecture – 8-Bit Non-Multiplexed Non-Intel Architecture – Serial (SPI)
- I/O Ports (2) – 8-Bit – Bidirectional
- Flexible Interrupt Structure
- Programmable Clock Output A detailed description of the IA82527, including the features listed above, is provided in Chapter 4, Functional Description.
CAN Serial Communications Controller December 20, 2012 IA211080504-07 http://www.innovasic.com Customer Support: Page 8 of 58 (888) 824-4184 2. Packaging, Pin Descriptions, and Physical Dimensions
2.1 Packages and Pinouts
The Innovasic Semiconductor IA82527 CAN Serial Communications Controller is available in the following RoHS packages:
- 44-Pin Plastic Leaded Chip Carrier (PLCC), equivalent to original Intel PLCC package
- 44-Pin Plastic Quad Flat Pack (PQFP), equivalent to original Intel QFP package
2.1.1 PLCC Package
Figure 1. PLCC Package Diagram
Table 1. PLCC Pin List
2.1.2 PLCC Physical Dimensions
The physical dimensions for the PLCC are as shown in Figure 2. Figure 2. PLCC Physical Dimensions Note: Controlling dimension in inches.
2.1.3 PQFP Package
Figure 3. PQFP Package Diagram
Table 2. PQFP Pin List
2.1.4 PQFP Physical Dimensions
The physical dimensions for the PQFP are as shown in Figure 4. Figure 4. PQFP Physical Dimensions
2.2 Pin/Signal Descriptions
Table 3. Pin/Signal Descriptions provide the 8-bit address bus input to the device. 16-bit data bus (input/output) for the device.
Table 3. Pin/Signal Descriptions (Continued) device during the address phase of the bus cycle. address phase of the bus cycle. must run at <=12 MHz to produce clock output. selects the device allowing CPU access. csas a2/ad2/csas 2 40 chip select active state. Input. Serial Interface Mode.
these lines provide the 8-bit data bus to the device. the remainder of the way to VSS. e rd_n/e 6 44 enable. Input. Active High. Mode 3 (synchronous). icp a0/ad0/icp 4 42 idle clock polarity. Input. Serial Interface Mode. polarity for the idle state of sclk is high.
- PLCC Package: – When the MUX bit of the CPU Interface Register is 0, pin 24 functions as the int_n output and pin 11 functions as p2.6. – When the MUX bit of the CPU Interface Register is 1, pin 11 functions as the int_n output and pin 24 functions as Vcc/2.
- PQFP Package: – When the MUX bit of the CPU Interface Register is 0, pin 18 functions as the int_n output and pin 5 functions as p2.6. – When the MUX bit of the CPU Interface Register is 1, pin 5 functions as the int_n output and pin 18 functions as Vcc/2. int_n/p2.6 11 5 miso ready/miso 28 22 master in slave out. Output (open drain). Serial Interface Mode. When the IA82527 is configured to operate with a serial interface, miso is the serial data output.
- mode1 = 0
- mode0 = 0
- rd_n = 0
- wr_n = 0 the Serial Interface Mode will be selected. The mode1 and mode0 pins are internally connected to weak pull-downs. These pins will be pulled low during reset if unconnected. Following reset, these pins will float. mode1 mode1 30 24 mosi a4/ad4/mosi 42 36 master out slave in. Input. Serial Interface Mode. When the IA82527 is configured to operate with a serial interface, mosi is the serial data input.
purpose). Mode 0, Mode 2, and Serial Interface Mode. pin to be configured as a high-impedance input. port is configured by writing to the P1CONF Register. Data is read from Port 1 via the P1IN Register (BFH). Register following a reset is FFH. the P1OUT Register following a reset is 00H.
the P1CONF Register following a reset is 00H. Data is read from Port 2 via the P2IN Register (CFH). Register following a reset is FFH. the P2OUT Register following a reset is 00H. functions based on CPU interface mode. See Section 4.1.3 I/O Ports. provided to force system CPU wait states as required.
required during a cold reset. driven low for a minimum of 1 ms. are the inputs to the IA82527 from the CAN bus lines.
- When the CoBy Bit in the Bus Configuration Register (2FH) is a 0, rx0 and rx1 are connected to the input comparator rx0 is connected to the non-inverting input and rx1 is connected to the inverting input). A recessive level is read when rx0 > rx1. A dominant level is read when rx1 > rx0.
- When the CoBy Bit in the Bus Configuration Register (2FH) is a 1, input comparison is disabled, and rx0, which is still connected to the non-inverting input of the comparator, is the CAN bus line input. For this configuration, the DcR0 bit of the Bus Configuration Register must be a 0. After a cold reset (power on), the default configuration is the use of both rx0 and rx1 for the CAN bus input. rx1 rx1 21 15 sclk a6/ad6/sclk 40 34 serial clock. Input. Serial Interface Mode. The sclk pin is the serial clock input to the IA82527 (slave device). The clock signal is provided by the master device.
- When a logic 0 is placed on the ste pin, the synchronization bytes sent through the miso pin are 00H and 00H.
- When a logic 1 is placed on the ste pin, the synchronization bytes sent through the miso pin are AAH and 55H. The IA82527 sends the synchronization bytes after the cs_n signal has been asserted tx0 tx0 26 20 Transmit (tx), lines 0 and 1. Output (push-pull). Pins tx0 and tx1 are the outputs from the IA82527 to the CAN bus lines. During a recessive bit, tx0 is high and tx1 is low. During a dominant bit, tx0 is low and tx1 is high. tx1 tx1 25 19 VCC VCC 1 39 Power (VCC). This pin provides power for the IA82527 device. It must be connected to a +5V DC power source. VCC/2 int_n/ VCC/2 24 18 Reference Voltage, ISO Physical Layer (VCC/2). Output. The VCC/2 pin provides a reference voltage for the ISO low-speed physical layer:
- 2.38V DC (minimum) to 2.60V DC (maximum) (VCC = +5.0V; IOUT ≤ 75 μA)
- 1.46V DC (minimum) to 1.688V DC (maximum) (VCC = +3.3V; IOUT ≤ 75 μA) This pin only functions as VCC/2 when the MUX bit of the CPU Interface Register (02H) is 1. VSS1 VSS1 23 17 Ground, Digital (VSS1). This pin provides the digital ground (0V) for the IA82527. It must be connected to a VSS board plane. VSS2 VSS2 20 14 Ground, Analog (VSS2). This pin provides the ground (0V) for the IA82527 analog comparator. It must be connected to a VSS board plane. wr_n wr_n/wrl_n/r-w_n 7 1 write. Input. Active Low. Mode 0. When wr_n is asserted (low), it signals a write cycle.
high byte of data (bits 15–8). low byte of data (bits 7–0). input for this clock source.
- Maximum Ratings, Thermal Characteristics, and DC Parameters
Additionally, the DC parameters of the ISO Physical Layer are provided in Table 7. Table 4. Absolute Maximum Ratings Table 5. Thermal Characteristics
Table 6. DC Parameters Table 7). CLKOUT IOH = −80 μA. All other IOH pins = −200 μA.
Table 7. ISO Physical Layer DC Parameters All ratings listed are for the temperature range TA = −40°C to +125°C (VCC = 5V ± 10%) or (VCC = 3.0 -3.6V).
4.1 Hardware Architecture
A block diagram of the IA82527 CAN Serial Communications Controller is shown in Figure 5.
- CAN Controller
- Message RAM
- CPU Interface
- I/O Ports
- Programmable Clock Output These features are briefly described in the following subsections.
Figure 5. Functional Block Diagram
4.1.1 CAN Controller
data) and the CAN Bus (serial data).
4.1.2 Message RAM
controller simultaneous access to the Message RAM.
4.1.3 CPU Interface
parallel interface options and a serial interface option. Different interface options, or modes, are selected using interface mode pins, mode1 and mode0.
- 8-bit Intel multiplexed address and data buses
- 16-bit Intel multiplexed address and data buses
- 8-bit non- Intel multiplexed address and data buses
- 8-bit non-multiplexed address and data buses The serial interface mode is fully compatible with the Motorola® SPI protocol and will interface to most commonly used serial interfaces. The serial interface is implemented in slave mode only, and responds to the master using the specially designed serial interface protocol. The serial interface mode interconnection scheme is shown in Figure 6.
Figure 6. mosi/miso Connection
CAN Serial Communications Controller December 20, 2012 IA211080504-07 http://www.innovasic.com Customer Support: Page 30 of 58 (888) 824-4184
4.1.3 I/O Ports
The IA82527 contains two 8-bit General Purpose Input Output (GPIO) ports. Each GPIO port is selectable or programmable as either an input or an output. CPU interface modes may use some of the GPIO pins or signals, precluding their use as GPIO. Six bits of GPIO Port 2 (p2.5 to p2.0) are always available as GPIO. GPIO Port 2 bits 6 and 7 (p2.6 and p2.7) have alternate functions as the alternate source for int_n and as the wrh_n input for CPU mode 2 and may be available as GPIO depending on the CPU mode. GPIO Port 1 is available for use as GPIO in CPU modes 0, 2, and SPI and is not available in CPU modes 1 and 3.
4.1.4 Programmable Clock Output
Using an oscillator, clock divider register, and a driver circuit, the IA82527 provides a programmable clock output. The output frequency range available is from the external crystal frequency to that frequency divided by 15. The clock output allows the IA82527 to drive other devices such as the host CPU. The slew rate of the clkout signal is selectable via the CLKOUT Register (1FH).
4.2 Address Map
The IA82527 includes 256 8-bit locations that provide device configuration registers and message storage. The address map is shown in Table 8.
4.3 CAN Message Objects
Each CAN message object has a unique identifier and can be configured as either transmit or receive, except for message object 15. Message object 15 is a double-buffered receive-only buffer with a special mask design to allow select groups of different message identifiers to be received. Each message object contains registers for control and status bits. All message objects have separate transmit and receive interrupts and status bits that allow the host CPU to determine when a message frame has been sent or received. The IA82527 implements a global masking feature that allows the user to globally mask any identifier bits of the incoming message. This mask is programmable, which permits application-specific message identification. The Message Object Structure is shown in Table 9.
Table 8. Address Map
Table 9. Message Object Structure
CAN Serial Communications Controller December 20, 2012 IA211080504-07 http://www.innovasic.com Customer Support: Page 33 of 58 (888) 824-4184 5. AC Specifications The AC characteristics of the IA82527 are provided in the figures and tables of this chapter. The IA82527 can be configured to operate in the following parallel and serial CPU interface modes:
- Mode 0: 8-Bit Multiplexed Intel Architecture
- Mode 1: 16-Bit Multiplexed Intel Architecture
- Mode 2: 8-Bit Multiplexed Non-Intel Architecture
- Mode 3: 8-Bit Non-Multiplexed Non-Intel Architecture
- Serial Interface Mode The AC characteristics of these modes in operation are provided as follows:
- Mode 0 and Mode 1: General Bus Timing (Tables 10 and 11/Figure 7)
- Mode 0 and Mode 1: Ready Timing for Read Cycle (Table 10 and 11/Figure 8)
- Mode 0 and Mode 1: Ready Timing for Write Cycle with No Write Pending (Table 10 and 11/Figure 9)
- Mode 0 and Mode 1: Ready Timing for Write Cycle with Write Pending (Table 10 and 11/Figure 10)
- Mode 2: General Bus Timing (Table 12 and 13/Figure 11)
- Mode 3: Asynchronous Operation, Read Cycle (Table 14 and 15/Figure 12)
- Mode 3: Asynchronous Operation, Write Cycle (Table 14 and 15/Figure 13)
- Mode 3: Synchronous Operation, Read Cycle (Table 16 and 17/Figure 14)
- Mode 3: Synchronous Operation, Write Cycle (Table 16 and 17/Figure 15)
- Serial Interface Mode: icp = 0 and cp = 0 (Table 18 and 19/Figure 16)
- Serial Interface Mode: icp = 1 and cp = 1 (Table 18 and 19/Figure 17)
Table 10. Mode 0 and Mode 1: General Bus and Ready Timing for 5.0V Operation too short to read from 04H and 05H (see tRLDV). than 2×tMCLK between the rising edge of wr_n or wrh_n and the falling edge of rd_n. than 2×tMCLK after the rising edge of wr_n or wrh_for the first write.
Table 11. Mode 0 and Mode 1: General Bus and Ready Timing for 3.3V Operation too short to read from 04H and 05H (see tRLDV). than 2×tMCLK between the rising edge of wr_n or wrh_n and the falling edge of rd_n. than 2×tMCLK after the rising edge of wr_n or wrh_for the first write.
Figure 7. Mode 0 and Mode 1: General Bus Timing
Figure 10. Mode 0 and Mode 1: Ready Timing for Write Cycle with Write Active
Table 12. Mode 2: General Bus Timing for 5.0V Operation
Table 13. Mode 2: General Bus Timing for 3.3V Operation
Figure 11. Mode 2: General Bus Timing
Table 14. Mode 3: Asynchronous Operation Timing for 5.0V Operation edge of cs_n for the write and the falling edge of cs_n for the read are separated by at least 2 × tMCLK.
Table 15. Mode 3: Asynchronous Operation Timing for 3.3V Operation edge of cs_n for the write and the falling edge of cs_n for the read are separated by at least 2 × tMCLK.
Figure 12. Mode 3: Asynchronous Operation, Read Cycle
Figure 13. Mode 3: Asynchronous Operation, Write Cycle
Table 16. Mode 3: Synchronous Operation Timing for 5.0V Operation edge of e for the write cycle and the rising edge of e for the read cycle are separated by at least 2 × tMCLK.
Table 17. Mode 3: Synchronous Operation Timing for 3.3V Operation edge of e for the write cycle and the rising edge of e for the read cycle are separated by at least 2 × tMCLK.
Figure 14. Mode 3: Synchronous Operation, Read Cycle Timing
Figure 15. Mode 3: Synchronous Operation, Write Cycle Timing
Table 18. Serial Interface Mode Timing for 5.0V Operation
Table 19. Serial Interface Mode Timing for 3.3V Operation
- Innovasic Part Number Cross-Reference
Table 20. Innovasic Part Number Cross-Reference Other packages and temperature grades may also be available.
CAN Serial Communications Controller December 20, 2012 IA211080504-07 http://www.innovasic.com Customer Support: Page 54 of 58 (888) 824-4184 7. Errata
7.1 Summary
No. Problem Version 2 Part Numbers IA82527PQF44AR2 IA82527PLC44AR2
1 The CPU writes to Msg Box 15 RAM cannot be read back if
MsgVal is set. Exists
2 Setting the IntPnd bit to 1 from CPU interface will not cause
Interrupt. Exists 3 An unintended Remote Frame may be generated. Exists Majority Logic sample mode delays start of ACK bit transmission by one time quanta. Exists dsack0_n signal may not respond properly under certain conditions. Exists
7.2 Detail
Errata No. 1 Problem: The CPU writes to Msg Box 15 RAM cannot be read back if MsgVal is set. Description: If the MsgVal bit (Bits [7–6]) of Msg Box 15 Control_0 register (0xF0) is set, any CPU writes to the Msg Box 15 arbitration 0–3 registers (0xF2–0xF5), and data 0–7 registers (0xF7–0xFE) will operate properly, however CPU reads of these registers will return unknown data. In other words, any CPU data written to Msg Box 15 will not be read back correctly if the MsgVal bit is set. If the MsgVal bit (Bits [7–6]) of Msg Box 15 Control_0 register (0xF0) is reset, CPU data written can be read back normally. Workaround: The workaround is to clear the MsgVal bit (Bits [7–6]) of Msg Box 15 Control_0 register (0xF0) before trying to read back any CPU data written to the Msg Box 15 arbitration 0–3 registers (0xF2–0xF5), and data 0–7 registers (0xF7–0xFE).
CAN Serial Communications Controller December 20, 2012 IA211080504-07 http://www.innovasic.com Customer Support: Page 55 of 58 (888) 824-4184 Errata No. 2 Problem: Setting the IntPnd bit to 1 from CPU interface will not cause Interrupt. Description: During normal operation, a CAN message event sets the IntPnd bit of Control 0 Register of the appropriate message box (assuming appropriate interrupt enables are set), and the interrupt signal is asserted. The CPU will then reset IntPnd to clear the interrupt. The errata issue occurs if the user directly sets the IntPnd bit via the CPU interface, no interrupt will be generated. Workaround: None. Errata No. 3 Problem: An unintended Remote Frame may be generated. Description: If a Message Box is set to receive and a Remote Frame with a matching ID and Data Length Code (DLC) is received, the IA82527 will generate an unexpected Remote Frame for the ID in the Message Box instead of just acknowledging the CAN message. A Message Box configured as follows may lead to this scenario, as explained below: 1. A Message Box is set with an ID in the Arbitration Registers to match the ID of Remote Frame. 2. The Message Box Control_0 Register has MsgVal(Bits[7-6]) in the set state. 3. The Message Box Control_1 Register has all fields in the reset state. 4. The Message Box Configuration Register has the Dir bit (bit 3) reset to 0 for receive. 5. The Message Box Configuration Register has the DLC field set to match the DLC of the Remote Frame. When the IA82527 sees a Remote Frame that matches the Message Box ID and DLC, the IA82527 will generate the expected RX_OK status change interrupt. The IA82527 will also generate an unexpected RX interrupt for the Message Box that matches the ID of the Remote Frame if the RXIE field of the Message Box Control_0 register is in the set state. In addition, the IA82527 will generate an unexpected Remote Frame for the ID in the Message Box. Workaround: In a system that uses remote frames, only use a single Remote Frame Requester for a single Remote Frame Responder.
CAN Serial Communications Controller December 20, 2012 IA211080504-07 http://www.innovasic.com Customer Support: Page 56 of 58 (888) 824-4184 Errata No. 4 Problem: Majority Logic sample mode delays start of ACK bit transmission by one time quanta. Description: When the SPL bit (Bit 7) of the Bit Timing Register 1 (0x4F) is set to 1 to enable the 3 sample Majority Logic mode, the transmission of the ACK bit in response to a received CAN frame will be time shifted by 1 time quanta. With sufficient cable propagation delays and propagation delays through CAN transceiver parts, CAN nodes on the CAN bus may see the ACK bit being a 0 shifted over into its ACK delimiter bit time and flag this as an error. Workaround: Use Single Sample mode instead of Majority Logic Sample Mode. The SPL bit of the Bit Timing Register 1 (bit 7 of address 0x4F) should be a 0. Errata No. 5 Problem: dsack0_n signal may not respond properly under certain conditions. Description: Under certain conditions when the cs_n is asserted near the edge of xtal1 the dsack0_n signal may not be properly generated. Depending on the clock divider settings sys_clk and mem_clk at address 0x02, if the setup or hold time for cs_n with respect to xtal1 edge (rising or falling) is violated, it is possible that dsack0_n will not respond to the cycle. This can cause problems for systems that are dependent upon dsack0_n to occur before releasing cs_n to finish the cycle. Note: The cycle still operates correctly in respect to reading or writing of data, only the dsack0_n signal may not be generated. Workaround: Workaround #1: Do not use dsack0_n as part of the bus cycle timing. Workaround #2: cs_n must meet the following timing relationship with regards to the xtal1 clock edge: sys clock divide edge of xtal1 setup (ns) hold (ns) 1 dsc=0 rise 7 16 2 dsc=1 fall 7 16
Table 21 presents the sequence of revisions to document IA211080504. Table 21. Revision History at 3.3V, and added Errata 4.
CAN Serial Communications Controller December 20, 2012 IA211080504-07 http://www.innovasic.com Customer Support: Page 58 of 58 (888) 824-4184 9. For Further Information The Innovasic Semiconductor IA82527 Controller Area Network (CAN) Serial Communications Controller is a form, fit, and function replacement for the original Intel® 82527 Serial Communications Controller. The Innovasic Support Team wants our information to be complete, accurate, useful, and easy to understand. Please feel free to contact our experts at Innovasic at any time with suggestions, comments, or questions. Innovasic Support Team
5635 Jefferson Street NE
Albuquerque, NM 87109 (505) 883-5263 Fax: (505) 883-5477 Toll Free: (888) 824-4184 E-mail: support@innovasic.com Website: http://www.Innovasic.com