AN8130FBP PANASONIC | Alldatasheet

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A/D and D/A Converters Panasonic High Speed Low Power Consumption Bi-CMOS 10-Bit A/D Convertor i Overview Ut mn The AN830FBP is a 10-bit A/D convertor for image processing which employs the bi-CMOS process to real- ize the low consumption power. & soasanseangase @ Features : SEE + 10-bit resolution E E89 S » Maximum conversion rate : 20 MSPS (min.) | E a9 » Sample holding circuit not required os + Low consumption power : 750 mW (typ.) | SEEUEREEEEnEEEL + S/H circuit built-in 3/218 « 2-step parallel type 3 sal ical i a nN + Digital video broadcasting such as D-STB (a) + Image equipment such as hi-vision device « OA equipment such as image scanner » Measuring equipment such as digital oscilloscope 64-pin Flat Package @ Block Diagram DVcc AVec AVer QO-GO— O99SHHSO @) @2) AVes oe LG) AVee @! ‘@) Veen (10) (23) CLKSH nc a © cx (26) INV wm O LS aw va @) AD | eS a 8 e a oe wo @ on G Lowe [8 (55) BLOCK | Ds AGND @ |e D9(MsB)| Olan rr ree li) om COOOODOOMOOODOOB IER) AGND DVeg

A/D and D/A Converters AN8130FBP $$ $$ Oe Wi Major Characteristics (Vcec=5V, Vee=—5V, Ta=25) Parameter [Conciion Rating | _Unit Resolution a a Linearity error [Ym=2Ver CdS SYS Differential lineartyenor | C*dCSCOS CSB Maximumeonversionrate || Sd Cuantaton noise (SN) 3B Differential phase (DP) feux= 20MHz, Nolock [| os | deg Input band (BW) [Vw=2Ve2 te Absolute Maximum Rating (Ta=25°C) Parameter [Symbol Rating nit Vv Supply volage v Analogue input voltage Vv Digital input voltage Vv Digital output current mA Reference voltage Vv Operaing ante pers c Storage temperature x *Ta=70T Ii Recommended Operating Conditions (Ta=25‘C) Parameter [Symbot Tin yp matt Positive supply voltage [Mee 4s 525 Vv Negative supply voltage a a Vv Reference voltage [ve So Vv Ve [ = Vv ‘Analogue input voltage a Vv [vw ae Vv Digital output current a [oe tw SM clock inputpulse width® | tw [ts | | Cs” ns A/D clock input pulse width * | tw Ts Two | CC” ns * fox= 16MHz

AN8130FBP A/D and D/A Converters ANeTSOrpA CO OO Wl Electrical Characteristics (Vec=5V, Vee=—5V, Ta=25T) Parameter [symbot [Condon min op | mar [| Uni [pe || — +i) 3, of ma [te | —* te [at [ Relocu msiuivecunem Pe mew fae te wh Cock input come [te [Vasw=Venm av | — | 1 8] xa [te [Vaxw=Vexu=0av | — | +[ 8] xa Linearity enor [&[ve=2v,-, «(| — ‘| =| — | os Maximum conversion rate [Fou | Vn=2¥Vp-2 ——~+|__20 | — | — | mises [fox=16Mii=imniz | — | ss] — | os Cuantiaton nie SN [iew=20Mtiz.fo=iMez | — | 32 [| — | ap [tax =20MHE,fw=aMiiz | — | 47| — |B Sawtooth 40% subcarric Differential phase [pp __| fae °20MItz, Nolock | — [ os[ 1 [ aeg Clock delay a i Timing Chart : N+2 N+1 Analogue input N 1 t (Vowsn) t Clock input (S/H) (CLKsu) N N+1 N+2 Clock input (A/D) Ne N+2 Digiatourt 3 Xs? |)

A/D and D/A Converters AN8130FBP Ee eels @ Output Code Digital output Sep 2.000VFS 1.953mV STEP M C : om OVE 9876543210 INV= “H” 000 —0,000000 © 0000000000 oo1 —0.001953 © 0000000001 su 0.998047 © otiniiit $12 1.000000 © 1000000000 513 —1,001953 0 1000000001 1023 1.998047 O quaniiit 1024 2.000000 eeeeetieney

1 Pin Descriptions

FaNo | Symbot_|/Pinname | Sundard waveform] Voltage level_] Description

16.17 Morice | iv

4,56 18,11 8, 14, 18 It is a power supply pin for analogue signal. 1, 2, 25 Connect tantalum capacitor of several a F 7.9.3] av, sv and ceramic capacitor of 0.1 F as near as 39g] ]VEE | Atsloeue eatve power spey pin possible to this pin between this pin and 42, 45, 51 AGND. 53, 54, 56 51, 59, 60 28, 30 - It is a power supply pin for digital circuit D ital post i sv block. Connect tantalum capacitor of 49 DVco._| Digital postive power supply pin several 2F and ceramic capacitor of 0.1 — - uF as near as possible to this pin between 9, 12 Connect the analogue ground and digital 15,55] AGND_ | analogue ground pin ov ground with the possible lowest impedance 61 at one point as near as possible to the chip. Inserting ferrite fuse between above two grounds and connecting the AGND with the ground for power supply may decrease the noise.

AN8130FBP A/D and D/A Converters Pin Descriptions (cont.) Pate [ Symi | Pinaane [Sana [ Vorpiont | Poin a [Var [er i ti | Ws used ot hee nal of

63 Vem | Reference voltage middle pointlevel || — IV a ee Reman Mens sero Y

and Veo is given -2 V. Connect tantalum capacitor of several F and ceramic - capacitor of 0.1 1 F in parallel between 1 Vat —_| Reference voltage high level ov each pin and analogue ground. Vem is provided for linearity compensation which gives middle point potential. However, it is normally opened. Setting the INV pin to "L” level invert all the outputs (DO - D9) but not the overflow 26 Digital output invert pin TIL output. This pin is set to "L” level with no connection and operates a synchronously with clock. When overflow occurs, it becomes "H” 34 OVF | Overflow output TIL level. This output is not affected by the INV pin It is an input pin of analogue signal for sample holding circuit. Input capacitance is about 10 pF. However, in order to obtain good frequency characteristics, P ~-2v drive it by using a buffer with the possible 10 | VINsu | Analogue input (S/H) or largest driving capacity. ‘The resistor of about 150 Q should be inserted between this pin and AGND pin to make the frequency characteristics flat.

3 Analogue input (A/D) | == O~—2V_| Itis an output for sample holding circuit,

Tt is an input pin of analogue signal for A/D conversion circuit. Normally, the . sample holding output VOs« is directly 2 Analogue input (A/D) 0~—2V connected with it. When ringing is large, connect the inductor of about 0.3 4 H and the resistor of about 150 0 in series with it. Itis a clock for A/D and S/H circuits. For their timing, refer to the attached sheet. A Input the data of small jitter at TTL level. 23 | ChKsa | Clock input (S/1), Refertothe | op Take care to suppress the ringing, 24 | CLKap | Clock input (A/D) timing chart. particularly overshoot. When CMOS is used, the high level should set 3.5 V or lower by resistive divider.

35 DO Digital output (LSB)

36 DI Digital ouput It is an output pin for the TTL level. In

37 D2 Digital output order to prevent the digital noise to

38 D3__| Digital output entering into the analogue circuit, suppress

4 D4 —_| Digital output Refertothe | pry the ringing as far as possible. It is a Ds _| Digital output timing char. effective to insert the ferrite beads or mn" D6 | Digital output resistor of about 220 2 between each pin ae and the input pin for IC of logic which 46 D7 Digital output receives it.

47 D8_—_| Digital output

48 D9 Digital output (MSB)

A/D and D/A Converters AN8130FBP <_< @ Characteristic Curve Input Signal Frequency and SINAD/Distortion Conversion Frequency and SINAD (Conversion Frequency = 20 MHz) © © -0 5 eC LE «Coos gol PTT Peer TTT AT TTT PTT EL TMM TTT} resin tr é gat LUT TT Tg TT || Lee eC IT eer Sof UTI TTT Sr TTI) 2M TT Ty a” *oL TTT TTT TP #0 EE TP). or 0203 03123 510 20-30 or 0203 05. «12 3 510 Conversion Frequency (MHz) Input Signal Frequency fin (MHz) Input Signal Frequency and SNR/DNL (Conversion Frequency =20MHz) on . CLS § J ene) TT Trl |, 2 2 {LIU TIN” z 2 _eermmen | TTT. 8 gL] TI TTT ‘eee CUM, | ge oL_L TUT TT, or 020305. 1 23 510 Input Signal Frequency fin (MHz) E