AN79953

CY8C41XX INFINEON | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 59

Technical content

Features

• 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU with single-cycle multiply - Up to 384 KB of flash with Read Accelerator - Up to 32 KB of SRAM - 16-channel DMA engine
• Programmable analog - Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator modes and ADC input buffering capability. Opamps can operate in Deep Sleep low-power mode. - 12-bit 1-Msps SAR ADC with differential and single-ended modes, and Channel Sequencer with signal averag- ing - Temperature sensor built into SAR ADC - Two low-power comparators that operate in Deep Sleep low-power mode
• Programmable digital - Programmable Smart I/O logic blocks allowing Boolean operations to be performed on port inputs and out- puts
• Low-power 1.71-V to 5.5-V operation - Deep Sleep mode with operational analog and 3.7-µA digital system current
• Capacitive sensing - Multi-sensing converter (MSC) provides best-in-class signal-to-noise ratio (SNR) (>5:1) and liquid tolerance for capacitive sensing - Infineon-supplied software middleware makes capacitive sensing design easy - Automatic hardware tuning (SmartSense) - Two MSC converters are provided - Autonomous channel scanning without CPU assistance
• L C D D r i v e c a p a b i l i t y - LCD segment drive capability on GPIOs
• I 2 S -I 2 S m a s t e r t r a n s m i t t e r
• Cryptographic block - AES, SHA, TRNG, PRNG, and CRC functions
• Serial communication -C A N F D - Five independent run-time reconfigurable serial co mmunication blocks (SCBs) with re-configurable I 2C, SPI, or UART functionality. High-speed I2C support is provided.

Datasheet 2 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU

• Timing and pulse-width modulation - Eight 16-bit timer/counter/pulse-width modulator (TCPWM) blocks - Center-aligned, Edge, and Pseudo-random modes - Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications - Quadrature decoder
• Clock sources - 4 to 33 MHz external crystal oscillator (ECO) - PLL to generate 48-MHz frequency - 32-kHz watch crystal oscillator (WCO) - ±2% internal main oscillator (IMO) - 40-kHz internal low-power oscillator (ILO)
• Up to 84 programmable GPIO pins - 100-pin TQFP (0.5-mm pitch), 64-pin TQFP (0.5-mm pitch), and 48-pin TQFP (0.5-mm) packages - GPIO pins can have sensing, analog, or digital functionality
• ModusToolbox™ software - Comprehensive collection of multi-platform tools and software libraries - Includes board support packages (BSPs), peripheral driver library (PDL), and middleware such as CAPSENSE™
• Industry-standard tool compatibility - After configuration, development can be done with Arm®-based industry-standard development tools

Datasheet 3 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Table of contents Table of contents

Datasheet 4 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Table of contents

Datasheet 5 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Development ecosystem

1 Development ecosystem

1.1 PSoC™ 4 MCU resources

There is a wealth of data at www.infineon.com to help you select the right PSoC™ device and quickly and effec- tively integrate it into your design. The following is an abbreviated, hyperlinked list of resources for PSoC™ 4 MCU:

• Overview: PSoC™ Portfolio , PSoC™ Roadmap
• Product selectors: PSoC™ 4 MCU
• Application notes cover a broad range of topics, from basic to advanced level, and include the following: - AN79953: Getting Started With PSoC™ 4 - AN91184: PSoC™ 4 Bluetooth® LE - Designing Bluetooth® LE applications - AN88619: PSoC™ 4 hardware design considerations - AN73854: Introduction to bootloaders - AN89610: Arm® Cortex® code optimization - AN86233: PSoC™ 4 MCU power reduction techniques - AN57821: Mixed signal circuit board layout - AN85951: PSoC™ 4, PSoC™ 6 MCU and CAPSENSE™ design guide - AN96475: Design Considerations for Electrical Fast Transient (EFT) Immunity of a CAPSENSE™ system - AN80994: Design Considerations for Electrical Fast Transient (EFT) Immunity
• Code examples demonstrate product features and usage, and are also available on the GitHub repositories.
• Technical reference manuals (TRMs) provide detailed descriptions of PSoC™ 4 MCU architecture and registers.
• PSoC™ 4 MCU programming specification provides the information necessary to program PSoC™ 4 MCU nonvolatile memory.
• Development tools - ModusToolbox™ software enables cross platform code development with a robust suite of tools and software libraries. - CY8CKIT-041S-MAX PSoC™ 4100S Max pioneer kit, is an easy-to-use and inexpensive development platform. This kit includes connectors for Arduino™ compatible shields. - MiniProg4 and MiniProg3 all-in-one development programmers and debuggers.
• PSoC™ 4 MCU CAD libraries provide footprint and schematic support for common tools. IBIS models are also available.
• Training videos are available on a wide range of topics including the PSoC™ 4 MCU 101 series .
• Infineon Developer Community enables connection with fellow PSoC™ developers around the world, 24 hours a day, 7 days a week, and hosts a dedicated PSoC™ 4 MCU Community .

Datasheet 6 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Development ecosystem

1.2 ModusToolbox™ software

ModusToolbox™ software is a comprehensive collection of multi-platform tools and software libraries that enables an immersive development experience for creating converged MCU and wireless systems. It is:

• Comprehensive - it has the resources you need
• Flexible - you can use the resources in your own workflow
• Atomic - you can get just the resources you want There is a large collection of code repositories on GitHub, including:
• Board support packages (BSPs) aligned with Infineon kits
• Low-level resources, including a peripheral driver library (PDL)
• Middleware enabling industry-leading features such as CAPSENSE™
• An extensive set of thoroughly tested code example applications ModusToolbox™ software is IDE-neutral and easily adaptable to your workflow and preferred development environment. It includes a project creator, peripheral and library configurators, a library manager, as well as the optional Eclipse IDE for ModusToolbox™, as Figure 1 shows. For information on using Infineon tools, refer to the documentation delivered with ModusToolbox™ software, and AN79953 - Getting started with PSoC™ 4. Figure 1 ModusToolbox™ software tools

Datasheet 7 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Block diagram Block diagram This device includes extensive support for programming, testing, debugging, and tracing both hardware and firmware. The Arm® Serial-Wire Debug (SWD) interface supports all programming and debug features of the device. Complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The ModusToolbox™ software IDE provides fully integrated programming and debug support for this device. The SWD interface is fully compatible with industry-standard third-party tools. It has the following advantages:

• Allows disabling of debug features
• Robust flash protection
• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the firmware thus providing security. Additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled. Therefore, this device, with device security enabled, may not be returned for failure analysis. This is a trade-off it allows the customer to make. Peripherals CPU Subsystem System Interconnect (Single Layer AHB) PSoC™ 4100S Max IOSS GPIO (8x ports) IO Subsystem Peripheral Interconnect (MMIO)PCLK FLASH 384 KB Read Accelerator SPCIF SRAM Controller ROM 8 KB ROM Controller 32-bit AHB-Lite Up to 84x GPIOs DeepSleep Active/Sleep Power Modes Digital DFT Test Analog DFT System Resources Lite Power Clock Reset Clock Control IMO Sleep Control REFPO R Reset Control TestMode Entry WIC XRES WDT ILO PWRSYS 8x TCPWM WCO 2x LP Comparator SAR ADC (12-bit) CTBm 2x OpAmp Programmable Analog SARMUX High-speed I/O Matrix & Smart I/O SWD/TC, MTB NVIC, IRQMUX, MPU Cortex® M0+

48 MHz

ECO (w/PLL) CAN FD DataWire/ DMA Initiator/MMIO CRYPTO (AES,SHA,TRNG, PRNG, CRC) I2S Master TX

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2 Functional definition

2.1 CPU and memory subsystem

2.1.1 CPU

The Cortex®-M0+ CPU in PSoC™ 4100S Max is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a subset of the Thumb-2 instruction set. It includes a nested vectored interrupt controller (NVIC) block with eight interrupt inputs and also includes a Wakeup Interrupt Controller (WIC). The WIC can wake the processor from Deep Sleep mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode. The CPU subsystem includes a 16-channel DMA engine and also includes a debug interface, the serial wire debug (SWD) interface, which is a two-wire form of JTAG. The debug configuration used for PSoC™ 4100S Max has four breakpoint (address) comparators and two watchpoint (data) comparators.

2.1.2 Cryptographic accelerator

The Crypto accelerator block supports 128-bit AES, all SHA modes, True Random Number and Pseudo Random Number Generator function, and a CRC function. It incorporates a 512 byte instruction and operand storage buffer.

2.1.3 Flash

The PSoC™ 4100S Max device has a 384 KB flash module with a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS) access time at 48 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average.

2.1.4 SRAM

32 KB of SRAM are provided with zero wait-state access at 48 MHz.

2.1.5 SROM

An 8-KB supervisory ROM that contains boot and configuration routines is provided.

2.2 System resources

2.2.1 Power system

The power system is described in detail in the section “Power” on page 24. It provides assurance that voltage levels are as required for each respective mode and either delays mode entry (for example, on power-on reset (POR)) until voltage levels are as required for proper functionality, or generates resets (for example, on brown-out detection). operates with a single external supply over the range of either 1.8 V ±5% (externally regulated) or 2.0 to 5.5 V (internally regulated) and has three different power modes, transitions between which are managed by the power system. PSoC™ 4100S Max provides Active, Sleep, and Deep Sleep low-power modes. All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes 35 µs. The opamps can remain operational in Deep Sleep mode.

2.2.2 Clock system

The PSoC™ 4100S Max clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. In addition, the clock system ensures that there are no metastable conditions. The clock system for the PSoC™ 4100S Max consists of the IMO, ILO, a 32-kHz Watch Crystal Oscillator (WCO), MHz ECO and PLL, and provision for an external clock. The WCO block allows locking the IMO to the 32-kHz oscillator.

Datasheet 9 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Functional definition Figure 2 MCU clocking architecture The HFCLK signal can be divided down as shown to generate synchronous clocks for the analog and digital peripherals. There are 21 clock dividers for the PSoC™ 4100S Max (six with fractional divide capability, 15 with integer divide only). There are 15 16-bit dividers allowing a lot of flexibility in generating fine-grained frequencies. In addition, there are five 16-bit fractional dividers and one 24-bit fractional divider.

2.2.3 IMO clock source

The IMO is the primary source of internal clocking in the PSoC™ 4100S Max. It is trimmed during testing to achieve the specified accuracy. The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO tolerance with Infineon-provided calibration settings is ±2% over the entire voltage and temperature range.

2.2.4 ILO clock source

The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the watchdog timer (WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Infineon provides a software component, which does the calibration.

2.2.5 Watch crystal oscillator (WCO)

The PSoC™ 4100S Max clock subsystem a lso implements a low-frequency (32-kHz watch crystal) oscillator that can be used for precision timing applications. The WCO block allows locking the IMO to the 32 kHz oscillator.

2.2.6 External crystal oscillators (ECO)

The PSoC™ 4100S Max also implements a 4 to 33 MHz crystal oscillator.

2.2.7 Watchdog timer and counters

A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is recorded in a Reset Cause register, which is firmware readable. The Watchdog counters can be used to implement a Real-Time clock using the 32-kHz WCO.

2.2.8 Reset

PSoC™ 4100S Max can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the reset. An XRES pin is reserved for external reset by asserting it active low. The XRES pin has an internal pull-up resistor that is always enabled. ECO IMO PLL LFCLK ILO WCO Watchdog Counters (WDC) WDT Watchdog Timer (WDT) WDC0 16-bits WDC1 16-bits WDC2 32-bits Divide By 2,4,8 HFCLK HFCLK 5X 16.5-bit, 1X 24.5 bit Integer Dividers Fractional Dividers SYSCLKPrescaler 15X 16-bit External Clock

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2.3 Analog blocks

2.3.1 12-bit SAR ADC The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks to do a 12-bit conversion. The Sample-and-Hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the amplifier driving the SAR inputs, which determine its settling time, to be relaxed if required. It is possible to provide an external bypass (through a fixed pin location) for the internal reference amplifier. The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through selected channels autonomously (sequencer scan) with zero switching overhead (that is, aggregate sampling bandwidth is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching is effected through a state machine or through firmware driven switching. A feature provided by the sequencer is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying source impedance and frequency, it is possible to have different sample times programmable for each channel. Also, signal range specification through a pair of range registers (low and high range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed and the CPU to read the values and check for out-of-range values in software. The SAR is not available in Deep Sleep mode as it requires a high-speed clock (up to 18 MHz). The SAR operating range is 1.71 V to 5.5 V. Figure 3 SAR ADC

2.3.2 Opamps (continuous-time block; CTB)

PSoC™ 4100S Max has two opamps with Comparator modes which allow most common analog functions to be performed on-chip eliminating external components; PGAs, Voltage Buffers, Filters, Trans-Impedance Amplifiers, and other functions can be realized, in some cases with external passives. saving power, cost, and space. The on-chip opamps are designed with enough bandwidth to drive the Sample-and-Hold circuit of the ADC without requiring external buffering. The opamps can be used in Deep Sleep mode.

2.3.3 Low-power comparators (LPC)

PSoC™ 4100S Max has a pair of low-power comparators, which can also operate in low power modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event. The LPC outputs can be routed to pins. SARMUX SARMUX Po r t (Up to 16 i nputs) vplusvm inus Data and status flags Reference Selection External Reference and Bypass (optional ) POS NEG SAR Sequencer SAR ADC Inputs from other Ports VDDA /2 VDDA VREF AHB System Bus and Programmable Logic Interconnect Sequencing and Control

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2.3.4 Analog multiplexed buses

PSoC™ 4100S Max has two concentric independent buses that go around the periphery of the chip. These buses (called amux buses) are connected to firmware-programmable analog switches that allow the chip's internal resources to connect to any pin on the I/O Ports.

2.4 Programmable digital blocks

2.4.1 Smart I/O block

The Smart I/O block is a fabric of switches and LUTs that allows Boolean functions to be performed in signals being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip and on signals going out as outputs. There are three Smart I/O blocks in the PSoC™ 4100S Max.

2.5 Fixed function digital blocks

2.5.1 Timer/Counter/PWM (TCPWM) block

The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register to record the count value at the time of an event (which may be an I/O event), a period register that is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow use as dead-band programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be shut off immediately with no time for software intervention. Each block also incorporates a Quadrature decoder. There are eight TCPWM blocks in PSoC™ 4100S Max.

2.5.2 Serial Communication Block (SCB)

PSoC™ 4100S Max has five serial communication bl ocks, which can be programmed to have SPI, I2C, or UART functionality. I2C Mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of multi-master arbitration). This block is capable of operating at speeds of up to 1000 kbps (Fast Mode Plus) and has flexible buffering options to reduce interrupt overhead and latency for the CPU. In addition, the block supports HS I2C (3.4 Mbps) in Slave mode only. HS I2C is provided in one SCB block, SCB0. It also supports EZI2C that creates a mailbox address range in the memory of PSoC™ 4100S Max and effectively reduces I 2C communi- cation to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the CPU not having read data on time. The I 2C peripheral is compatible with the I2C Standard-mode and Fast-mode devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. PSoC™ 4100S Max is not completely compliant with the I2C spec in the following respect:

• GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I2C system. UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated. SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.

Datasheet 12 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Functional definition

2.6 GPIO

PSoC™ 4100S Max has up to 84 GPIOs. The GPIO block implements the following:

• Eight drive modes: - Analog input mode (input and output buffers disabled) - Input only - Weak pull-up with strong pull-down - Strong pull-up with weak pull-down - Open drain with strong pull-down - Open drain with strong pull-up - Strong pull-up with strong pull-down - Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL).
• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes
• Selectable slew rates for dV/dt related noise control to improve EMI The pins are organized in logical entities called ports, which are 8-bit in width (less for Ports 5 and 6). During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it.

2.7 Special function peripherals

2.7.1 CAPSENSE™ sensing

CAPSENSE™ is supported in PSoC™ 4100S Max via the MSC CAPSENSE™ block. There are two independent MSC blocks in the PSoC™ 4100S Max which can be used to scan sense inputs autonomously (without CPU sequencing and intervention) with support for DMA, or can operate via CPU firmware driven switch sequencing via the Analog Mux Busses that any GPIO pin can be connected to. CAPSENSE™ function can thus be provided on a pin or group of pins in a system via autonomous scanning or via firmware control. The PSoC™ 4100S Max MSC block provides the following im provements over previous generation capacitive sensing blocks:

• Improved SNR based on the all new ratio-metric analog architecture and advanced hardware filtering to enable modern sleek user interface solutions with superior liquid tolerance, and robust and reliable touch HMI solution for harsh environments.
• Higher sensitivity to support smaller sensors, higher proximity detection range, and a much wider range of overlay thicknesses and materials.
• Autonomous (that is, CPU independent) channel sequencing and scanning for low power optimization.
• Improved shield drive method and support for wide range of shield electrode capacitance values for superior liquid tolerance.
• Higher sensor capacitance range to support easier layout and wider variety of sensors.
• Improved EMI performance
• The MSC block API is backwards compatible with the CSD block to preserve code compatibility. A driver is provided for the CAPSENSE™ block to make it very easy for the user to use. Shield drive for water tolerance is provided. The CAPSENSE™ blocks provide both Self as well as Mutual capacitance sensing. Shield drive can be either Active (with an Op Amp) or passive (less power, for shield loads less than 20 pF).

Datasheet 13 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Functional definition It is possible to synchronize the two MSC blocks to provide true synchronized and synchronous sampling so that the sensing operation can be extended to bigger displays and scan time reduced. Synchronization can extend to multiple chips to extend simultaneous sampling and increase the number of sensors.

2.7.2 LCD segment drive

PSoC™ 4100S Max has an LCD controller, which can drive up to 8 commons and up to 64 segments. Any pin can be either a common or a segment pin. It uses full digital methods to drive the LCD segments requiring no gener- ation of internal LCD voltages. The two methods used are referred to as Digital Correlation and PWM. Digital Correlation pertains to modulating the frequency and drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but can result in better results when driving TN displays.

2.7.3 CAN FD

The CAN FD block used in the PSoC™ 4100S Max is certified to be Bosch CAN standard compliant and operates at 5 Mbps. It incorporates a 4 KB receive and transmit buffer.

2.7.4 I2S Master

This is an I2S TX master interface. The interface supports transport of mono or stereo audio data, with sample sizes of 8-, 16-, or 24-bits, up to at least CD Red Book audio quality rates. In addition to the I2S protocol, the hardware is configurable to also support the left justified audio format. As an I2S TX master, this interface requires three or four GPIO signals to interface to an external audio DAC:

• I2S_CLK – external I2S host clock (input)
• SCK – serial data clock (output)
• SD – serial audio data (output)
• WS – serial word select (output) When used with most audio DACs these GPIO are configured as LVTTL drivers/receivers

Datasheet 14 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Pinouts 3P i n o u t s Table 1 provides the pin list for PSoC™ 4100S Max for the 100-pin TQFP , 64-pin TQFP fine pitch (0.5-mm), and 48-pin TQFP packages. Table 1 Pin List for PSoC 4100S Max 100-TQFP 64-TQFP 48-TQFP 100-TQFP 64-TQFP 48-TQFP Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name 70 P0.7 46 P0.7 35 P0.7 10 VSSD 10 VSSD 10 VSSD 75 XRES 47 XRES 36 XRES 15 P10.3 – – – – 76 VCCD 48 VCCD 37 VCCD 16 P10.4 – – – – 77 VSSD 49 VSSD 38 VSSD 17 P10.5 – – – – 78 VDDD 50 VDDD 39 VDDD 18 P6.0 12 P6.0 – – 83 P5.0 51 P5.0 – – 23 P12.0 – – – – 84 P5.1 52 P5.1 – – 24 P12.1 – – – – 85 P5.2 53 P5.2 – – 25 P6.5 16 P6.5 – – 86 P5.3 54 P5.3 – – 26 VSSD 17 VSSD 10 VSSD 87 P5.4 – – – – 27 P3.0 18 P3.0 12 P3.0 91 VDDA 56 VDDA 40 VDDA 29 P3.2 20 P3.2 14 P3.2 92 VSSA 57 VSSA 41 VSSA 30 P3.3 21 P3.3 16 P3.3 97 P1.4 62 P1.4 46 P1.4 35 VDDD 26 VDDD 21 VDDD 98 P1.5 63 P1.5 47 P1.5 36 P11.0 – – – – 99 P1.6 64 P1.6 48 P1.6 37 P11.1 – – – – 100 P1.7 1 P1.7 1 P1.7 38 P11.2 – – – –

Datasheet 15 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Pinouts Descriptions of the power pins are as follows: VDDD: Power supply for the digital section. VDDA: Power supply for the analog section. VSSD, VSSA: Ground pins for the digital and analog sections respectively. VCCD: Regulated digital supply (1.8 V ±5%) GPIOs by package: 2 P2.0 2 P2.0 41 P11.5 – – – – 53 P5.6 35 P5.6 – – 42 VDDD 26 VDDD 21 VDDD 54 P5.7 36 P5.7 – – 45 P4.2 29 P4.2 24 P4.2 57 P7.2 – – – – 46 P4.3 30 P4.3 25 P4.3 58 P7.3 – – – – 50 P4.7 34 P4.7 –– 6 2 P 7 . 7 –– – – Note 1. Pin 11 is No-Connect (NC) on the 48-pin TQFP and 64-TQFP package. Pins 1, 52, 89, and 90 are NC on the 100-pin TQFP package. Number 100-TQFP 64-TQFP 48-TQFP GPIO 84 54 38 Table 1 Pin List for PSoC 4100S Max (continued) 100-TQFP 64-TQFP 48-TQFP 100-TQFP 64-TQFP 48-TQFP Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name

Datasheet 16 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Pinouts

3.1 Alternate pin functions

Each port pin has multiple alternate functions. These are defined in Table 2. The columns ACT #x and DS #y denote Active and Deep Sleep mode signals respectively. The notation for a signal is of the form “IPName[x].signal_name[u]:y” , where: IPName = Name of the block (such as tcpwm). x = Unique instance of the IP . Signal_name = Name of the signal. u = Signal number where there is more than one signal for a particular signal name. y = Designates copies of the signal name. For example, the name “tcpwm[0].line_compl[3]:4” indicates that this is instance 0 of a TCPWM block, the signal is “line_compl # 3 (complement of the line output)” , and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize use of on-chip resources. Table 2 Pin alternate function table for PSoC™ 4100S Max Name ACT #0 ACT #1 ACT #2 DS #0 DS #1 DS #2 DS #3 P0.2 – – canfd_rx[0]:1 lcd.com[2] lcd.seg[2] – scb[0].spi_select3:0 P0.3 – – canfd_tx[0]:1 lcd.com[3]:0 lcd.seg[3] – scb[2].spi_select0:1

Datasheet 17 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Pinouts Table 2 Pin alternate function table for PSoC™ 4100S Max (continued) Name ACT #0 ACT #1 ACT #2 DS #0 DS #1 DS #2 DS #3

Datasheet 18 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Pinouts Table 2 Pin alternate function table for PSoC™ 4100S Max (continued) Name ACT #0 ACT #1 ACT #2 DS #0 DS #1 DS #2 DS #3

Datasheet 19 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Pinouts P7.7 tcpwm.line_compl[3]:2 – – lcd.com[61]:0 lcd.seg[61]:0 – – Table 2 Pin alternate function table for PSoC™ 4100S Max (continued) Name ACT #0 ACT #1 ACT #2 DS #0 DS #1 DS #2 DS #3

Datasheet 20 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Pinouts Table 3 Analog and special functions Name Analog[2] SMARTIO MSC_SENSE MSC_SHIELD AMUXA AMUXB P0.0 lpcomp.in_p[0] msc[1].[4] – msc[1].sense:14 msc[1].s hield:14 amuxbus_a_msc1 amuxbus_b_msc1 P0.1 lpcomp.in_n[0] msc[1].s_pad[5] – msc[1].sense:15 msc[1].s hield:15 amuxbus_a_msc1 amuxbus_b_msc1 P0.2 lpcomp.in_p[1] msc[1].s_pad[6] – msc[1].sense:16 msc[1].s hield:16 amuxbus_a_msc1 amuxbus_b_msc1 P0.3 lpcomp.in_n[1] msc[1].s_pad[7] – msc[1].sense:17 msc[1].s hield:17 amuxbus_a_msc1 amuxbus_b_msc1 P0.4 wco.wco_in – msc[1].sense:18 msc[1].s hield:18 amuxbus_a_msc1 amuxbus_b_msc1 P0.5 wco.wco_out – msc[1].sense:19 msc[1].s hield:19 amuxbus_a_msc1 amuxbus_b_msc1 P0.6 exco.eco_in – msc[1].sense:20 msc[1].s hield:20 amuxbus_a_msc1 amuxbus_b_msc1 P0.7 exco.eco_out – msc[1].sense:21 msc[1].s hield:21 amuxbus_a_msc1 amuxbus_b_msc1 P8.0 –– msc[1].sense:22 msc[1].s hield:22 amuxbus_a_msc1 amuxbus_b_msc1 P8.1 –– msc[1].sense:23 msc[1].s hield:23 amuxbus_a_msc1 amuxbus_b_msc1 P8.2 –– msc[1].sense:24 msc[1].s hield:24 amuxbus_a_msc1 amuxbus_b_msc1 P8.3 –– msc[1].sense:25 msc[1].s hield:25 amuxbus_a_msc1 amuxbus_b_msc1 P9.0 msc[1].s_pad[8] – msc[1].sense:26 msc[1].s hield:26 amuxbus_a_msc1 amuxbus_b_msc1 P9.1 msc[1].s_pad[9] – msc[1].sense:27 msc[1].s hield:27 amuxbus_a_msc1 amuxbus_b_msc1 P9.2 msc[1].s_pad[10] – msc[1].sense:28 msc[1].s hield:28 amuxbus_a_msc1 amuxbus_b_msc1 P9.3 msc[1].s_pad[11] – msc[1].sense:29 msc[1].s hield:29 amuxbus_a_msc1 amuxbus_b_msc1 P5.0 msc[1].s_pad[12] – msc[1].sense:30 msc[1].s hield:30 amuxbus_a_msc1 amuxbus_b_msc1 P5.1 msc[1].cmod1pad – msc[1].sense:31 msc[1].shield:31 amuxbus_a_msc1 amuxbus_b_msc1 P5.2 msc[1].cmod2pad – msc[1].sense:3 msc[1].shield:3 amuxbus_a_msc1 amuxbus_b_msc1 P5.3 msc[1].s_pad[13] – msc[1].sense:2 msc[1].shield:2 amuxbus_a_msc1 amuxbus_b_msc1 P5.4 msc[1].s_pad[14] – msc[1].sense:1 msc[1].shield:1 amuxbus_a_msc1 amuxbus_b_msc1 P5.5 msc[1].s_pad[15] – msc[1].sense:0 msc[1].shield:0 amuxbus_a_msc1 amuxbus_b_msc1 P1.0 ctb0_oa0+ smartio[2].io[0] msc[0].sense:0 msc[0].shield:0 amuxbus_a _pass amuxbus_b_pass Note 2. All s_pad pins are CTRLMUX (control mux) pins.

Datasheet 21 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Pinouts P1.1 ctb0_oa0- smartio[2].io[1] msc[0].sense:1 msc[0].shield:1 amuxbus_a _pass amuxbus_b_pass P1.2 ctb0_oa0_out smartio[2].io[2] msc[0].sense:2 msc[0].shield:2 amuxbu s_a_pass amuxbus_b_pass P1.3 ctb0_oa1_out smartio[2].io[3] msc[0].sense:3 msc[0].shield:3 amuxbu s_a_pass amuxbus_b_pass P1.4 ctb0_oa1- smartio[2].io[4] msc[0].sense:4 msc[0].shield:4 amuxb us_a_pass amuxbus_b_pass P1.5 ctb0_oa1+ smartio[2].io[5] msc[0].sense:5 msc[0].shield:5 amuxb us_a_pass amuxbus_b_pass P1.6 ctb0_oa0+ smartio[2].io[6] msc[0].sense:6 msc[0].shield:6 amuxb us_a_pass amuxbus_b_pass P1.7 ctb0_oa1+ sar_ext_vref0 sar_ext_vref1 smartio[2].io[7] msc[0].sense:7 msc[0].shield:7 amuxbus_a_pass amuxbus_b_pass P2.0 sarmuxs[0] smartio[0].io[0] msc[0].sense:8 msc[0].shield:8 amux bus_a_pass amuxbus_b_pass P2.1 sarmuxs[1] smartio[0].io[1] msc[0].sense:9 msc[0].shield:9 amux bus_a_pass amuxbus_b_pass P2.2 sarmuxs[2] smartio[0].io[2] m sc[0].sense:10 msc[0].shield:10 am uxbus_a_pass amuxbus_b_pass P2.3 sarmuxs[3] smartio[0].io[3] m sc[0].sense:11 msc[0].shield:11 am uxbus_a_pass amuxbus_b_pass P2.4 sarmuxs[4] smartio[0].io[4] m sc[0].sense:12 msc[0].shield:12 am uxbus_a_pass amuxbus_b_pass P2.5 sarmuxs[5] smartio[0].io[5] m sc[0].sense:13 msc[0].shield:13 am uxbus_a_pass amuxbus_b_pass P2.6 sarmuxs[6] smartio[0].io[6] msc[0 ].sense:14 msc[0].shield:14 amuxbu s_a_pass amuxbus_b_pass P2.7 sarmuxs[7] smartio[0].io[7] msc[0 ].sense:15 msc[0].shield:15 amuxbu s_a_pass amuxbus_b_pass P10.0 –– msc[0].sense:16 msc[0].s hield:16 amuxbus_a_msc0 amuxbus_b_msc0 P10.1 –– msc[0].sense:17 msc[0].s hield:17 amuxbus_a_msc0 amuxbus_b_msc0 P10.2 –– msc[0].sense:18 msc[0].s hield:18 amuxbus_a_msc0 amuxbus_b_msc0 P10.3 –– msc[0].sense:19 msc[0].s hield:19 amuxbus_a_msc0 amuxbus_b_msc0 P10.4 –– msc[0].sense:20 msc[0].s hield:20 amuxbus_a_msc0 amuxbus_b_msc0 P10.5 –– msc[0].sense:21 msc[0].s hield:21 amuxbus_a_msc0 amuxbus_b_msc0 P6.0 –– msc[0].sense:22 msc[0].s hield:22 amuxbus_a_msc0 amuxbus_b_msc0 P6.1 –– msc[0].sense:23 msc[0].s hield:23 amuxbus_a_msc0 amuxbus_b_msc0 P6.2 –– msc[0].sense:24 msc[0].s hield:24 amuxbus_a_msc0 amuxbus_b_msc0 P6.3 –– msc[0].sense:25 msc[0].s hield:25 amuxbus_a_msc0 amuxbus_b_msc0 P6.4 –– msc[0].sense:26 msc[0].s hield:26 amuxbus_a_msc0 amuxbus_b_msc0 P12.0 –– msc[0].sense:27 msc[0].s hield:27 amuxbus_a_msc0 amuxbus_b_msc0 Table 3 Analog and special functions (continued) Name Analog[2] SMARTIO MSC_SENSE MSC_SHIELD AMUXA AMUXB

Datasheet 22 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Pinouts P12.1 –– msc[0].sense:28 msc[0].s hield:28 amuxbus_a_msc0 amuxbus_b_msc0 P6.5 msc[0].s_pad[0] – msc[0].sense:29 msc[0].s hield:29 amuxbus_a_msc0 amuxbus_b_msc0 P3.2 – smartio[1].io[2] msc[0].sense:32 msc[0].shield:32 amuxbus_a_msc0 amuxbus_b_msc0 P3.3 – smartio[1].io[3] msc[0].sense:33 msc[0].shield:33 amuxbus_a_msc0 amuxbus_b_msc0 P11.0 msc[0].spad[7] – msc[0].sense:38 msc[0].s hield:38 amuxbus_a_msc0 amuxbus_b_msc0 P11.1 msc[0].s_pad[8] – msc[0].sense:39 msc[0].s hield:39 amuxbus_a_msc0 amuxbus_b_msc0 P11.2 msc[0].s_pad[9] – msc[0].sense:40 msc[0].s hield:40 amuxbus_a_msc0 amuxbus_b_msc0 P11.3 msc[0].s_pad[10] – msc[0].sense:41 msc[0].s hield:41 amuxbus_a_msc0 amuxbus_b_msc0 P11.4 msc[0].s_pad[11] – msc[0].sense:42 msc[0].s hield:42 amuxbus_a_msc0 amuxbus_b_msc0 P11.5 –– msc[0].sense:43 msc[0].s hield:43 amuxbus_a_msc0 amuxbus_b_msc0 P4.0 msc[0].cmod3pad – msc[0].sense:44 msc[0].s hield:44 amuxbus_a_msc0 amuxbus_b_msc0 P4.1 msc[0].cmod4pad – msc[0].sense:45 msc[0].s hield:45 amuxbus_a_msc0 amuxbus_b_msc0 P4.2 msc[0].cmod1pad – msc[0].sense:46 msc[0].s hield:46 amuxbus_a_msc0 amuxbus_b_msc0 P4.3 msc[0].cmod2pad – msc[0].sense:47 msc[0].s hield:47 amuxbus_a_msc0 amuxbus_b_msc0 P4.4 msc[0].s_pad[12] – msc[0].sense:48 msc[0].s hield:48 amuxbus_a_msc0 amuxbus_b_msc0 P4.5 msc[0].s_pad[13] – msc[0].sense:49 msc[0].s hield:49 amuxbus_a_msc0 amuxbus_b_msc0 P4.6 msc[0].s_pad[14] – msc[0].sense:50 msc[0].s hield:50 amuxbus_a_msc0 amuxbus_b_msc0 P4.7 msc[0].s_pad[15] – msc[0].sense:51 msc[0].s hield:51 amuxbus_a_msc0 amuxbus_b_msc0 P5.6 msc[1].s_pad[0] – msc[1].sense:4 msc[1].shield:4 amuxbus_a_msc1 amuxbus_b_msc1 P5.7 msc[1].s_pad[1] – msc[1].sense:5 msc[1].shield:5 amuxbus_a_msc1 amuxbus_b_msc1 P7.0 msc[1].cmod3pad – msc[1].sense:6 msc[1].shield:6 amuxbus_a_msc1 amuxbus_b_msc1 P7.1 msc[1].cmod4pad – msc[1].sense:7 msc[1].shield:7 amuxbus_a_msc1 amuxbus_b_msc1 Table 3 Analog and special functions (continued) Name Analog[2] SMARTIO MSC_SENSE MSC_SHIELD AMUXA AMUXB

Datasheet 23 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Pinouts P7.2 –– msc[1].sense:8 msc[1].shield:8 amuxbus_a_msc1 amuxbus_b_msc1 P7.3 –– msc[1].sense:9 msc[1].shield:9 amuxbus_a_msc1 amuxbus_b_msc1 P7.4 –– msc[1].sense:10 msc[1].s hield:10 amuxbus_a_msc1 amuxbus_b_msc1 P7.5 –– msc[1].sense:11 msc[1].s hield:11 amuxbus_a_msc1 amuxbus_b_msc1 P7.6 msc[1].s_pad[2] – msc[1].sense:12 msc[1].s hield:12 amuxbus_a_msc1 amuxbus_b_msc1 P7.7 msc[1].s_pad[3] – msc[1].sense:13 msc[1].s hield:13 amuxbus_a_msc1 amuxbus_b_msc1 Table 3 Analog and special functions (continued) Name Analog[2] SMARTIO MSC_SENSE MSC_SHIELD AMUXA AMUXB

Datasheet 24 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Power 4P o w e r Figure 4 shows the set of power supply pins as implemented for PSoC™ 4100S Max. The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog circuits run directly from the VDDA input. Figure 4 Power supply connections There are two distinct modes of operation. In Mode 1, the supply voltage range is 2.0 V to 5.5 V (unregulated externally; internal regulator operational). In Mode 2, the supply range is1.8 V ±5% (externally regulated; 1.71 to 1.89, internal regulator bypassed). 4.1 Mode 1: 2.0 V to 5.5 V external supply In this mode, PSoC™ 4100S Max is powered by an external power supply that can be anywhere in the range of 2.0 to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered from a battery system that starts at 3.5 V and works down to 2.0 V. In this mode, the internal regulator of PSoC™ 4100S Max supplies the internal logic and its output is connected to the VCCD pin. The VCCD pin must be bypassed to ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to anything else. 4.2 Mode 2: 1.8 V ±5% external supply In this mode, PSoC™ 4100S Max is powered by an external power supply that must be within the range of 1.71 to 1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins are shorted together and bypassed. The internal regulator can be disabled in the firmware. Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is to use a capacitor in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. Analog Domain VDDA VSSA VDDA

1.8 Volt

Datasheet 26 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5 Electrical specifications

5.1 Absolute maximum ratings

5.2 Device-level specifications

All specifications are valid for –40°C  TA  105°C and TJ  125°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Table 4 Absolute maximum ratings [3] Spec ID# Parameter Description Min Typ Max Unit Details/ conditions SID1 V DDD_ABS Digital supply relative to VSS –0.5 – 6 V – SID2 V CCD_ABS Direct digital core voltage input relative to VSS –0.5 – 1.95 V – SID3 V GPIO_ABS GPIO voltage –0.5 – V DD+0.5 V – SID4 I GPIO_ABS Maximum current per GPIO –25 – 25 mA – SID5 I GPIO_injection GPIO injection current, Max for V IH > VDDD, and Min for VIL < VSS –0.5 – 0.5 mA Current injected per pin BID44 ESD_HBM Electrostatic discharge human body model 2200 – – V – BID45 ESD_CDM Electrostatic discharge charged device model 500 – – V – BID46 LU Pin current for latch-up –140 – 140 mA – Table 5 DC specifications Typical values measured at VDD = 3.3 V and 25°C. Spec ID# Parameter Description Min Typ Max Unit Details/ conditions SID53 V DD Power supply input voltage 2.0 – 5.5 V Internally regulated supply SID255 V DD Power supply input voltage CCD = VDDD = VDDA) 1.71 – 1.89 V Internally unregulated supply SID54 V CCD Output voltage (for core logic) – 1.8 – V – SID55 C EFC External regulator voltage bypass –0 . 1 – µF X5R ceramic or better SID56 C EXC Power supply bypass capacitor – 1 – µF X5R ceramic or better SID10 I DD5 Execute from flash; CPU at 6 MHz – 2.1 – mA – SID16 I DD8 Execute from flash; CPU at 24 MHz – 5.8 – mA Note 3. Usage above the absolute maximum conditions listed in Table 4 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.

Datasheet 27 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications SID19 I DD11 Execute from flash; CPU at 48 MHz – 11.2 – mA – Sleep Mode, VDDD = 2.0 V to 5.5 V (Regulator on) SID22 I DD17 I2C wakeup WDT , and Compar- ators on – 1.8 2.4 mA 6 MHZ SID25 I DD20 I2C wakeup, WDT , and Compar- ators on – 2.3 3.0 mA 12 MHZ Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed) SID28 I DD23 I2C wakeup, WDT , and Compar- ators on –1 . 8 2 . 4 m A 6 MHZ SID28A I DD23A I2C wakeup, WDT , and Compar- ators on –2 . 3 3 . 0 m A 12 MHZ Deep Sleep Mode, VDD = 2.0 V to 3.6 V (Regulator on) SID30 I DD25 I2C wakeup and WDT on; T = –40°C to 60°C –3 . 7 4 0 µA T = –40°C to 60°C SID31 I DD26 I2C wakeup and WDT on – 3.7 125 µA Max is at 3.6 V and 85°C Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on) SID33 I DD28 I2C wakeup and WDT on; T = –40°C to 60°C – 3.7 40 µA T = –40°C to 60°C SID34 I DD29 I2C wakeup and WDT on – 3.7 148 µA Max is at 5.5 V and 85 °C Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed) SID36 I DD31 I2C wakeup and WDT on; T = –40°C to 60°C – 2.5 60 µA T = –40°C to 60°C SID37 I DD32 I2C wakeup and WDT on – 3.2 180 µA Max is at 1.89 V and 85°C XRES Current SID307 I DD_XR Supply current while XRES asserted – 2 5 mA Table 6 AC specifications Spec ID# Parameter Description Min Typ Max Unit Details/ conditions SID48 F CPU CPU frequency DC – 48 MHz 1.71 VDD 5.5 SID49[4] TSLEEP Wakeup from Sleep mode – 0 – µs – SID50[4] TDEEPSLEEP Wakeup from Deep Sleep mode – 35 – µs – Table 5 DC specifications (continued) Typical values measured at VDD = 3.3 V and 25°C. Spec ID# Parameter Description Min Typ Max Unit Details/ conditions Note 4. Guaranteed by characterization.

Datasheet 28 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.2.1 GPIO

Table 7 GPIO DC specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID57 V IH [5] Input voltage high threshold 0.7 VDDD ––V CMOS Input SID58 V IL Input voltage low threshold – – 0.3  VDDD V CMOS Input SID241 V IH [5] LVTTL input, VDDD < 2.7 V 0.7 VDDD ––V – SID242 V IL LVTTL input, VDDD < 2.7 V – – 0.3  VDDD V – SID243 V IH [5] LVTTL input, VDDD  2.7 V 2.0 – – V – SID244 V IL LVTTL input, VDDD  2.7 V – – 0.8 V – SID59 V OH Output voltage high level V DDD –0.6 – – V IOH = 4 mA at 3 V VDDD SID60 V OH Output voltage high level V DDD –0.5 – – V IOH = 1 mA at 1.8 V VDDD SID61 V OL Output voltage low level – – 0.6 V IOL = 4 mA at 1.8 V VDDD SID62 V OL Output voltage low level – – 0.6 V IOL = 10 mA at 3 V VDDD SID62A V OL Output voltage low level – – 0.4 V IOL = 3 mA at 3 V VDDD SID63 R PULLUP Pull-up resistor 3.5 5.6 8.5 k Ω – SID64 R PULLDOWN Pull-down resistor 3.5 5.6 8.5 k Ω – SID65 I IL Input leakage current (absolute value) –– 2 n A 25 °C, VDDD = 3.0 V SID66 C IN Input capacitance – – 7 pF – SID67[6] VHYSTTL Input hysteresis LVTTL 25 40 – mV VDDD  2.7 V SID68[6] VHYSCMOS Input hysteresis CMOS 0.05 × VDDD –– m V VDD < 4.5 V SID68A[6] VHYSCMOS5V5 Input hysteresis CMOS 200 – – mV VDD > 4.5 V SID69[6] IDIODE Current through protection diode to V DD/VSS – – 100 µA – SID69A[6] ITOT_GPIO Maximum total source or sink chip current – – 200 mA – SID69B I TOT_GPIO_CS Maximum total source or sink chip current when doing CAPSENSE™ measure- ments –– 4 0 m A Notes 5. V IH must not exceed VDDD + 0.2 V. 6. Guaranteed by characterization.

Datasheet 29 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.2.2 XRES

Table 8 GPIO AC specifications (Guaranteed by characterization) Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID70 T RISEF Rise time in fast strong mode 2 – 12 ns 3.3 V VDDD, Cload = 25 pF SID71 T FALLF Fall time in fast strong mode 2 – 12 ns 3.3 V VDDD, Cload = 25 pF SID72 T RISES Rise time in slow strong mode 10 – 60 ns 3.3 V VDDD, Cload = 25 pF SID73 T FALLS Fall time in slow strong mode 10 – 60 ns 3.3 V VDDD, Cload = 25 pF SID74 F GPIOUT1 GPIO FOUT; 3.3 V  VDDD 5.5 V Fast strong mode ––3 3 M H z 90/10%, 25 pF load, 60/40 duty cycle SID75 F GPIOUT2 GPIO FOUT; 1.71 VVDDD 3.3 V Fast strong mode – – 16.7 MHz 90/10%, 25 pF load, 60/40 duty cycle SID76 F GPIOUT3 GPIO FOUT; 3.3 V VDDD 5.5 V Slow strong mode –– 7M H z 90/10%, 25 pF load, 60/40 duty cycle SID245 F GPIOUT4 GPIO FOUT; 1.71 V VDDD  3.3 V Slow strong mode. –– 3 . 5 M H z 90/10%, 25 pF load, 60/40 duty cycle SID246 F GPIOIN GPIO input operating frequency;

1.71 V V

DDD 5.5 V ––4 8 M H z 90/10% VIO Table 9 XRES DC specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID77 VIH Input voltage high threshold 0.7 × VDDD – – V CMOS Input SID78 VIL Input voltage low threshold – – 0.3  VDDD V SID79 RPULLUP Pull-up resistor – 60 – kΩ – SID80 CIN Input capacitance – – 7 pF – SID81[7] VHYSXRES Input voltage hysteresis – 100 – mV Typical hysteresis is 200 mV for VDD > 4.5 V SID82 IDIODE Current through protection diode to V DD/VSS – – 100 µA – Table 10 XRES AC specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID83[7] TRESETWIDTH Reset pulse width 1 – – µs – BID194[7] TRESETWAKE Wake-up time from reset release –– 2 . 7 m s – Note 7. Guaranteed by characterization.

Datasheet 30 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.3 Analog peripherals

5.3.1 CTBm opamp

Table 11 CTBm opamp specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions IDD Opamp block current, External load SID269 I DD_HI power = hi – 1100 1900 µA – SID270 I DD_MED power = med – 550 1020 µA – SID271 I DD_LOW power = lo – 150 370 µA – GBW Load = 50 pF, 0.1 mA, VDDA = 2.7 V SID272 G BW_HI power = hi 6 – – MHz Input and output are 0.2 V to VDDA-0.2 V SID273 G BW_MED power = med 3 – – MHz Input and output are

0.2 V to V

DDA-0.2 V SID274 G BW_LO power = lo – 1 – MHz Input and output are DDA-0.2 V IOUT_MAX VDDA = 2.7 V, 500 mV from rail SID275 I OUT_MAX_HI power = hi 10 – – mA Output is 0.5 V to V DDA -0.5 V SID276 I OUT_MAX_MID power = mid 10 – – mA Output is 0.5 V to V DDA -0.5 V SID277 I OUT_MAX_LO power = lo – 5 – mA Output is 0.5 V to V DDA -0.5 V IOUT VDDA = 1.71 V, 500 mV from rail SID278 I OUT_MAX_HI power = hi 4 – – mA Output is 0.5 V to V DDA -0.5 V SID279 IOUT_MAX_MID power = mid 4 –– m A Output is 0.5 V to VDDA-0.5 V SID280 IOUT_MAX_LO power = lo – 2 –m A Output is 0.5 V to VDDA-0.5 V IDD_Int Opamp block current internal load SID269_I IDD_HI_Int power = hi – 1500 1700 µA – SID270_I IDD_MED_Int power = med – 700 980 µA – SID271_I IDD_LOW_Int power=lo –– 405 µA – GBW VDDA = 2.7 V –– – – SID272_I GBW_HI_Int power=hi 8 –– MHz Output is 0.25 V to VDDA-0.25 V General opamp specs for both internal and external modes SID281 VIN Charge-pump on, VDDA = 2.7 V 0.05 – VDDA-0.2 V –

Datasheet 31 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications SID282 VCM Charge-pump on, VDDA = 2.7 V 0.05 – VDDA-0.2 V – VOUT VDDA = 2.7 V SID283 VOUT_1 power=hi, Iload=10 mA 0.5 – VDDA -0.5 V – SID284 VOUT_2 power=hi, Iload=1 mA 0.2 – VDDA -0.2 V – SID285 VOUT_3 power=med, Iload=1 mA 0.2 – VDDA -0.2 V – SID286 VOUT_4 power=lo, Iload=0.1 mA 0.2 – VDDA -0.2 V – SID288 VOS_TR Offset voltage, trimmed –1.0 0.5 1.0 mV High mode, input 0 V to VDDA-0.2 V SID288A VOS_TR Offset voltage, trimmed – 1 – mV Medium mode, input 0V t o VDDA-0.2 V SID288B VOS_TR Offset voltage, trimmed – 2 – mV Low mode, input 0 V to VDDA-0.2 V SID290 VOS_DR_TR Offset voltage drift, trimmed –10 3 10 µV/°C High mode SID290A VOS_DR_TR Offset voltage drift, trimmed – 10 – µV/°C Medium mode SID290B VOS_DR_TR Offset voltage drift, trimmed – 10 – µV/°C Low mode SID291 CMRR DC 70 80 – dB Input is 0 V to VDDA-0.2 V, Output is 0.2 V to VDDA-0.2 V SID292 PSRR At 1 kHz, 10-mV ripple 70 85 – dB VDDD = 3.6 V, high-power mode, input is 0.2 V to V DDA-0.2 V Noise SID294 VN2 Input-referred, 1 kHz, power = Hi – 72 – nV/rtH z Input and output are at 0.2 V to V DDA-0.2 V SID295 VN3 Input-referred, 10 kHz, power = Hi – 28 – nV/rtH z Input and output are at 0.2 V to V DDA-0.2 V SID296 VN4 Input-referred, 100 kHz, power = Hi – 15 – nV/rtH z Input and output are at 0.2 V to V DDA-0.2 V SID297 CLOAD Stable up to max. load. Performance specs at 50 pF. –– 125 pF – Table 11 CTBm opamp specifications (continued) Spec ID# Parameter Description Min Typ Max Unit Details/conditions

Datasheet 32 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications SID298 SLEW_RATE Cload = 50 pF, Power = High, V DDA = 2.7 V 4 –– V/µs – SID299 T_OP_WAKE From disable to enable, no external RC dominating –– 25 µs – SID299A OL_GAIN Open Loop Gain – 90 – dB – COMP_MODE Comparator mode; 50 mV drive, Trise=Tfall (approx.) SID300 TPD1 Response time; power = hi – 150 – ns Input is 0.2 V to VDDA-0.2 V SID301 TPD2 Response time; power = med – 500 – ns Input is 0.2 V to VDDA-0.2 V SID302 TPD3 Response time; power = lo – 2500 – ns Input is 0.2 V to VDDA-0.2 V SID303 VHYST_OP Hysteresis – 10 – mV – SID304 WUP_CTB Wake-up time from Enabled to Usable –– 25 µs – Deep Sleep Mode Mode 2 is lowest current range. Mode 1 has higher GBW. SID_DS_1 IDD_HI_M1 Mode 1, High current – 1400 – µA 25°C SID_DS_2 IDD_MED_M1 Mode 1, Medium current – 700 – µA 25°C SID_DS_3 IDD_LOW_M1 Mode 1, Low current – 200 – µA 25°C SID_DS_4 IDD_HI_M2 Mode 2, High current – 120 – µA 25°C SID_DS_5 IDD_MED_M2 Mode 2, Medium current – 60 – µA 25°C SID_DS_6 IDD_LOW_M2 Mode 2, Low current – 15 – µA 25°C SID_DS_7 GBW_HI_M1 Mode 1, High current – 4 – MHz 20-pF load, no DC load 0.2 V to V DDA-0.2 V SID_DS_8 GBW_MED_M1 Mode 1, Medium current – 2 – MHz 20-pF load, no DC load 0.2 V to V DDA-0.2 V SID_DS_9 GBW_LOW_M1 Mode 1, Low current – 0.5 – MHz 20-pF load, no DC load 0.2 V to VDDA-0.2 V SID_DS_10 GBW_HI_M2 Mode 2, High current – 0.5 – MHz 20-pF load, no DC load 0.2 V to V DDA-0.2 V Table 11 CTBm opamp specifications (continued) Spec ID# Parameter Description Min Typ Max Unit Details/conditions

Datasheet 33 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications SID_DS_11 GBW_MED_M2 Mode 2, Medium current – 0.2 – MHz 20-pF load, no DC load 0.2 V to V DDA-0.2 V SID_DS_12 GBW_Low_M2 Mode 2, Low current – 0.1 – MHz 20-pF load, no DC load 0.2 V to V DDA-0.2 V SID_DS_13 VOS_HI_M1 Mode 1, High current – 5 – mV With trim 25°C, 0.2 V to VDDA-0.2 V SID_DS_14 VOS_MED_M1 Mode 1, Medium current – 5 – mV With trim 25°C, 0.2 V to VDDA-0.2 V SID_DS_15 VOS_LOW_M1 Mode 1, Low current – 5 – mV With trim 25°C, 0.2 V to VDDA-0.2 V SID_DS_16 VOS_HI_M2 Mode 2, High current – 5 – mV With trim 25°C, 0.2V to VDDA-0.2 V SID_DS_17 VOS_MED_M2 Mode 2, Medium current – 5 – mV With trim 25°C, 0.2 V to VDDA-0.2 V SID_DS_18 VOS_LOW_M2 Mode 2, Low current – 5 – mV With trim 25°C, 0.2 V to VDDA-0.2 V SID_DS_19 IOUT_HI_M1 Mode 1, High current – 10 – mA Output is 0.5 V to VDDA-0.5 V SID_DS_20 IOUT_MED_M1 Mode 1, Medium current – 10 – mA Output is 0.5 V to VDDA-0.5 V SID_DS_21 IOUT_LOW_M1 Mode 1, Low current – 4 – mA Output is 0.5 V to VDDA-0.5 V SID_DS_22 IOUT_HI_M2 Mode 2, High current – 1 – mA – SID_DS_23 IOUT_MED_M2 Mode 2, Medium current – 1 – mA – SID_DS_24 IOUT_LOW_M2 Mode 2, Low current – 0.5 – mA – Table 11 CTBm opamp specifications (continued) Spec ID# Parameter Description Min Typ Max Unit Details/conditions

Datasheet 34 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.3.2 Comparator

Table 12 Comparator DC specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID84 V OFFSET1 Input offset voltage, Factory trim – – ±10 mV – SID85 V OFFSET2 Input offset voltage, Custom trim – –± 4 m V – SID86 V HYST Hysteresis when enabled –1 0 3 5 m V – SID87 V ICM1 Input common mode voltage in normal mode 0 –V DDD-0.1 V Modes 1 and 2 SID247 V ICM2 Input common mode voltage in low power mode 0 –V DDD V – SID247A V ICM3 Input common mode voltage in ultra low power mode 0 –V DDD-1.15 V VDDD ≥ 2.2 V at –40°C SID88 C MRR Common mode rejection ratio 50 – –d B VDDD ≥ 2.7V SID88A C MRR Common mode rejection ratio 42 – –d B VDDD ≤ 2.7V SID89 I CMP1 Block current, normal mode – – 400 µA – SID248 I CMP2 Block current, low power mode – – 100 µA – SID259 I CMP3 Block current in ultra low-power mode – –6 µ A VDDD ≥ 2.2 V at –40°C SID90 Z CMP DC Input impedance of comparator 35 – –M Ω – Table 13 Comparator AC specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID91 T RESP1 Response time, normal mode, 50-mV overdrive – 38 110 ns – SID258 T RESP2 Response time, low power mode, 50-mV overdrive – 70 200 ns – SID92 T RESP3 Response time, ultra-low power mode, 200-mV overdrive – 2.3 15 µs VDDD ≥ 2.2 V at –40°C Note 8. Guaranteed by characterization.

Datasheet 35 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.3.3 Temperature sensor

5.3.4 SAR ADC

Table 14 Temperature sensor specifications Spec ID# Parameter Description Min Typ Max Unit Details/ conditions SID93 T SENSACC Temperature sensor accuracy[9] –5 ±1 5 °C 0 to +85°C Table 15 SAR ADC specifications Spec ID# Parameter Description Min Typ Max Unit Details/ conditions SAR ADC DC Specifications SID94 A_RES Resolution – – 12 bits – SID95 A_CHNLS_S Number of channels - single ended – – 16 – SID96 A-CHNKS_D Number of channels - differential – – 4 Diff inputs use neighboring I/O SID97 A-MONO Monotonicity Yes – SID98 A_GAINERR Gain error – – ±0.125 % With external reference SID99 A_OFFSET Input offset voltage – – ±2.3 mV Measured with 1-V reference SID100 A_ISAR Current consumption – – 1 mA – SID101 A_VINS Input voltage range - single ended V SS –V DDA V – SID102 A_VIND Input voltage range - differential V SS –V DDA V – SID103 A_INRES Input resistance – – 2.2 K Ω – SID104 A_INCAP Input capacitance – – 10 pF – SID260 VREFSAR Trimmed internal reference to SAR 1.188 1.2 1.212 V – SAR ADC AC specifications SID106 A_PSRR Power supply rejection ratio 70 – – dB – SID107 A_CMRR Common mode rejection ratio 66 – – dB Measured at 1 V SID108 A_SAMP Sample rate – – 1 Msps – SID109 A_SNR Signal-to-noise and distortion ratio (SINAD) 64 – – dB FIN = 10 kHz SID110 A_BW Input bandwidth without aliasing – – A_samp/2 kHz – SID111 A_INL Integral non linearity –3 – 3 LSB – SID112 A_DNL Differential non linearity –1 – 3L S B – SID113 A_THD Total harmonic distortion –– –62 dB Fin = 10 kHz SID261 F SARINTREF SAR operating speed without external reference bypass –– 100 ksps 12-bit resolution Note 9. Characterized for typical silicon, not measured in production.

Datasheet 36 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.3.5 CAPSENSE™ block (MSC)

Table 16 MSC specifications Spec ID# Parameter Description Min Typ Max Units Details/conditions SID.MSC.1 V DD_RIPPLE Max allowed ripple on power supply, 1 kHz to

10 MHz

– – ±50 mV VDD ≥ 2 V (with ripple), 25°C TA, Sensitivity ≥ 50 counts/0.1 pF, 2 pF < Cs < 50 pF SID.MSC.2 V DD_RIP- PLE_1.8 Max allowed ripple on power supply, 1kHz to – – ±25 mV VDD > 1.75 V (with ripple), 25°C TA, Sensitivity ≥ 50 counts/0.1 pF, 2 pF < Cs < 50 pF SID.MSC.x1 Fmod Clock frequency – – 48 MHz VDD ≥ 2V SID.MSC.x2 Fmod_1.8 Clock frequency – – 36 MHz VDD < 2 V SID.MSC.3 I MSC_VDDA Current drawn by block from VDDA – 650 – µA Current drawn from VDDA during a scan. CSD scan with Cs≈20 pF, VDDA= 3.3 V, Fmod = 498 MHz, Fs = 1 MHz. SID.MSC.5 V MSC Voltage range of operation 1.71 – 5.5 V SID.MSC.6 SNR Ratio of counts of finger to noise. Guaranteed by characterization 5–– R a t i o Capacitance range of 5 to 50 pF, sensitivity ≥ 50 counts/pF. VDDA ≥ 2V. SID.MSC.7 CMOD External modulator capacitor. –2 . 2– n F 5-V rating, X7R or NP0 cap. SID.MSC.x7 CMOD tolerance External modulator capacitor. –5 – 5 % Tolerance on CMOD capacitor. SID.MSC.x8 F sense_Cap- Sense Capacitive sense frequency range 45 6000 kHz – SID.MSC.9 Noise floor for self-cap mode Capacitive noise sensi- tivity (CNS) for CSD scans – – 0.1 fF-rms With 8 pF self-capacitance. Typical conditions. SID.MSC.9A Noise floor for mutual-cap mode Capacitive noise sensi- tivity (CNS) for CSX scans – – 0.03 fF-rms With 1.5 pF mutual-capacitance. Typical conditions. SID.MSC.10 Input range for self-cap mode Input capacitance range for self-cap mode 2– 200 pF SID.MSC.10A Input range for self-cap mode Input capacitance range for mutual-cap mode 0.5 – 30 pF

Datasheet 37 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.4 Digital peripherals

5.4.1 Timer Counter Pulse-width Modulator (TCPWM)

Table 17 TCPWM specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID.TCPWM.1 ITCPWM1 Block current consumption at 3 MHz –– 4 5 μA All modes (TCPWM) SID.TCPWM.2 ITCPWM2 Block current consumption at 12 MHz – – 155 μA All modes (TCPWM) SID.TCPWM.2A ITCPWM3 Block current consumption at 48 MHz – – 650 μA All modes (TCPWM) SID.TCPWM.3 TCPWMFREQ Operating frequency – – Fc MHz Fc max = CLK_SYS Maximum = 48 MHz SID.TCPWM.4 TPWMENEXT Input trigger pulse width 2/Fc – – ns For all trigger events[10] SID.TCPWM.5 TPWMEXT Output trigger pulse widths 2/Fc – – ns Minimum possible width of Overflow, Underflow, and CC (Counter equals Compare value) outputs SID.TCPWM.5A TCRES Resolution of counter 1/Fc – – ns Minimum time between successive counts SID.TCPWM.5B PWMRES PWM resolution 1/Fc – – ns Minimum pulse width of PWM Output SID.TCPWM.5C QRES Quadrature inputs resolution 1/Fc – – ns Minimum pulse width between Quadrature phase inputs

Datasheet 38 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.4.2 I 2C

5.4.3 SPI

Table 18 Fixed I 2C DC specifications[10] Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID149 I I2C1 Block current consumption at 100 kHz –– 5 0 µA – SID150 I I2C2 Block current consumption at 400 kHz – – 135 µA – SID151 I I2C3 Block current consumption at 1 Mbps – – 310 µA – SID151H I I2C5 Block current consumption at 3.4 Mbps – – 1000 µA – SID152 I I2C4 Block current in Deep Sleep mode –1 – µA – Table 19 Fixed I 2C AC specifications[10] Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID153 F I2C1 Bit rate – – 3.4 Msps HS I2C Slave mode Table 20 SPI DC specifications [10] Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID163 ISPI1 Block current consumption at 1 Mbps – – 360 µA – SID164 ISPI2 Block current consumption at 4 Mbps – – 560 µA – SID165 ISPI3 Block current consumption at 8 Mbps – – 600 µA – Table 21 SPI AC specifications [10] Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID166 FSPI SPI Operating frequency (Master; 6X Oversampling) –– 8 M H z – Fixed SPI Master Mode AC specifications SID167 TDMO MOSI Valid after SClock driving edge –– 1 5 n s – SID168 TDSI MISO Valid before SClock capturing edge 20 – – ns Full clock, late MISO sampling SID169 THMO Previous MOSI data hold time 0– – n s Referred to Slave capturing edge Fixed SPI Slave Mode AC specifications SID170 TDMI MOSI Valid before Sclock Capturing edge 40 – – ns – Note 10.Guaranteed by characterization.

Datasheet 39 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.4.4 UART

5.4.5 LCD direct drive

SID171 TDSO MISO Valid after Sclock driving edge –– 42 + 3*Tcpu ns TCPU = 1/FCPU SID171A TDSO_EXT MISO Valid after Sclock driving edge in Ext. Clk mode –– 4 8 n s – SID172 THSO Previous MISO data hold time 0– – n s – SID172A TSSELSSCK SSEL Valid to first SCK Valid edge 100 – – ns – Table 22 UART DC specifications [10] Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID160 I UART1 Block current consumption at 100 Kbps –– 5 5 µ A – SID161 I UART2 Block current consumption at 1000 Kbps – – 312 µA – Table 23 UART AC specifications [10] Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID162 F UART Bit rate – – 1 Mbps – Table 24 LCD direct drive DC specifications [10] Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID155 C LCDCAP LCD capacitance per segment/common driver – 500 5000 pF – SID156 LCD OFFSET Long-term segment offset – 20 – mV – SID157 I LCDOP1 LCD system operating current Vbias = 5 V – 2– m A 32  4 segments at

50 Hz 25°C

LCD system operating current Vbias = 3.3 V – 2– m A 32  4 segments at Table 25 LCD Direct Drive AC specifications [11] Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID159 F LCD LCD frame rate 10 50 150 Hz – Table 21 SPI AC specifications [10] (continued) Spec ID# Parameter Description Min Typ Max Unit Details/conditions

Datasheet 40 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.5 Memory

Table 26 Flash DC specifications Spec ID# Parameter Description Min Typ Max Unit Details/ conditions SID173 V PE Erase and program voltage 1.71 – 5.5 V – SID173A I PW Page write current at 16 MHz – – 3.5 mA 5.5V VDDD Table 27 Flash AC specifications Spec ID# Parameter Description Min Typ Max Unit Details/ conditions SID174 T ROWWRITE [12] Row (block) write time (erase and program) – – 20 ms Row (block) = 256 bytes SID175 T ROWERASE [12] Row erase time – – 16 ms – SID176 T ROWPROGRAM [12] Row program time after erase – – 4 ms – SID178 T BULKERASE [12] Bulk erase time (384 KB) – – 35 ms – SID180[11] TDEVPROG [12] Total device program time – – 7 Seconds – SID181[11] FEND Flash endurance 100 K – – Cycles – SID182[11] FRET Flash retention. TA  55°C,

100 K P/E cycles 20 – – Years –

SID182A[11] – Flash retention. TA  85°C,

10 K P/E cycles 10 – – Years –

SID182B – Flash retention. TA  105°C, 10K P/E cycles,  three years at TA ≥ 85°C 10 – 20 Years – SID256 TWS48 Number of Wait states at

48 MHz 2– – – CPU execution

SID257 TWS24 Number of Wait states at

24 MHz 1– – – CPU execution

11.Guaranteed by characterization. 12.It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations may be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.

Datasheet 41 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.6 System resources

5.6.1 Power-on reset (POR)

5.6.2 SWD Interface

Table 28 Power-on reset specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID.CLK#6 SR_POWER_UP Power supply slew rate 1 – 67 V/ms At power-up and power-down SID185[11] VRISEIPOR Rising trip voltage 0.80 – 1.5 V – SID186[11] VFALLIPOR Falling trip voltage 0.70 – 1.4 V – Table 29 Brown-out Detect (BOD) for V CCD Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID190[13] VFALLPPOR BOD trip voltage in active and sleep modes 1.48 – 1.62 V – SID192[13] VFALLDPSLP BOD trip voltage in Deep Sleep 1.11 – 1.5 V – Table 30 SWD Interface specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID213 F_SWDCLK1 3.3 V  VDD  5.5 V – – 14 MHz SWDCLK ≤ 1/3 CPU clock frequency SID214 F_SWDCLK2 1.71 V  VDD  3.3 V – – 7 MHz SWDCLK ≤ 1/3 CPU clock frequency SID215[14] T_SWDI_SETUP T = 1/f SWDCLK 0.25*T – – ns – SID216[14] T_SWDI_HOLD T = 1/f SWDCLK 0.25*T – – ns – SID217[14] T_SWDO_VALID T = 1/f SWDCLK – – 0.5*T ns – SID217A[14] T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns – Notes 13.Guaranteed by characterization. 14.Guaranteed by design.

Datasheet 42 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.6.3 Internal main oscillator

Table 31 IMO DC specifications (Guaranteed by design) Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID218 I IMO1 IMO operating current at – – 250 µA – SID219 I IMO2 IMO operating current at

24 MHz

– – 180 µA – Table 32 IMO AC specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID223 FIMOTOL1 Frequency variation at 24, 32, and 48 MHz (trimmed) – – ±2.0 % At –40°C to 85°C, for industrial temperature range and original extended industrial range parts SID223A [15] – – ±2.5 % At –40°C to 105°C, for all extended industrial temperature range parts SID223B [15] – – ±2.0 % At –30°C to 105°C, for enhanced IMO extended industrial temperature range parts SID223C [15] – – ±1.5 % At –20°C to 105°C, for enhanced IMO extended industrial temperature range parts SID223D [15] – – ±1.25 % At 0°C to 85°C, for enhanced IMO extended industrial temperature range parts SID226 T STARTIMO IMO startup time – – 7 µs – SID228 T JITRMSIMO2 RMS jitter at 24 MHz – 145 – ps – Note 15.The enhanced IMO extended temperature range parts replace the original extended industrial temperature range parts. For details on how to identify enhanced IMO extended temperature range parts, refer to KBA235887.

Datasheet 43 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.6.4 Internal low-speed oscillator

5.6.5 Watch crystal oscillator (WCO)

5.6.6 External clock

Table 33 ILO DC specifications (Guaranteed by design) Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID231 I ILO1 ILO operating current – 0.3 1.05 µA – Table 34 ILO AC specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID234[16] TSTARTILO1 ILO startup time – – 2 ms – SID236[16] TILODUTY ILO duty cycle 40 50 60 % – SID237 F ILOTRIM1 ILO frequency range 20 40 80 kHz – Table 35 WCO specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID398 F WCO Crystal frequency – 32.768 – kHz – SID399 F TOL Frequency tolerance – 50 250 ppm With 20-ppm crystal SID400 ESR Equivalent series resistance – 50 – k Ω – SID401 PD Drive Level – – 1 µW – SID402 T START Startup time – – 500 ms – SID403 CL Crystal load capacitance 6 – 12.5 pF – SID404 C0 Crystal shunt capacitance – 1.35 – pF – SID405 I WCO1 Operating current (high power mode) –– 8 µ A – Table 36 External clock specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID305[17] ExtClkFreq External clock input frequency 0 – 48 MHz – SID306[17] ExtClkDuty Duty cycle; measured at V DD/2 45 – 55 % – Notes 16.Guaranteed by design. 17.Guaranteed by characterization.

Datasheet 44 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.6.7 External crystal oscillator and PLL

5.6.8 System clock

Table 37 External crystal oscillator (ECO) specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID316[18] IECO1 Block current – – 1.5 mA – SID317[18] FECO Crystal frequency range 4 – 33 MHz – Table 38 PLL specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID410 IDD_PLL_48 In = 3 MHz, Out = 48 MHz – 530 610 µA – SID411 IDD_PLL_24 In = 3 MHz, Out = 24 MHz – 300 405 µA – SID412 FPLLIN PLL input frequency 1 – 48 MHz – SID413 FPLLINT PLL intermediate frequency; prescaler out 1 – 3 MHz SID414 FPLLVCO VCO output frequency before post-divide 22.5 – 104 MHz SID415 DIVVCO VCO Output post-divider range; PLL output frequency is FPPLVCO/DIVVCO 1–8 SID416 PLLLocktime Lock time at startup – – 250 µs – SID417 Jperiod_1 Period jitter for VCO ≥ 67 MHz – – 150 ps Guaranteed by design SID416A Jperiod_2 Period jitter for VCO ≤ 67 MHz – – 200 ps Guaranteed by design Table 39 System clock specifications Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID262[18] TCLKSWITCH System clock source switching time 3– 4 P e r i o d s – Note 18.Guaranteed by characterization.

Datasheet 45 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Electrical specifications

5.6.9 Smart I/O

Table 40 Smart I/O pass-through time (Delay in bypass mode) Spec ID# Parameter Description Min Typ Max Unit Details/conditions SID252 PRG_BYPASS Max delay added by Smart I/O in bypass mode –– 1 . 6n s – Table 41 CAN FD Spec ID# Parameter Description Min Typ Max Unit Details/Conditions SID.CAN.1 F CANFD CAN FD peak frequency – – 5 MHz – SID.CAN.2 I CANFD CAN FD block current – 0.24 0.3 mA – Table 42 I2S transmitter Spec ID# Parameter Description Min Typ Max Unit Details/conditions I2S Specifications. Master mode TX only. SID413 I2S_WORD Length of I2S Word 8 – 24 bits – SID414M I2S_WS_U Word clock frequency – – 48 kHz 3.072 MHz bit clock with 32-bit word SID415S I2S_SCK Output clock frequency – – 2.304 MHz 24 bits L-R channels at 48 kHz SID437U TD_WS_U WS transition delay from Falling Edge of SCK -20 – 20 ns – SID438U TD_SDO SDO transition delay from Falling Edge of SCK -20 – 20 ns – SID443 T SCKCY SCK Bit clock duty cycle 45 – 55 % – SID445 EXTCLK_SOC External clock frequency 1.024 – 48 MHz – SID446 EXTCLK_DUTY External clock frequency 45 – 55 % –

Datasheet 46 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU

Ordering information

6 Ordering information

The marketing part numbers for the PSoC™ 4100S Max devices are listed in Table 43. Table 43 PSoC™ 4100S Max ordering information Category MPN Max CPU speed (MHz) Features Packages Temperature range (°C) Flash (KB) SRAM (KB) Opamp (CTBm) CAPSENSE™ 12-bit SAR ADC Segment LCD drive SAR ADC sample rate LP comparators TCPWM blocks SCB blocks CAN controller CRYPTO I2S Smart IOs GPIO 48-TQFP 64-TQFP (0.5mm pitch) 100-TQFP 4148 CY8C4148AZI-S548 48 256 32 2 – 1 ✔ 1 Msps 2 8 5 – – – 24 84 – – ✔ -40 to 85 CY8C4148AZI-S553 48 256 32 2 2 1 ✔ 1 Msps 2 8 4 – – ✔ 24 38 ✔ –– -40 to 85 CY8C4148AZI-S555 48 256 32 2 2 1 ✔ 1 Msps 2 8 5 – – ✔ 24 54 – ✔ – -40 to 85 CY8C4148AZI-S558 48 256 32 2 2 1 ✔ 1 Msps 2 8 5 – – ✔ 24 84 – – ✔ -40 to 85 CY8C4148AZQ-S558 48 256 32 2 2 1 ✔ 1 Msps 2 8 5 – – ✔ 24 84 – – ✔ -40 to 105 CY8C4148AZI-S583 48 256 32 2 2 1 ✔ 1 Msps 2 8 4 – ✔✔ 24 38 ✔ –– -40 to 85 CY8C4148AZI-S585 48 256 32 2 2 1 ✔ 1 Msps 2 8 5 – ✔✔ 24 54 – ✔ – -40 to 85 CY8C4148AZI-S588 48 256 32 2 2 1 ✔ 1 Msps 2 8 5 – ✔✔ 24 84 – – ✔ -40 to 85 CY8C4148AZI-S593 48 256 32 2 2 1 ✔ 1 M s p s 2 841 ✔✔ 24 38 ✔ –– -40 to 85 CY8C4148AZI-S595 48 256 32 2 2 1 ✔ 1 M s p s 2 851 ✔✔ 24 54 – ✔ – -40 to 85 CY8C4148AZI-S598 48 256 32 2 2 1 ✔ 1 M s p s 2 851 ✔✔ 24 84 – – ✔ -40 to 85 4149 CY8C4149AZI-S543 48 384 32 2 – 1 ✔ 1 Msps 2 8 5 – – – 24 38 ✔ –– -40 to 85 CY8C4149AZI-S545 48 384 32 2 – 1 ✔ 1 Msps 2 8 5 – – – 24 54 – ✔ – -40 to 85 CY8C4149AZQ-S545 48 384 32 2 – 1 ✔ 1 Msps 2 8 5 – – – 24 54 – ✔ – -40 to 105 CY8C4149AZI-S548 48 384 32 2 – 1 ✔ 1 Msps 2 8 5 – – – 24 84 – – ✔ -40 to 85 CY8C4149AZQ-S548 48 384 32 2 – 1 ✔ 1 Msps 2 8 5 – – – 24 84 – – ✔ -40 to 105 CY8C4149AZI-S553 48 384 32 2 2 1 ✔ 1 Msps 2 8 5 – – ✔ 24 38 ✔ –– -40 to 85 CY8C4149AZI-S555 48 384 32 2 2 1 ✔ 1 Msps 2 8 5 – – ✔ 24 54 – ✔ – -40 to 85 CY8C4149AZQ-S555 48 384 32 2 2 1 ✔ 1 Msps 2 8 5 – – ✔ 24 54 – ✔ – -40 to 105 CY8C4149AZI-S558 48 384 32 2 2 1 ✔ 1 Msps 2 8 5 – – ✔ 24 84 – – ✔ -40 to 85 CY8C4149AZQ-S558 48 384 32 2 2 1 ✔ 1 Msps 2 8 5 – – ✔ 24 84 – – ✔ -40 to 105 CY8C4149AZI-S565 48 384 32 2 – 1 ✔ 1 Msps 2 8 5 1 – – 24 54 – ✔ – -40 to 85 CY8C4149AZI-S568 48 384 32 2 – 1 ✔ 1 Msps 2 8 5 1 – – 24 84 – – ✔ -40 to 85 CY8C4149AZI-S575 48 384 32 2 2 1 ✔ 1 M s p s 2 851– ✔ 24 54 – ✔ – -40 to 85 CY8C4149AZI-S578 48 384 32 2 2 1 ✔ 1 M s p s 2 851– ✔ 24 84 – – ✔ -40 to 85 CY8C4149AZI-S583 48 384 32 2 2 1 ✔ 1 Msps 2 8 4 – ✔✔ 24 38 ✔ –– -40 to 85 CY8C4149AZI-S585 48 384 32 2 2 1 ✔ 1 Msps 2 8 5 – ✔✔ 24 54 – ✔ – -40 to 85 CY8C4149AZI-S588 48 384 32 2 2 1 ✔ 1 Msps 2 8 5 – ✔✔ 24 84 – – ✔ -40 to 85

Datasheet 47 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU The nomenclature used in the preceding table is based on the following part numbering convention: 4149 CY8C4149AZI-S593 48 384 32 2 2 1 ✔ 1 M s p s 2 841 ✔✔ 24 38 ✔ –– -40 to 85 CY8C4149AZQ-S593 48 384 32 2 2 1 ✔ 1 M s p s 2 841 ✔✔ 24 38 ✔ –– -40 to 105 CY8C4149AZI-S595 48 384 32 2 2 1 ✔ 1 M s p s 2 851 ✔✔ 24 54 – ✔ – -40 to 85 CY8C4149AZQ-S595 48 384 32 2 2 1 ✔ 1 M s p s 2 851 ✔✔ 24 54 – ✔ – -40 to 105 CY8C4149AZI-S598 48 384 32 2 2 1 ✔ 1 M s p s 2 851 ✔✔ 24 84 – – ✔ -40 to 85 CY8C4149AZQ-S598 48 384 32 2 2 1 ✔ 1 M s p s 2 851 ✔✔ 24 84 – – ✔ -40 to 105 Field Description Values Meaning CY8C Infineon prefix 4A r c h i t e c t u r e 4 PSoC™ 4 AF a m i l y 1 4100 family B CPU speed 2 24 MHz 4 48 MHz CF l a s h c a p a c i t y 4 16 KB 5 32 KB 6 64 KB 7 128 KB 8 256 KB 9 384 KB AX TQFP (0.8-mm pitch) AZ TQFP (0.5-mm pitch) LQ QFN PV SSOP FN CSP F Temperature range I Industrial Q Extended Industrial S Series designator S PSoC™ 4 S-series M PSoC™ 4 M-series L PSoC™ 4 L-series BL PSoC™ 4 Bluetooth® LE-series XYZ Attributes code 000-999 Code of feature set in the specific family Table 43 PSoC™ 4100S Max ordering information (continued) Category MPN Max CPU speed (MHz) Features Packages Temperature range (°C) Flash (KB) SRAM (KB) Opamp (CTBm) CAPSENSE™ 12-bit SAR ADC Segment LCD drive SAR ADC sample rate LP comparators TCPWM blocks SCB blocks CAN controller CRYPTO I2S Smart IOs GPIO 48-TQFP 64-TQFP (0.5mm pitch) 100-TQFP

Datasheet 48 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU The following is an example of a part number: CY8C 4 A B C DE F – S XYZ Infineon prefix Architecture Family within architecture CPU speed Temperature range Package code Flash capacity Attributes code Example 4: PSoC™ 4 1: 4100 family 4: 48 MHz I: Industrial AZ/AX: TQFP 5: 32 KB Series designator

Datasheet 49 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Packaging 7P a c k a g i n g The PSoC™ 4100S Max is offered in 100-TQFP , 64-TQFP Fine pitch, and 48-TQFP packages. Table 44 provides the package dimensions and Infineon drawing numbers. Table 44 Package list Spec ID# Package Description Package Dwg BID34 100-pin TQFP 14 × 14 × 1.4-mm height with 0.5-mm pitch 51-85048 BID27 64-pin TQFP 10 × 10 × 1.6-mm height with 0.5-mm pitch 51-85051 BID34A 48-pin TQFP 7 × 7 × 1.4-mm height with 0.5-mm pitch 51-85135 Table 45 Package thermal characteristics Parameter Description Package Min Typ Max Units TA Operating ambient temperature – –40 25 105 °C TJ Operating junction temperature – –40 25 125 °C Table 46 Solder reflow peak temperature Package Maximum peak temperature Maximum time at peak temperature All 260°C 30 seconds Table 47 Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-020 Package MSL All MSL 3

Datasheet 50 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Packaging

7.1 Package diagrams

Figure 6 100-pin 14 × 14 × 1.4-mm TQFP package (0.5-mm Pitch) outline Figure 7 64-pin 10 × 10 × 1.6-mm TQFP package (0.5-mm Pitch) outline 51-85048 *K 51-85051 *D

Datasheet 51 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Packaging Figure 8 48-Pin 7 × 7 × 1.4-mm TQFP package (0.5-mm Pitch) outline 51-85135 *C

Datasheet 52 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Acronyms 8A c r o n y m s Table 48 Acronyms used in this document Acronym Description abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm data transfer bus ALU arithmetic logic unit AMUXBUS analog multiplexer bus API application programming interface APSR application program status register Arm® advanced RISC machine, a CPU architecture ATM automatic thump mode BW bandwidth CAN Controller Area Network, a communications protocol CMRR common-mode rejection ratio CPU central processing unit CRC cyclic redundancy check, an error-checking protocol DAC digital-to-analog converter, see also IDAC, VDAC DFB digital filter block DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. DMIPS Dhrystone million instructions per second DMA direct memory access, see also TD DNL differential nonlinearity, see also INL DNU do not use DR port write data registers DSI digital system interconnect DWT data watchpoint and trace ECC error correcting code ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory EMI electromagnetic interference EMIF external memory interface EOC end of conversion EOF end of frame EPSR execution program status register ESD electrostatic discharge ETM embedded trace macrocell

Datasheet 53 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Acronyms FIR finite impulse response, see also IIR FPB flash patch and breakpoint FS full-speed GPIO general-purpose input/output, applies to a PSoC™ pin HVI high-voltage interrupt, see also LVI, LVD IC integrated circuit IDAC current DAC, see also DAC, VDAC IDE integrated development environment I2C, or IIC Inter-Integrated Circuit, a communications protocol IIR infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO INL integral nonlinearity, see also DNL I/O input/output, see also GPIO, DIO, SIO, USBIO IPOR initial power-on reset IPSR interrupt program status register IRQ interrupt request ITM instrumentation trace macrocell LCD liquid crystal display LIN Local Interconnect Network, a communications protocol. LR link register LUT lookup table LVD low-voltage detect, see also LVI LVI low-voltage interrupt, see also HVI LVTTL low-voltage transistor-transistor logic MAC multiply-accumulate MCU microcontroller unit MISO master-in slave-out NC no connect NMI nonmaskable interrupt NRZ non-return-to-zero NVIC nested vectored interrupt controller NVL nonvolatile latch, see also WOL opamp operational amplifier PAL programmable array logic, see also PLD PC program counter PCB printed circuit board PGA programmable gain amplifier Table 48 Acronyms used in this document (continued) Acronym Description

Datasheet 54 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Acronyms PHUB peripheral hub PHY physical layer PICU port interrupt control unit PLA programmable logic array PLD programmable logic device, see also PAL PLL phase-locked loop PMDD package material declaration data sheet POR power-on reset PRES precise power-on reset PRS pseudo random sequence PS port read data register PSoC™ Programmable System-on-Chip™ PSRR power supply rejection ratio PWM pulse-width modulator RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square RTC real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC/CT switched capacitor/continuous time SCL I2C serial clock SDA I2C serial data S/H sample and hold SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced features. See GPIO. SOC start of conversion SOF start of frame SPI Serial Peripheral Interface, a communications protocol SR slew rate SRAM static random access memory SRES software reset SWD serial wire debug, a test protocol SWV single-wire viewer TD transaction descriptor, see also DMA THD total harmonic distortion Table 48 Acronyms used in this document (continued) Acronym Description

Datasheet 55 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Acronyms TIA transimpedance amplifier TRM technical reference manual TTL transistor-transistor logic TX transmit UART Universal Asynchronous Transmitter Receiver, a communications protocol UDB universal digital block USB Universal Serial Bus USBIO USB input/output, PSoC™ pins used to connect to a USB port VDAC voltage DAC, see also DAC, IDAC WDT watchdog timer WOL write once latch, see also NVL WRES watchdog timer reset XRES external reset I/O pin XTAL crystal Table 48 Acronyms used in this document (continued) Acronym Description

Datasheet 56 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Document conventions

9 Document conventions

9.1 Units of measure

°C degrees Celsius dB decibel fF femto farad Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz k kilo ohm ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz M mega-ohm Msps megasamples per second µA microampere µF microfarad µH microhenry µs microsecond µV microvolt µW microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt  ohm pF picofarad ppm parts per million ps picosecond s second sps samples per second sqrtHz square root of hertz V volt

Datasheet 57 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU Errata

10 Errata

This section describes the errata for the PSoC™ 4100S Max. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document to the device’s data sheet for a complete functional description. Contact your local sales representative if you have questions.

10.1 Part numbers affected

10.2 PSoC™ 4100S Max qualification status

10.3 PSoC™ 4100S Max errata summary

The following table defines the errata applicability to available family devices. When using the CTRLMUX sensor connection method, the Rx nodes of mutual cap sensors may not get initialized to VDD/2 as expected, leading to improper Cmod initialization and improper raw counts, unless enough number of init sub-conversions are configured. In some cases, the raw count value may saturate to the maximum value. Note: The raw count output for the same Rx node when scanned again for a different Tx (i.e. a touchpad where a sensor is connected to the same Rx but another Tx) will be correct because the Rx would have been properly initialized to V DD/2 during the previous sensor scan connected to this Rx. This defect does not impact the raw count when using the AMUXBUS sensor connection method as the sensor Rx does get initialized to VDDA/2 during Cmod initialization. Part number Device characteristics CY8C414X-S5XX PSoC™ 4100S Max Items PSoC™ 4100S Max Silicon revision Fix status 1. Mutual cap sensors may not get initialized correctly in CTRLMUX connection method All Pre-production silicon None planned 1. Mutual cap sensors may not get initialized correctly in CTRLMUX connection method Problem definition Incorrect raw count may be obtained in CTRLMUX mode Parameters affected Raw count Trigger condition(s) CTRLMUX mode Scope of impact Incorrect sensor reading Workaround One of the following workarounds may be used. 1. Increase the number of init sub-conversions to allow correct Cmod initialization. 2. Group all CSX sensors to consecutive slots. Set the inactive sensor connection to VDD/2 and add an extra scan for the first CSX sensor, ignore the raw count result of this extra scan. 3. Use the AMUXBUS sensor connection method. Please refer to the PSoC™ 4 and PSoC™ 6 CAPSENSE™ design guide for details on how to implement the above workarounds. Fix status No fix planned.

Datasheet 58 002-30372 Rev. *E 2022-10-14 PSoC™ 4 MCU: PSoC™ 4100S Max Based on Arm® Cortex®-M0+ CPU

Revision history

revision Date Description of changes *E 2022-10-14 Release to the web

81726 Munich, Germany

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