AN77759

CY8C58LP INFINEON | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 140

Technical content

Datasheet sections

• 4.1 Arm Cortex-M3 CPU
• 4.2 Cache Controller
• 4.3 DMA and PHUB
• 4.4 Interrupt Controller
• 5.1 Static RAM
• 5.2 Flash Program Memory
• 5.3 Flash Security
• 5.4 EEPROM
• 5.5 Nonvolatile Latches (NVLs)
• 5.6 External Memory Interface
• 5.7 Memory Map
• 6.1 Clocking System
• 6.2 Power System
• 6.3 Reset
• 6.4 I/O System and Routing
• 7.1 Example Peripherals
• 7.2 Universal Digital Block
• 7.3 UDB Array Description
• 7.4 DSI Routing Interface Description
• 7.5 CAN
• 7.6 USB
• 7.7 Timers, Counters, and PWMs
• 7.8 I2C
• 7.9 Digital Filter Block
• 8.1 Analog Routing
• 8.2 Delta-sigma ADC
• 8.3 Successive Approximation ADC
• 8.4 Comparators
• 8.5 Opamps
• 8.6 Programmable SC/CT Blocks
• 8.7 LCD Direct Drive
• 8.8 CapSense
• 8.9 Temp Sensor
• 8.10 DAC
• 8.11 Up/Down Mixer
• 8.12 Sample and Hold
• 9.1 JTAG Interface
• 9.2 SWD Interface
• 9.3 Debug Features
• 9.4 Trace Features
• 9.5 SWV and TRACEPORT Interfaces
• 9.6 Programming Features
• 9.7 Device Security
• 9.8 CSP Package Bootloader
• 10.1 Documentation
• 10.2 Online
• 10.3 Tools
• 11.1 Absolute Maximum Ratings
• 11.3 Power Regulators
• 11.4 Inputs and Outputs
• 11.5 Analog Peripherals
• 11.6 Digital Peripherals
• 11.7 Memory
• 11.8 PSoC System Resources
• 11.9 Clocking
• 12.1 Part Numbering Conventions
• 15.1 Units of Measure

www.infineon.com Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering.

PSoC® 5LP: CY8C58LP Family Datasheet Programmable System-on-Chip (PSoC®) Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-84932 Rev. *N Revised November 27, 2019 General Description PSoC® 5LP is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a microcontroller on a single chip. The PSoC 5LP architecture boosts performance through:  32-bit Arm Cortex-M3 core plus DMA controller and digital filter processor, at up to 80 MHz  Ultra low power with industry's widest voltage range  Programmable digital and analog peripherals enable custom functions  Flexible routing of any analog or digital peripheral function to any pin PSoC devices employ a highly configurable system-on-chip archit ecture for embedded control desig n. They integrate configurable analog and digital circuits, controlled by an on-chip microcont roller. A single PSoC device can integrate as many as 100 digit al and analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality.

Features

 Operating characteristics  Voltage range: 1.71 to 5.5 V, up to 6 power domains  Temperature range (ambient): –40 to 85 °C [1] Extended temperature parts: –40 to 105 °C  DC to 80-MHz operation  Power modes

• Active mode 3.1 mA at 6 MHz, and 15.4 mA at 48 MHz
• 2-µA sleep mode
• 300-nA hibernate mode with RAM retention  Boost regulator from 0.5-V input up to 5-V output  Performance  32-bit Arm Cortex-M3 CPU, 32 interrupt inputs  24-channel direct memory access (DMA) controller  24-bit 64-tap fixed-point digital filter processor (DFB)  Memories  Up to 256 KB program flash, with cache and security features  Up to 32 KB additional flash for error correcting code (ECC)  Up to 64 KB RAM  2 KB EEPROM  Digital peripherals  Four 16-bit timer, counter, and PWM (TCPWM) blocks  I2C, 1 Mbps bus speed  USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral inter- face (TID#10840032) using internal oscillator[2]  Full CAN 2.0b, 16 Rx, 8 Tx buffers  20 to 24 universal digital blocks (UDB), programmable to create any number of functions:
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• I 2C, UART, SPI, I2S, LIN 2.0 interfaces
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generators
• Quadrature decoders
• Gate-level logic functions  Programmable clocking  3- to 74-MHz internal oscillator, 1% accuracy at 3 MHz  4- to 25-MHz external crystal oscillator  Internal PLL clock generation up to 80 MHz  Low-power internal oscillator at 1, 33, and 100 kHz  32.768-kHz external watch crystal oscillator  12 clock dividers routable to any peripheral or I/O  Analog peripherals  Configurable 8- to 20-bit delta-sigma ADC  Up to two 12-bit SAR ADCs  Four 8-bit DACs  Four comparators  Four opamps  Four programmable analog blocks, to create:
• Programmable gain amplifier (PGA)
• Transimpedance amplifier (TIA)
• M i x e r
• Sample and hold circuit  CapSense® support, up to 62 sensors  1.024 V ±0.1% internal voltage reference  Versatile I/O system  46 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs)  Up to eight performance I/O (SIO) pins
• 25 mA current sink
• Programmable input threshold and output high voltages
• Can act as a general-purpose comparator
• Hot swap capability and overvoltage tolerance  Two USBIO pins that can be used as GPIOs  Route any digital or analog peripheral to any GPIO  LCD direct drive from any GPIO, up to 46 × 16 segments  CapSense support from any GPIO  1.2-V to 5.5-V interface voltages, up to four power domains  Programming, debug, and trace  JTAG (4-wire), serial wire debug (SWD) (2-wire), single wire viewer (SWV), and Traceport (5-wire) interfaces  Arm debug and trace modules embedded in the CPU core  Bootloader programming through I2C, SPI, UART, USB, and other interfaces  Package options: 68-pin QFN, 100-pin TQFP , and 99-pin CSP  Development support with free PSoC Creator™ tool  Schematic and firmware design support  Over 100 PSoC Components™ integrate multiple ICs and system interfaces into one PSoC. Components are free embedded ICs represented by icons. Drag and drop component icons to design systems in PSoC Creator.  Includes free GCC compiler, supports Keil/Arm MDK compiler  Supports device programming and debugging Notes 1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. This feature on selec t devices only. See Ordering Information on page 127 for details.

In addition, PSoC Creator includes a device selection tool.

1. Drag and drop component icons to build your hardware
2. Codesign your application firmware with the PSoC hardware,
3. Configure components using the configuration tools
4. Explore the library of 100+ components
5. Review component datasheets

Figure 1. Multiple-Sensor Example Project in PSoC Creator

Document Number: 001-84932 Rev. *N Page 4 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 1. Architectural Overview Introducing the CY8C58LP family of ultra low power, flash Progr ammable System-on-Chip (PSoC) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5LP platform. The CY8C58LP family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexibl e analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure 1-1. Simplified Block Diagram Figure 1-1 illustrates the major components of the CY8C58LP family. They are:  Arm Cortex-M3 CPU subsystem  Nonvolatile subsystem  Programming, debug, and test subsystem  Inputs and outputs  Clocking  Power  Digital subsystem  Analog subsystem PSoC’s digital subsystem p rovides half of its unique configurability. It connects a digital signal from any peripheral to any pin through the digital syst em interconnect (DSI). It also provides functional flexibility through an array of small, fast, low power UDBs. PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. You can also easily create a digital circuit usi ng boolean primitives by means of graphical design entry. Each UDB contains programmable array logic (PAL)/programmable logic device (PLD) functionality, together with a small state machine engine to support a wide variety of peripherals. Digital Filter Block LCD Direct Drive CapSense Temperature Sensor 4 x Opamp ADCs 4 x DAC 1 x Del Sig ADC 4 x SC/ CT Blocks (TIA, PGA, Mixer etc) 4 x CMP Program Debug & Trace Boundary Scan Program & Debug Cortex M3 CPU Interrupt Controller PHUB DMA Cache Controller SRAM FLASH EEPROM EMIF Digital Interconnect Analog Interconnect 1.71 to 5.5 V 0. 5 to 5.5 V ( Optional) 4- 25 MHz ( Optional) Xtal Osc

32.768 KHz

( Optional) RTC Timer IMO Clock Tree WDT and Wake ILO Clocking System

1.8 V LDO

Universal Digital Block Array (24 x UDB) 4 x Timer Counter PWM FS USB 2.0 UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDBUDB UDB UDB UART Logic 12- Bit PWM I2 C S l a v e 8- Bit SPI 12- Bit SPI Logic 8- Bit Timer 16- Bit PRS UDB 8- Bit Timer Quadrature Decoder 16- Bit PWM Sequencer U sag e E xam p le fo r UDB UDBUDB UDBUDB UDBUDB UDBUDB 22 Ω Memory System CPU System Analog System System Bus Digital SystemSystem Wide Resources CAN 2.0

Document Number: 001-84932 Rev. *N Page 5 of 139 PSoC® 5LP: CY8C58LP Family Datasheet In addition to the flexibility of the UDB array, PSoC also provides configurable digital blocks targeted at specific functions. For the CY8C58LP family, these blocks can include four 16-bit timers, counters, and PWM blocks; I 2C slave, master, and multimaster; Full-Speed USB; and Full CAN 2.0. For more details on the peripherals see the Example Peripherals on page 40 of this datasheet. For information on UDBs, DSI, and other digital blocks, see the Digital Subsystem on page 40 of this datasheet. PSoC’s analog subsystem is t he second half of its unique configurability. All analog performance is based on a highly accurate absolute voltage refe rence with less than 0.1% error over temperature and voltage. The configurable analog subsystem includes:  Analog muxes  Comparators  Analog mixers  Voltage references  ADCs  DACs  Digital filter block (DFB) All GPIO pins can route analog signals into and out of the device using the internal analog bus. This allows the device to interface up to 62 discrete analog signals. One of the ADCs in the analog s u b s y s t e m i s a f a s t , a c c u r a t e , c o n f i g u r a b l e d e l t a - s i g m a A D C with these features:  Less than 100-µV offset  A gain error of 0.2%  Integral non linearity (INL) less than ±2 LSB  Differential non linearity (DNL) less than ±1 LSB  SINAD better than 84 dB in 16-bit mode This converter addresses a wide variety of precision analog applications including some of the most demanding sensors. The CY8C58LP family also offers up to two SAR ADCs. Featuring 12-bit conversions at up to 1 M samples per second, they also offer low nonlinearity and offset errors and SNR better than 70 dB. They are well-suited for a variety of higher speed analog applications. The output of any of the ADCs can optionally feed the programmable DFB via DMA without CPU intervention. You can configure the DFB to perform IIR and FIR digital filters and several user defined custom functions. The DFB can implement filters with up to 64 taps. It can perform a 48-bit multiply-accumulate (MAC) operation in one clock cycle. Four high-speed voltage or current DACs support 8-bit output signals at an update rate of up to 8 Msps. They can be routed out of any GPIO pin. You can c reate higher resolution voltage PWM DAC outputs using the UDB array. This can be used to create a pulse width modulated (PWM) DAC of up to 10 bits, at up to 48 kHz. The digital DACs in each UDB support PWM, PRS, or delta-sigma algorithms with programmable widths. In addition to the ADCs, DACs, and DFB, the analog subsystem provides multiple:  Comparators  Uncommitted opamps  Configurable switched capacitor/continuous time (SC/CT) blocks. These support:  Transimpedance amplifiers  Programmable gain amplifiers  Mixers  Other similar analog components See the “Analog Subsystem” section on page 51 of this datasheet for more details. PSoC’s CPU subsystem is built around a 32-bit three-stage pipelined Arm Cortex-M3 proce ssor running at up to 80 MHz. The Cortex-M3 includes a tightly integrated nested vectored interrupt controller (NVIC) and various debug and trace modules. The overall CPU subsystem inc ludes a DMA controller, flash cache, and RAM. The NVIC provides low latency, nested interrupts, and tail-chaining of interrupts and other features to increase the efficiency of interrupt handling. The DMA controller enables peripherals to exchange data without CPU involvement. This allows the CPU to run slower (saving power) or use those CPU cycles to improve the performance of firmware algorithms. The flash cache also reduces system power consumption by allowing less frequent flash access. PSoC’s nonvolatile subsystem cons ists of flash, byte-writeable EEPROM, and nonvolatile configuration options. It provides up to 256 KB of on-chip flash. The CPU can reprogram individual blocks of flash, enabling boot loaders. You can enable an ECC for high reliability applications. A powerful and flexible protection model secures the user's sensitive information, allowing selective memory block locking for read and write protection. Two KB of byte-writable EEPROM is available on-chip to store application data. Additionally, selected configuration options such as boot speed and pin drive mode are stored in nonvolatile memory. This allows settings to activate immediately after POR. The three types of PSoC I/O are extremely flexible. All I/Os have many drive modes that are set at POR. PSoC also provides up to four I/O voltage domains through the V DDIO pins. Every GPIO has analog I/O, LCD drive, CapSense, flexible interrupt generation, slew rate control, and digital I/O capability. The SIOs on PSoC allow VOH to be set independently of VDDIO when used as outputs. When SIOs are in input mode they are high impedance. This is true even when the device is not powered or when the pin voltage goes above the supply voltage. This makes the SIO ideally suited for use on an I 2C bus where the PSoC may not be powered when other devices on the bus are. The SIO pins also have high current sink capability for applications such as LED drives. The programmable input threshold feature of the SIO can be used to make the SIO function as a general purpose analog comparator. For devices with FS USB, the USB physical interface is also provided (USBIO). When not using USB, these pins may also be used for limited digital functionality and device programming. All the features o f the PSoC I/Os are covered in detail in the I/O System and Routing o n p a g e 3 3 o f t h i s datasheet.

Document Number: 001-84932 Rev. *N Page 7 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 2-3. 68-pin QFN Part Pinout [3] (TRACEDATA[2], GPIO) P2[6] (TRACEDATA[3], GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] VSSB IND VBOOST VBAT VSSD XRES (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (Configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (NTRST, GPIO) P1[5] VDDIO1 (GPIO) P1[6] VCCD (OPAMP3+, GPIO) P3[3] (GPIO) P1[7] (SIO) P12[6] (SIO) P12[7] (USBIO, D+, SWDIO) P15[6] (USBIO, D-, SWDCK) P15[7] VDDD VSSD (MHZ XTAL: XO, GPIO) P15[0] (MHZ XTAL: XI, GPIO) P15[1] (IDAC1, GPIO) P3[0] (IDAC3, GPIO) P3[1] (OPAMP3-, EXTREF1, GPIO) P3[2] (OPAMP1-, GPIO) P3[4] (OPAMP1+, GPIO) P3[5] P0[3] (GPIO, OPAMP0-, EXTREF0) P0[2] (GPIO, OPAMP0+, SAR1 EXTREF) P0[1] (GPIO, OPAMP0OUT) P0[0] (GPIO, OPAMP2OUT) P12[3] (SIO) P12[2] (SIO) VSSD VDDA VSSA VCCA P15[3] (GPIO, KHZ XTAL: XI) P15[2] (GPIO, KHZ XTAL: XO) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, 12C1: SCL) P3[7] (GPIO, OPAMP3OUT) P3[6] (GPIO, OPAMP1OUT) VDDIO3 P2[5] (GPIO, TRACEDATA[1]) VDDIO2 P2[4] (GPIO, TRACEDATA[0]) P2[3] (GPIO, TRACECLK) P2[2] (GPIO) P2[1] (GPIO) P2[0] (GPIO) P15[5] (GPOI) P15[4] (GPIO) VDDD VSSD VCCD P0[7] (GPIO, IDAC2) P0[6] (GPIO, IDAC0) P0[5] (GPIO, OPAMP2-) P0[4] (GPIO, OPAMP2+, SAR0 EXTREF) VDDIO0 QFN (TOP VIEW) Lines show VDDIO to I/O supply association [4] [4] Notes 3. The center pad on the QFN package should be connected to digi tal ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices. 4. Pins are Do Not Us e (DNU) on devices without USB. The pin must be left floating.

Document Number: 001-84932 Rev. *N Page 8 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 2-4. 100-pin TQFP Part Pinout Table 2-1. VDDIO and Port Pin Associations VDDIO Port Pins VDDD P15[7:6] (USB D+, D-) TQFP (TRACEDATA[1], GPIO) P2[5] (TRACEDATA[2], GPIO) P2[6] (TRACEDATA[3], GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] (GPIO) P6[4] (GPIO) P6[5] (GPIO) P6[6] (GPIO) P6[7] VSSB IND VBOOST VBAT VSSD XRES (GPIO) P5[0] (GPIO) P5[1] (GPIO) P5[2] (GPIO) P5[3] (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (Configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (NTRST, GPIO) P1[5] VDDIO1 (GPIO) P5[7] NC (OPAMP3-, EXTREF1, GPIO) P3[2] (GPIO) P1[6] (GPIO) P1[7] (SIO) P12[6] (SIO) P12[7] (GPIO) P5[4] (GPIO) P5[5] (GPIO) P5[6] (USBIO, D+, SWDIO) P15[6] (USBIO, D-, SWDCK) P15[7] VDDD VSSD VCCD NC (MHZ XTAL: XO, GPIO) P15[0] (MHZ XTAL: XI, GPIO) P15[1] (IDAC1, GPIO) P3[0] (IDAC3, GPIO) P3[1] (OPAMP3+, GPIO) P3[3] (OPAMP1-, GPIO) P3[4] (OPAMP1+, GPIO) P3[5] VDDIO3 VDDIO0 P0[3] (GPIO, OPAMP0-, EXTREF0) P0[2] (GPIO, OPAMP0+, SAR1 EXTREF) P0[1] (GPIO, OPAMP0OUT) P0[0] (GPIO, OPAMP2OUT) P4[1] (GPIO) P4[0] (GPIO) P12[3] (SIO) P12[2] (SIO) VSSD VDDA VSSA VCCA NC NC NC NC NC NC P15[3] (GPIO, KHZ XTAL: XI) P15[2] (GPIO, KHZ XTAL: XO) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, I2C1: SCL) P3[7] (GPIO, OPAMP3OUT) P3[6] (GPIO, OPAMP1OUT) VDDIO2 P2[4] (GPIO, TRACEDATA[0]) P2[3] (GPIO, TRACECLK) P2[2] (GPIO) P2[1] (GPIO) P2[0] (GPIO) P15[5] (GPIO) P15[4] (GPIO) P6[3] (GPIO) P6[2] (GPIO) P6[1] (GPIO) P6[0] (GPIO) VDDD VSSD VCCD P4[7] (GPIO) P4[6] (GPIO) P4[5] (GPIO) P4[4] (GPIO) P4[3] (GPIO) P4[2] (GPIO) P0[7] (GPIO, IDAC2) P0[6] (GPIO, IDAC0) P0[5] (GPIO, OPAMP2-) P0[4] (GPIO, OPAMP2+, SAR0 EXTREF) 100 Lines show VDDIO to I/O supply association [6] [6] Note 5. Pins are Do Not Us e (DNU) on devices without USB. The pin must be left floating.

Document Number: 001-84932 Rev. *N Page 9 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 2-2 shows the pinout for the 99-pin CSP package. Since there are four VDDIO pins, the set of I/O pins associated with any VDDIO may sink up to 100 mA total, same as for the 100-pin and 68-pin devices. Figure 2-5 on page 10 and Figure 2-6 on page 11 show an example schematic and an example PCB layout, for the 1 00-pin TQFP part, for optimal analog performance on a two-layer board.  The two pins labeled VDDD must be connected together.  The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-5 and Power System on page 26. The trace between the two VCCD pins should be as short as possible.  The two pins labeled VSSD must be connected together. For information on circuit board layout issues for mixed signals, refer to the application note, AN57821 - Mixed Signal Circuit Board Layout Considerations for PSoC® 3 and PSoC 5. Table 2-2. CSP Pinout Ball Name Ball Name Ball Name Ball Name E5 P2[5] L2 VIO1 B2 P3[6] C8 VIO0 G6 P2[6] K2 P1[6] B3 P3[7] D7 P0[4] G5 P2[7] C9 P4[2] C3 P12[0] E7 P0[5] H6 P12[4] E8 P4[3] C4 P12[1] B9 P0[6] K7 P12[5] K1 P1[7] E3 P15[2] D8 P0[7] L8 P6[4] H2 P12[6] E4 P15[3] D9 P4[4] J6 P6[5] F4 P12[7] A1 NC F8 P4[5] H5 P6[6] J1 P5[4] A9 NC F7 P4[6] J5 P6[7] H1 P5[5] L1 NC E6 P4[7] L7 VSSB F3 P5[6] L9 NC E9 VCCD K6 Ind G1 P5[7] A3 VCCA F9 VSSD L6 VBOOST G2 P15[6][6] A4 VSSA G9 VDDD K5 VBAT F2 P15[7][6] B7 VSSA H9 P6[0] L5 VSSD E2 VDDD B8 VSSA G8 P6[1] L4 XRES F1 VSSD C7 VSSA H8 P6[2] J4 P5[0] E1 VCCD A5 VDDA J9 P6[3] K4 P5[1] D1 P15[0] A6 VSSD G7 P15[4] K3 P5[2] D2 P15[1] B5 P12[2] F6 P15[5] L3 P5[3] C1 P3[0] A7 P12[3] F5 P2[0] H4 P1[0] C2 P3[1] C5 P4[0] J7 P2[1] J3 P1[1] D3 P3[2] D5 P4[1] J8 P2[2] H3 P1[2] D4 P3[3] B6 P0[0] K9 P2[3] J2 P1[3] B4 P3[4] C6 P0[1] H7 P2[4] G4 P1[4] A2 P3[5] A8 P0[2] K8 VIO2 G3 P1[5] B1 VIO3 D6 P0[3] Note 6. Pins are Do Not Use (DNU) on devices without USB. The pin mus t be left floating.

Document Number: 001-84932 Rev. *N Page 10 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 2-5. Example Schematic for 100-pin TQFP Part with Power Connections Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6. For more information on pad layout, refer to http://www.cypress.com/cad-resources/psoc-5lp-cad-libraries. VSSB10 IND11 VBOOST12 VBAT13 VSSD14 XRES15 VDDD37 VSSD38 VCCD39 VCCA 63VSSA 64VDDA 65VSSD 66 VCCD 86 VSSD 87 VDDD 88 SIO, P12[2] 67SIO, P12[3] 68P4[0] 69P4[1] 70OA2OUT, P0[0] 71OA0OUT, P0[1] 72OA0+, SAR1REF, P0[2] 73OA0-, REF0, P0[3] 74VDDIO0 75 OA2+, SAR0REF, P0[4] OA2-, P0[5] 77 IDAC0, P0[6] 78 IDAC2, P0[7] 79 P4[2] 80 P4[3] 81 P4[4] 82 P4[5] 83 P4[6] 84 P4[7] 85 P5[0]16 P5[1]17 P5[2]18 P5[3]19 P1[0], SWDIO, TMS20 P1[1], SWDCK, TCK21 P1[2]22 P1[3], SWV, TDO23 P1[4], TDI24 P1[5], NTRST25 VDDIO126 P1[6]27 P1[7]28 P12[6], SIO29 P12[7], SIO30 P5[4]31 P5[5]32 P5[6]33 P5[7]34 USB D+, P15[6]35 USB D-, P15[7]36 P6[7]9 P6[0] 89 P6[1] 90 P6[2] 91 P6[3] 92 P15[4] 93 P15[5] 94 P2[0] 95 P2[1] 96 P2[2] 97 P2[3] 98 P2[4] 99 VDDIO2 100 P2[5]1 P2[6]2 P2[7]3 P12[4], SIO4 P12[5], SIO5 P6[4]6 P6[5]7 P6[6]8 NC40 NC41 P15[0], MHZXOUT42 P15[1], MHZXIN43 P3[0], IDAC144 P3[1], IDAC345 P3[2], OA3-, REF146 P3[3], OA3+47 P3[4], OA1-48 P3[5], OA1+49 VDDIO350 OA1OUT, P3[6] 51OA3OUT, P3[7] 52SIO, P12[0] 53SIO, P12[1] 54KHZXOUT, P15[2] 55KHZXIN, P15[3] 56NC 57NC 58NC 59NC 60NC 61NC 62 VSSD VDDA VCCA VCCD VSSD VDDD VSSD VDDD VDDD VSSD VSSA VSSA VSSD VSSD VSSD VSSD 0.1 UF VSSD VDDD VDDD VDDD VDDD VDDD VSSD 1 UF 0.1 UF C10 0.1 UF C11 0.1 UF C16 0.1 UF C12 0.1 UF 0.1 UF 1 UF C15 1 UF VSSD VDDD VSSD VDDA VSSD VCCD 1 UF C17 VSSA VDDA

Document Number: 001-84932 Rev. *N Page 11 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance VDDD VSSD VDDA VSSA VSSD Plane VSSA Plane

Document Number: 001-84932 Rev. *N Page 12 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 3. Pin Descriptions IDAC0, IDAC1, IDAC2, IDAC3. Low-resistance output pin for high-current DACs (IDAC). Opamp0out, Opamp1out, Opamp2out, Opamp3out. High current output of uncommitted opamp.[7] Extref0, Extref1. External reference input to the analog system. SAR0 EXTREF, SAR1 EXTREF. External references for SAR ADCs Opamp0-, Opamp1-, Opamp2-, Opamp3-. Inverting input to uncommitted opamp. Opamp0+, Opamp1+, Opamp2+, Opamp3+. Noninverting input to uncommitted opamp. GPIO. Provides interfaces to the CPU, digital peripherals, analog peripherals, interrupts, LCD segment drive, and CapSense.[7] I2C0: SCL, I2C1: SCL. I2C SCL line providing wake from sleep on an address match. Any I/O pin can be used for I 2C SCL if wake from sleep is not required. I2C0: SDA, I2C1: SDA. I2C SDA line providing wake from sleep on an address match. Any I/O pin can be used for I 2C SDA if wake from sleep is not required. Ind. Inductor connection to boost pump. kHz XTAL: Xo, kHz XTAL: Xi. 32.768-kHz crystal oscillator pin. MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25-MHz crystal oscillator pin. nTRST. Optional JTAG Test Reset programming and debug port connection to reset the JTAG connection. SIO. Provides interfaces to the CPU, digital peripherals and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state when the device is unpowered. SWDCK. SWD Clock programming and debug port connection. SWDIO. SWD Input and Output programming and debug port connection. TCK. JTAG Test Clock programming and debug port connection. TDI. JTAG Test Data In programming and debug port connection. TDO. JTAG Test Data Out programming and debug port connection. TMS. JTAG Test Mode Select programming and debug port connection. TRACECLK. Cortex-M3 TRACEPORT connection, clocks TRACEDATA pins. TRACEDATA[3:0]. Cortex-M3 TRACEPORT connections, output data. SWV. SWV output. USBIO, D+. Provides D+ connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are Do Not Use (DNU) on devices without USB. USBIO, D-. Provides D- connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are Do Not Use (DNU) on devices without USB. VBOOST. Power sense connection to boost pump. VBAT. Battery supply to boost pump. VCCA. Output of the analog cor e regulator or the input to the analog core. Requires a 1uF capacitor to VSSA. The regulator output is not designed to drive external circuits. Note that if you use the device with an external core regulator (externally regulated mode), the voltage applied to this pin must not exceed the allowable range of 1.71 V to 1.89 V. When using the internal core regulator, (internally regulated mode, the default), do not tie any power to this pin. For detai ls see Power System on page 26. VCCD. Output of the digital core regulator or the input to the digital core. The two VCCD pins must be shorted together, with the trace between them as short as possible, and a 1uF capacitor to VSSD. The regulator output is not designed to drive external circuits. Note that if you use the device with an external core regulator (externally regulated mode), the voltage applied to this pin must not exceed the allowable range of 1.71 V to 1.89 V. When using the internal core regulator (internally regulated mode, the default), do not tie any power to this pin. For details see Power System on page 26. VDDA. Supply for all analog peripherals and analog core regulator. VDDA must be the highest voltage present on the device. All other supply pins must be less than or equal to VDDA. VDDD. Supply for all digital peripherals and digital core regulator. VDDD must be less than or equal to VDDA. VSSA. Ground for all analog peripherals. VSSB. Ground connection for boost pump. VSSD. Ground for all digital logic and I/O pins. VDDIO0, VDDIO1, VDDIO2, VDDIO3. Supply for I/O pins. Each VDDIO must be tied to a valid operating voltage (1.71 V to 5.5 V), and must be less than or equal to VDDA. XRES. External reset pin. Active low with internal pull-up. Note 7. GPIOs with opamp outputs are not recommended for use with Cap Sense.

Document Number: 001-84932 Rev. *N Page 13 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 4. CPU

4.1 Arm Cortex-M3 CPU

The CY8C58LP family of devices has an Arm Cortex-M3 CPU core. T he Cortex-M3 is a low-power 32-bit three-stage pipelined Harvard-architecture CPU that delivers 1.25 DMIPS/MHz. It is intended for deeply embedded applications that require fast interrupt handling features. Figure 4-1. Arm Cortex-M3 Block Diagram The Cortex-M3 CPU subsystem includes these features:  Arm Cortex-M3 CPU  Programmable nested vectored interrupt controller (NVIC), tightly integrated with the CPU core  Full featured debug and trace modules, tightly integrated with the CPU core  Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB of SRAM  Cache controller  Peripheral HUB (PHUB)  DMA controller  External memory interface (EMIF)

4.1.1 Cortex-M3 Features

The Cortex-M3 CPU features include:  4 GB address space. Predefined address regions for code, data, and peripherals. Multiple buses for efficient and simultaneous accesses of instructions, data, and peripherals.  The Thumb®-2 instruction set, which offers Arm-level performance at Thumb-level code density. This includes 16-bit and 32-bit instructions. Advanced instructions include:  Bit-field control  Hardware multiply and divide  Saturation  If-Then  Wait for events and interrupts  Exclusive access and barrier  Special register access Nested Vectored Interrupt Controller (NVIC) Debug Block (Serial and JTAG) Embedded Trace Module (ETM) Trace Port Interface Unit (TPIU) Interrupt Inputs JTAG/SWD Trace Pins: 5 for TRACEPORT or 1 for SWV mode Cortex M3 CPU Core I- Bus S- BusD-Bus 256 KB ECC Flash 1 KB Cache 32 KB SRAM DMA AHB Bridge & Bus Matrix PHUB GPIO & EMIF Prog. Digital Prog. Analog Special Functions Peripherals AHB Spokes AHB AHB AHB Bus Matrix Cortex M3 WrapperC-Bus Data Watchpoint and Trace (DWT) Instrumentation Trace Module (ITM) Flash Patch and Breakpoint (FPB) Bus Matrix 32 KB SRAM Bus Matrix

Document Number: 001-84932 Rev. *N Page 14 of 139 PSoC® 5LP: CY8C58LP Family Datasheet The Cortex-M3 does not suppor t Arm instructions for SRAM addresses.  Bit-band support for the SRAM region. Atomic bit-level write and read operations for SRAM addresses.  Unaligned data storage and access. Contiguous storage of data of different byte lengths.  Operation at two privilege levels (privileged and user) and in two modes (thread and handler). Some instructions can only be executed at the privileged level. There are also two stack pointers: Main (MSP) and Process (PSP). These features support a multitasking operating system running one or more user-level processes.  Extensive interrupt and system exception support.

4.1.2 Cortex-M3 Operating Modes

The Cortex-M3 operates at either the privileged level or the user level, and in either the thread mode or the handler mode. Because the handler mode is only enabled at the privileged level, there are actually only three states, as shown in Table 4-1. At the user level, access to certain instructions, special registers, configuration registers, and debugging components is blocked. Attempts to access them cause a f a u l t e x c e p t i o n . A t t h e privileged level, access to all instructions and registers is allowed. The processor runs in the handler mode (always at the privileged level) when handling an exception, and in the thread mode when not.

4.1.3 CPU Registers

The Cortex-M3 CPU registers are listed in Table 4-2. Registers R0-R15 are all 32 bits wide.

4.2 Cache Controller

The CY8C58LP family has a 1 KB, 4-way set-associative instruction cache between the CPU and the flash memory. This improves instruction execution rate and reduces system power consumption by requiring less frequent flash access.

4.3 DMA and PHUB

The PHUB and the DMA controller are responsible for data transfer between the CPU and peripherals, and also data transfers between peripherals. The PHUB and DMA also control device configuration during boot. The PHUB consists of:  A central hub that includes the DMA controller, arbiter, and router  Multiple spokes that radiate outward from the hub to most peripherals There are two PHUB masters: the CPU and the DMA controller. Both masters may initiate transactions on the bus. The DMA channels can handle peripheral communication without CPU intervention. The arbiter in the central hub determines which DMA channel is the highest priority if there are multiple requests. Table 4-1. Operational Level Condition Privileged User Running an exception Handler mode Not used Running main program Thread mode Thread mode Table 4-2. Cortex M3 CPU Registers Register Description R0-R12 General purpose registers R0-R12 have no special architecturally defined uses. Most instructions that specify a general purpose register specify R0-R12.  Low registers: Registers R0-R7 are accessible by all instructions that specify a general purpose register.  High registers: Registers R8-R12 are accessible by all 32-bit instructions that specify a general purpose register; they are not accessible by all 16-bit instructions. R13 R13 is the stack pointer register. It is a banked register that switches between two 32-bit stack pointers: the main stack pointer (MSP) and the process stack pointer (PSP). The PSP is used only when the CPU operates at the user level in thread mode. The MSP is used in all other privilege levels and modes. Bits[0:1] of the SP are ignored and considered to be 0, so the SP is always aligned to a word (4 byte) boundary. R14 R14 is the link register (LR). The LR stores the return address when a subroutine is called. R15 R15 is the program counter (PC). Bit 0 of the PC is ignored and considered to be 0, so instructions are always aligned to a half word (2 byte) boundary. xPSR The program status regi sters are divided into three status registers, which are accessed either together or separately:  Application program status register (APSR) holds program execution status bits such as zero, carry, negative, in bits[27:31].  Interrupt program status register (IPSR) holds the current exception number in bits[0:8].  Execution program status register (EPSR) holds control bits for interrupt continuable and IF-THEN instructions in bits[10:15] and [25:26]. Bit 24 is always set to 1 to indicate Thumb mode. Trying to clear it causes a fault exception. PRIMASK A 1-bit interrupt mask register. When set, it allows only the nonmaskable interrupt (NMI) and hard fault exception. All other exceptions and interrupts are masked. FAULTMASK A 1-bit interrupt mask register. When set, it allows only the NMI. All other exceptions and interrupts are masked. BASEPRI A register of up to nine bits that define the masking priority level. When set, it disables all interrupts of the same or higher priority value. If set to 0 then the masking function is disabled. CONTROL A 2-bit register for controlling the operating mode. Bit 0: 0 = privileged level in thread mode, 1 = user level in thread mode. Bit 1: 0 = default stack (MSP) is used, 1 = alternate stack is used. If in thread mode or user level then the alternate stack is the PSP. There is no alternate stack for handler mode; the bit must be 0 while in handler mode. Table 4-2. Cortex M3 CPU Registers (continued) Register Description

Document Number: 001-84932 Rev. *N Page 15 of 139 PSoC® 5LP: CY8C58LP Family Datasheet

4.3.1 PHUB Features

 CPU and DMA controller are both bus masters to the PHUB  Eight multi-layer AHB bus parallel access paths (spokes) for peripheral access  Simultaneous CPU and DMA access to peripherals located on different spokes  Simultaneous DMA source and destination burst transactions on different spokes  Supports 8-, 16-, 24-, and 32-bit addressing and data

4.3.2 DMA Features

 24 DMA channels  Each channel has one or more transaction descriptors (TDs) to configure channel behavior. Up to 128 total TDs can be defined  TDs can be dynamically updated  Eight levels of priority per channel  Any digitally routable signal, the CPU, or another DMA channel, can trigger a transaction  Each channel can generate up to two interrupts per transfer  Transactions can be stalled or canceled  Supports transaction size of infinite or 1 to 64k bytes  Large transactions may be broken into smaller bursts of 1 to 127 bytes  TDs may be nested and/or chained for complex transactions

4.3.3 Priority Levels

The CPU always has higher priority than the DMA controller when their accesses require the same bus resources. Due to the system architecture, the CPU can never starve the DMA. DMA channels of higher priority (lower priority number) may interrupt current DMA transfers. In the case of an interrupt, the current transfer is allowed to complete its current transaction. To ensure latency limits when multiple DMA accesses are requested simultaneously, a fairness algorithm guarantees an interleaved minimum percentage of bus bandwidth for priority levels 2 through 7. Priority levels 0 and 1 do not take part in the fairness algorithm and may use 100% of the bus bandwidth. If a tie occurs on two DMA requests of the same priority level, a simple round robin method is used to evenly share the allocated bandwidth. The round robin allocation can be disabled for each DMA channel, allowing it to always be at the head of the line. Prio rity levels 2 to 7 are guaranteed the minimum bus bandwidth shown in Table 4-4 after the CPU and DMA priority levels 0 and 1 have satisfied their requirements. When the fairness algorithm is disabled, DMA access is granted based solely on the priority level; no bus bandwidth guarantees are made.

4.3.4 Transaction Modes Supported

The flexible configuration of each DMA channel and the ability to chain multiple channels allow the creation of both simple and complex use cases. General use cases include, but are not limited to:

4.3.4.1 Simple DMA

In a simple DMA case, a single TD transfers data between a source and sink (peripherals or memory location). The basic timing diagrams of DMA read and write cycles are shown in Figure 4-2. For more description on other transfer modes, refer to the Technical Reference Manual. Table 4-3. PHUB Spokes and Peripherals PHUB Spokes Peripherals

0 SRAM

1 IOs, PICU, EMIF

2 PHUB local configuration, Power manager,

Clocks, IC, SWV, EEPROM, Flash programming interface

3 Analog interface and trim, Decimator

4 USB, CAN, I2C, Timers, Counters, and PWMs

5 DFB

6 UDBs group 1

7 UDBs group 2

Table 4-4. Priority Levels Priority Level % Bus Bandwidth 01 0 0 . 0 1 100.0 2 50.0 3 25.0 4 12.5 56 . 2 63 . 1 71 . 5

Document Number: 001-84932 Rev. *N Page 16 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 4-2. DMA Timing Diagram

4.3.4.2 Auto Repeat DMA

Auto repeat DMA is typically used when a static pattern is repetitively read from system memory and written to a peripheral. This is done with a single TD that chains to itself.

4.3.4.3 Ping Pong DMA

A ping pong DMA case uses double buffering to allow one buffer to be filled by one client while another client is consuming th e data previously received in the other buffer. In its simplest form, this is done by chaining two TDs together so that each TD calls the opposite TD when complete.

4.3.4.4 Circular DMA

Circular DMA is similar to ping pong DMA except it contains more than two buffers. In this case there are multiple TDs; after the last TD is complete it chains back to the first TD.

4.3.4.5 Indexed DMA

In an indexed DMA case, an external master requires access to locations on the system bus as if those locations were shared memory. As an example, a peripheral may be configured as an SPI or I 2C slave where an address is received by the external master. That address becomes an index or offset into the internal system bus memory space. This is accomplished with an initial “address fetch” TD that reads the target address location from the peripheral and writes that value into a subsequent TD in the chain. This modifies the TD chain on the fly. When the “address fetch” TD completes it moves on to the next TD, which has the new address information embedded in it. This TD then carries out the data transfer with the address location required by the external master.

4.3.4.6 Scatter Gather DMA

In the case of scatter gather DMA, there are multiple noncontiguous sources or destinations that are required to effectively carry out an overall DMA transaction. For example, a packet may need to be transmitted off of the device and the packet elements, including the header, payload, and trailer, exist in various noncontiguous locations in memory. Scatter gather DMA allows the segments to be concatenated together by using multiple TDs in a chain. The chain gathers the data from the multiple locations. A similar concept applies for the reception of data onto the device. Certain parts of the received data may need to be scattered to various locations in memory for software processing convenience. Each TD in the chain specifies the location for each discrete element in the chain.

4.3.4.7 Packet Queuing DMA

Packet queuing DMA is similar to scatter gather DMA but specifically refers to packet protocols. With these protocols, there may be separate configuration, data, and status phases associated with sending or receiving a packet. For instance, to transmit a packet, a memory mapped configuration register can be written inside a peripheral, specifying the overall length of the ensuing data phase. The CPU can set up this configuration information anywhere in system memory and copy it with a simple TD to the peripheral. After the configuration phase, a data phase TD (or a series of data phase TDs) can begin (potentially using scatter gather). When the data phase TD(s) finish, a status phase TD can be invoked that reads some memory mapped status information from the peripheral and copies it to a location in system memory specified by the CPU for later inspection. Multiple sets of configuration, data, and status phase “subchains” can be strung together to create larger chains that transmit multiple packets in this way. A similar concept exists in the opposite direction to receive the packets.

4.3.4.8 Nested DMA

One TD may modify another TD, as the TD configuration space is memory mapped similar to any other peripheral. For example, a first TD loads a second TD’s configuration and then calls the second TD. The second TD moves data as required by the application. When complete, the second TD calls the first TD, which again updates the sec ond TD’s configuration. This process repeats as often as necessary. CLK ADDR 16/32 WRITE DATA READY Basic DMA Read Transfer without wait states AB DATA (A) ADDRESS Phase DATA Phase AB ADDRESS Phase DATA Phase CLK WRITE DATA READY DATA (A) Basic DMA Write Transfer without wait states ADDR 16/32

Document Number: 001-84932 Rev. *N Page 17 of 139 PSoC® 5LP: CY8C58LP Family Datasheet

4.4 Interrupt Controller

The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in Table 4-5. Bit 0 of each exception vector indicates whether the exception is executed using Arm or Thumb instructions. Because the Cortex-M3 only supports Thumb instructions, this bit must always be 1. The Cortex-M3 non maskable interrupt (NMI) input can be routed to any pin, via the DSI, or disconnected from all pins. See DSI Routing Interface Description on page 45. The Nested Vectored Interrupt Controller (NVIC) handles interrupts from the peripherals, and passes the interrupt vectors to the CPU. It is closely integrated with the CPU for low laten cy interrupt handling. Features include:  32 interrupts. Multiple sources for each interrupt.  Eight priority levels, with dynamic priority control.  Priority grouping. This allows selection of preempting and non preempting interrupt levels.  Support for tail-chaining, and late arrival, of interrupts. This enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts.  Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead. If the same priority level is assigned to two or more interrupt s, the interrupt with the lower vector number is executed first. Each interrupt vector may choose from three interrupt sources: Fixed Function, DMA, and UDB. The fixed function interrupts are direct connections to the most common interrupt sources and provide the lowest resource cost connection. The DMA interrupt sources provide direct connections to the two DMA interrupt sources provided per DMA channel. The third interrupt source for vectors is from the UDB digital routing array. This allows any digital signal available to the UDB array to be used as an interrupt source. All interrupt sources may be routed to any interrupt vector using the UDB interrupt source connections. Table 4-5. Cortex-M3 Exceptions and Interrupts Exception Number Exception Type Priority Exception Table Address Offset Function 0x00 Starting value of R13 / MSP

1 Reset -3 (highest) 0x04 Reset

2 NMI -2 0x08 Non maskable interrupt

3 Hard fault -1 0x0C All classes of fault, when the corresponding f ault handler

cannot be activated because it is currently disabled or masked

4 MemManage Programmable 0x10 Memory management fault, for example, instruction

fetch from a nonexecutable region

5 Bus fault Programmable 0x14 Error response received from the bus system; caused

by an instruction prefetch abort or data access error

6 Usage fault Programmable 0x18 Typic ally caused by invalid instructions or trying to

7–10 - - 0x1C–0x28 Reserved

11 SVC Programmable 0x2C System ser vice call via SVC instruction

12 Debug monitor Programmable 0x30 Debug monitor

14 PendSV Programmable 0x38 Deferred request for system service

15 SYSTICK Programmable 0x3C System tick timer

16–47 IRQ Programmable 0x40–0x3FC Peri pheral interrupt request #0 - #31

Document Number: 001-84932 Rev. *N Page 18 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 4-6. Interrupt Vector Table Interrupt # Cortex-M3 Exception # Fixed Function DMA UDB 0 16 Low voltage detect (LVD) phub_termout0[0] udb_intr[0] 1 17 Cache/ECC phub_te rmout0[1] udb_intr[1] 21 8 Reserved phub_termout0[2] udb_intr[2] 3 19 Sleep (Pwr Mgr) phub_t ermout0[3] udb_intr[3] 4 20 PICU[0] phub_term out0[4] udb_intr[4] 5 21 PICU[1] phub_term out0[5] udb_intr[5] 6 22 PICU[2] phub_term out0[6] udb_intr[6] 7 23 PICU[3] phub_term out0[7] udb_intr[7] 8 24 PICU[4] phub_term out0[8] udb_intr[8] 9 25 PICU[5] phub_term out0[9] udb_intr[9] 10 26 PICU[6] phub_term out0[10] udb_intr[10] 11 27 PICU[12] phub_termout 0[11] udb_intr[11] 12 28 PICU[15] phub_term out0[12] udb_intr[12] 13 29 Comparators Combined phub _termout0[13] udb_intr[13] 14 30 Switched Caps Combined phub_termout0[14] udb_intr[14] 15 31 I 2C phub_termout0[15] udb_intr[15] 16 32 CAN phub_termout1[0] udb_intr[16] 17 33 Timer/Counter0 phub_termout1[1] udb_intr[17] 18 34 Timer/Counter1 phub_termout1[2] udb_intr[18] 19 35 Timer/Counter2 phub_termout1[3] udb_intr[19] 20 36 Timer/Counter3 phub_termout1[4] udb_intr[20] 21 37 USB SOF Int phub_te rmout1[5] udb_intr[21] 22 38 USB Arb Int phub_te rmout1[6] udb_intr[22] 23 39 USB Bus Int phub_te rmout1[7] udb_intr[23] 24 40 USB Endpoint[0] phub_termout1[8] udb_intr[24] 25 41 USB Endpoint Data phub _termout1[9] udb_intr[25] 26 42 Reserved phub_termout1[10] udb_intr[26] 27 43 LCD phub_termout1[11] udb_intr[27] 28 44 DFB Int phub_termout1[12] udb_intr[28] 29 45 Decimator Int phub_termout1[13] udb_intr[29] 30 46 phub_err_int phub_termout1[14] udb_intr[30] 31 47 eeprom_fault_int phub_t ermout1[15] udb_intr[31]

Document Number: 001-84932 Rev. *N Page 19 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 5. Memory

5.1 Static RAM

CY8C58LP static RAM (SRAM) is used for temporary data storage. Code can be executed at full speed from the portion of SRAM that is located in the code space. This process is slower from SRAM above 0x20000000. The device provides up to 64 KB of SRAM. The CPU or the DMA controller can access all of SRAM. The SRAM can be accessed simultaneously by the Cortex-M3 CPU and the DMA controller if accessing different 32-KB blocks.

5.2 Flash Program Memory

Flash memory in PSoC devices provides nonvolatile storage for user firmware, user configurat ion data, bulk data storage, and optional ECC data. The main flash memory area contains up to 256 KB of user program space. Up to an additional 32 KB of flash space is available for Error Correcting Codes (ECC). If ECC is not used this space can store device configuration data and bulk user data. User code may not be run out of the ECC flash memory section. ECC can correct one bit error and detect two bit errors per 8 bytes of firmware memory; an interrupt can be generated when an error is detected. The flash output is 9 bytes wide with 8 bytes of data and 1 byte of ECC data. The CPU or DMA controller read both user code and bulk data located in flash through the cache controller. This provides higher CPU performance. If ECC is enabled, the cache controller also performs error checking and correction. Flash programming is performed through a special interface and preempts code execution out of flash. Code execution may be done out of SRAM during flash programming. The flash 24programming interface performs flash erasing, programming and setting code protection levels. Flash in-system serial programming (ISSP), ty pically used for production programming, is possible through both the SWD and JTAG interfaces. In-system progr amming, typically used for bootloaders, is also possible using serial interfaces such as I 2C, USB, UART, and SPI, or any communications protocol.

5.3 Flash Security

All PSoC devices include a flexible flash protection model that prevents access and visibility to on-chip flash memory. This prevents duplication or reverse engineering of proprietary code. Flash memory is organized in blocks, where each block contains 256 bytes of program or data and 32 bytes of ECC or configuration data. The device offers the ability to assign one of four protection levels to each row of flash. Table 5-1 lists the protection modes available. Flash protection levels can only be changed by performing a complete flash erase. The Full Protection and Field Upgrade settings disable external access (through a debugging tool such as PSoC Creator, for example). If your application requires code update through a boot loader, then use the Field Upgrade setting. Use the Unprotected setting only when no security is needed in your application. The PSoC device also offers an advanced security feature called Device Security which permanently disables all test, programming, and debug ports, protecting your application from external access (see the “Device Security” section on page 64). For more information on how to take full advantage of the security features in PSoC, see the PSoC 5 TRM. Disclaimer Note the following details of the flash code protection features on Cypress devices. Cypress products meet the specifications contained in their particular Cypress datasheets. C ypress believes that its family of products is one of the most secure families of its kind on t he market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of t hese methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantl y evolving. We at Cypress are committed to continuously improving the code protection features of our products.

5.4 EEPROM

PSoC EEPROM memory is a byte addressable nonvolatile memory. The CY8C58LP has 2 KB of EEPROM memory to store user data. Reads from EEPROM are random access at the byte level. Reads are done directly; writes are done by sending write commands to an EEPROM programming interface. CPU code execution can continue from flash during EEPROM writes. EEPROM is erasable and writea ble at the row level. The EEPROM is divided into 128 rows of 16 bytes each. The factory default values of all EEPROM bytes are 0. Because the EEPROM is mapped to the Cortex-M3 Peripheral region, the CPU cannot execute out of EEPROM. There is no ECC hardware associated with EEPROM. If ECC is required it must be handled in firmware. It can take as much as 20 milliseconds to write to EEPROM or flash. During this time the device should not be reset, or unexpected changes may be made to portions of EEPROM or flash. Reset sources (see Reset Sources on page 32) include XRES pin, software reset, and watchdog; care should be taken to make sure that these are not inadvertently activated. In addition, the low voltage detect circuits should be configured to generate an interrupt instead of a reset. Table 5-1. Flash Protection Protection Setting Allowed Not Allowed Unprotected External read and write + internal read and write Factory Upgrade External write + internal read and write External read Field Upgrade Internal read and write External read and write Full Protection Internal read External read and write + internal write

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5.5 Nonvolatile Latches (NVLs)

PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown in Table 5-3. The details for individual fields and their factory default settings are shown in Table 5-3:. Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase/write cycles is limited – see “Nonvolatile Latches (NVL)” on page 117. Table 5-2. Device Configuration NVL Register Map Register Address 7 6 5 4 3 2 1 0 0x00 PRT3RDM[1:0] PRT2RDM[1:0] PRT1RDM[1:0] PRT0RDM[1:0] 0x01 PRT12RDM[1:0] PRT6RDM[1:0] PRT5RDM[1:0] PRT4RDM[1:0] 0x02 XRESMEN DBGEN PRT15RDM[1:0] 0x03 DIG_PHS_DLY[3:0] ECCEN DPS[1:0] CFGSPEED Table 5-3. Fields and Factory Default Settings Field Description Settings PRTxRDM[1:0] Controls reset dri ve mode of the corresponding IO port. See “Reset Configuration” on page 39. All pins of the port are set to the same mode. 00b (default) - high impedance analog 01b - high impedance digital 10b - resistive pull up 11b - resistive pull down XRESMEN Controls whether pin P1[ 2] is used as a GPIO or as an external reset. P1[2] is generally used as a GPIO, and not as an external reset. 0 (default) - GPIO 1 - external reset DBGEN Debug Enable allows a ccess to the debug system, for third-party programmers. 0 - access disabled 1 (default) - access enabled CFGSPEED Controls the speed of t he IMO-based clock during the device boot process, for faster boot or low-power operation 0 (default) - 12 MHz IMO 1 - 48 MHz IMO DPS[1:0] Controls the usage of v arious P1 pins as a debug port. See “Programming, Debug Interfaces, Resources” on page 61. 00b - 5-wire JTAG 01b (default) - 4-wire JTAG 10b - SWD 11b - debug ports disabled ECCEN Controls whether ECC flash is used for ECC or for general configuration and data storage. See “Flash Program Memory” on page 19. 0 - ECC disabled 1 (default) - ECC enabled DIG_PHS_DLY[3:0] Selects the digital clock phase delay. See the T RM for details.

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5.6 External Memory Interface

CY8C58LP provides an external memory interface (EMIF) for connecting to external memory devices. The connection allows read and write accesses to e xternal memories. The EMIF operates in conjunction with UDBs, I/O ports, and other hardware to generate external memory address and control signals. At 33 MHz, each memory access cycle takes four bus clock cycles. Figure 5-1 is the EMIF block diagram. The EMIF supports synchronous and asynchronous memories. The CY8C58LP only supports one type of external memory device at a time. External memory is located in the Cortex-M3 external RAM space; it can use up to 24 address bits. See Memory Map on page 22. The memory can be 8 or 16 bits wide. Cortex-M3 instructions can be fetched from external memory if it is 16-bit. Other limitations apply; for details, see application note AN89610, PSoC ® 4 and PSoC 5LP Arm Cortex Code Optimization. There is no provision for code security in external memory. If code must be kept secure, then it should be placed in internal flash. See Flash Security on page 19 and Device Security on page 64. Figure 5-1. EMIF Block Diagram PHUB IO IF UDB EMIF I/O PORTs I/O PORTs I/O PORTs Data, Address, and Control Signals Data, Address, and Control Signals Address Signals Data Signals Control Signals Data, Address, and Control Signals EM Control Signals Other Control Signals DSI Dynamic Output Control DSI to Port Control External _ MEM_ DATA[15:0] External _ MEM _ ADDR[23 :0]

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5.7 Memory Map

The Cortex-M3 has a fixed address map, which allows peripherals to be accessed by simple memory access instructions.

5.7.1 Address Map

The 4-GB address space is divided into the ranges shown in Table 5-4: The bit-band feature allows individual bits in SRAM to be read or written as atomic operations. This is done by reading or writin g bit 0 of corresponding words in the bit-band alias region. For example, to set bit 3 in the word at address 0x20000000, write a 1 to address 0x2200000C. To test the value of that bit, read address 0x2200000C and the result is either 0 or 1 depending on the value of the bit. Most memory accesses done by the Cortex-M3 are aligned, that is, done on word (4-byte) boundary addresses. Unaligned accesses of words and 16-bit half-words on nonword boundary addresses can also be done, although they are less efficient.

5.7.2 Address Map and Cortex-M3 Buses

The ICode and DCode buses are used only for accesses within the Code address range, 0–0x1FFFFFFF. The System bus is used for data accesses and debug accesses within the ranges 0x20000000–0xDFFFFFFF and 0xE0100000–0xFFFFFFFF. Instruction fetches can also be done within the range 0x20000000–0x3FFFFFFF, although these can be slower than instruction fetches via the ICode bus. The private peripheral bus (PPB) is used within the Cortex-M3 to access system control registers and debug and trace module registers. Table 5-4. Address Map Address Range Size Use 0x00000000– 0x1FFFFFFF 0.5 GB Program code. This includes the exception vector table at power up, which starts at address 0. 0x20000000– 0x3FFFFFFF 0.5 GB Static RAM. This includes a 1 MByte bit-band region starting at 0x20000000 and a

32 Mbyte bit-band alias

0x22000000. 0x40000000– 0x5FFFFFFF 0.5 GB Peripherals. 0x60000000– 0x9FFFFFFF 1 GB External RAM. 0xA0000000– 0xDFFFFFFF 1 GB External peripherals. 0xE0000000– 0xFFFFFFFF

0.5 GB Internal peri pherals, including

trace modules. Table 5-5. Peripheral Data Address Map Address Range Purpose 0x00000000–0x0003FFFF 256 KB flash 0x1FFF8000–0x1FFFFFFF 32 KB SRAM in Code region 0x20000000–0x20007FFF 32 KB SRAM in SRAM region 0x40004000–0x400042FF Clocking, PLLs, and oscillators 0x40004300–0x400043FF Power management 0x40004500–0x400045FF Ports interrupt control 0x40004700–0x400047FF Flash programming interface 0x40004800–0x400048FF Cache controller 0x40004900–0x400049FF I 2C controller 0x40004E00–0x40004EFF Decimator 0x40004F00–0x40004FFF Fixed timer/counter/PWMs 0x40005000–0x400051FF I/O ports control 0x40005400–0x400054FF External Memory Interface (EMIF) control registers 0x40005800–0x40005FFF Analog Subsystem Interface 0x40006000–0x400060FF USB Controller 0x40006400–0x40006FFF UDB Working Registers 0x40007000–0x40007FFF PHUB Configuration 0x40008000–0x400087FF EEPROM 0x4000A000–0x4000A400 CAN 0x4000C000–0x4000C800 Digital Filter Block 0x40010000–0x4001FFFF Digital I nterconnect Configuration 0x48000000–0x48007FFF Flash ECC Bytes 0x60000000–0x60FFFFFF External Memory Interface (EMIF) 0xE0000000–0xE00FFFFF Cortex-M3 PPB Registers, including NVIC, debug, and trace Table 5-5. Peripheral Data Address Map (continued) Address Range Purpose

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6.1 Clocking System

The clocking system generates, di vides, and distributes clocks throughout the PSoC system. For the majority of systems, no external crystal is required. The IMO and PLL together can generate up to a 80 MHz clock, accurate to ±1% over voltage and temperature. Additional internal and external clock sources allow each design to optimize accuracy, power, and cost. All of the system clock sources can be us ed to generate other clock frequencies in the 16-bit clock dividers and UDBs for anything you want, for example a UART baud rate generator. Clock generation and distribution is automatically configured through the PSoC Creator IDE graphical interface. This is based on the complete system’s require ments. It greatly speeds the design process. PSoC Creator allows designers to build clocking systems with minimal input. The designer can specify desired clock frequencies and accuracies, and the software locates or builds a clock that meets the required specifications. This is possible because of the programmability inherent in PSoC. Key features of the clocking system include:  Seven general purpose clock sources  3- to 74-MHz IMO, ±1% at 3 MHz  4- to 25-MHz external crystal oscillator (MHzECO)  Clock doubler provides a doubled clock frequency output for the USB block, see USB Clock Domain on page 26.  DSI signal from an external I/O pin or other logic  24- to 80-MHz fractional phase-locked loop (PLL) sourced from IMO, MHzECO, or DSI  1-kHz, 33-kHz, 100-kHz ILO for watchdog timer (WDT) and Sleep Timer  32.768-kHz external crystal oscillator (ECO) for RTC  IMO has a USB mode that auto-locks to the USB bus clock requiring no external crystal for USB. (USB equipped parts only)  Independently sourced clock in all clock dividers  Eight 16-bit clock dividers for the digital system  Four 16-bit clock dividers for the analog system  Dedicated 16-bit divider for the CPU bus and CPU clock  Automatic clock configuration in PSoC Creator Table 6-1. Oscillator Summary Source Fmin Tolerance at Fmin Fmax Tolerance at Fmax Startup Time IMO 3 MHz ±1% over voltage and te mperature 74 MHz ±7% 13 µs max MHzECO 4 MHz Crystal dependent 25 MH z Crystal dependent 5 ms typ, ma x is crystal dependent DSI 0 MHz Input dependent 33 MHz Input dependent Input dependent PLL 24 MHz Input dependent 80 MHz Input dependent 250 µs max Doubler 48 MHz Input dependent 48 MHz Input dependent 1 µs max ILO 1 kHz –50%, +100% 100 kHz –55%, +100% 15 ms max in lowest power mode kHzECO 32 kHz Crystal dependent 32 kH z Crystal dependent 500 ms typ, max is crystal dependent

Document Number: 001-84932 Rev. *N Page 24 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 6-1. Clocking Subsystem 4-25 MHz ECO 3-74 MHz IMO 32 kHz ECO 1,33,100 kHz ILO s k e w Digital Clock Divider 16 bit Digital Clock Divider 16 bit Digital Clock Divider 16 bit Digital Clock Divider 16 bit Digital Clock Divider 16 bit Digital Clock Divider 16 bit Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit Bus Clock Divider 16 bit

48 MHz

s k e w Analog Clock Divider 16 bit s k e w Analog Clock Divider 16 bit s k e w Analog Clock Divider 16 bit Bus Clock CPU Clock

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6.1.1 Internal Oscillators

Figure 6-1 shows that there are two internal oscillators. They can be routed directly or divided. T he direct routes may not have a 50% duty cycle. Divided clocks have a 50% duty cycle.

6.1.1.1 Internal Main Oscillator

In most designs the IMO is the only clock source required, due to its ±1% accuracy. The IMO operates with no external components and outputs a stable clock. A factory trim for each frequency range is stored in the device. With the factory trim, tolerance varies from ±1% at 3 MHz, up to ±7% at 74 MHz. The IMO, in conjunction with the PLL, allows generation of CPU and system clocks up to the device's maximum frequency (see USB Clock Domain on page 26). The IMO provides clock outputs at 3, 6, 12, 24, 48, and 74 MHz.

6.1.1.2 Clock Doubler

The clock doubler outputs a clock at twice the frequency of the input clock. The doubler works at input frequency of 24 MHz, providing 48 MHz for the USB. It can be configured to use a clock from the IMO, MHzECO, or the DSI (external pin).

6.1.1.3 Phase-Locked Loop

The PLL allows low frequency, high accuracy clocks to be multiplied to higher frequencies. This is a tradeoff between higher clock frequency and accuracy and, higher power consumption and increased startup time. The PLL block provides a mechanism for generating clock frequencies based upon a variety of input sources. The PLL outputs clock frequencies in the range of 24 to 80 MHz. Its input and feedback dividers supply 4032 discrete ratios to create almost any desired system clock frequency. The accuracy of the PLL output depends on the accuracy of the PLL input source. The most common PLL use is to multiply the IMO clock at 3 MHz, where it is most accurate, t o generate the CPU and system clocks up to the device’s maximum frequency. The PLL achieves phase lock within 250 µs (verified by bit setting). It can be configured t o u s e a c l o c k f r o m t h e I M O , MHzECO, or DSI (external pin). The PLL clock source can be used until lock is complete and signaled with a lock bit. The lock signal can be routed through th e DSI to generate an interrupt. Disable the PLL before entering low power modes.

6.1.1.4 Internal Low-Speed Oscillator

The ILO provides clock frequencies for low power consumption, including the watchdog timer, and sleep timer. The ILO generates up to three different clocks: 1 kHz, 33 kHz, and 100 kHz. The 1-kHz clock (CLK1K) is typically used for a background ‘heartbeat’ timer. This clock inherently lends itself to low po wer supervisory operations such as the watchdog timer and long sleep intervals using the central timewheel (CTW). The central timewheel is a 1 kHz, free running, 13-bit counter clocked by the ILO. The central timewheel is always enabled except in hibernate mode and when the CPU is stopped during debug on chip mode. It can be used to generate periodic interrupts for timing purposes or to wake the system from a low power mode. Firmware can reset the central timewheel. The central timewheel can be programmed to wake the system periodically and optionally issue an interrupt. This enables flexible, periodic wakeups from low power modes or coarse timing applications. Systems that require accurate timing should use the RTC capability instead of the central timewheel. The 100-kHz clock (CLK100K) can be used as a low power system clock to run the CPU. It can also generate time intervals using the fast timewheel. The fast timewheel is a 5-bit counter, clocked by the 100-kHz clock. It features programmabl e settings and automatically resets when the terminal count is reached. An optional interrupt can be generated each time the terminal count is reached. This enables flexible, periodic interrupts of the CPU at a higher ra te than is allowed using the central timewheel. The 33-kHz clock (CLK33K) comes from a divide-by-3 operation on CLK100K. This output can be used as a reduced accuracy version of the 32.768-kHz ECO clock with no need for a crystal.

6.1.2 External Oscillators

Figure 6-1 shows that there are two external oscillators. They can be routed directly or divided. The direct routes may not have a 50% duty cycle. Divided clocks have a 50% duty cycle.

6.1.2.1 MHz External Crystal Oscillator

The MHzECO provides high frequency, high precision clocking using an external crystal (see Figure 6-2). It supports a wide variety of crystal types, in the range of 4 to 25 MHz. When used in conjunction with the PLL, it can generate CPU and system clocks up to the device' s maximum frequency (see Phase-Locked Loop on page 25). The GPIO pins connecting to the external crystal and capacitors are fixed. MHzECO accuracy depends on the crystal chosen. Figure 6-2. MHzECO Block Diagram Xo (Pin P15[0]) 4 - 25 MHz Crystal Osc XCLK_MHZ 4 – 25 MHz crystal Capacitors External Components Xi (Pin P15[1])

Document Number: 001-84932 Rev. *N Page 26 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 6.1.2.2 32.768 kHz ECO The 32.768-kHz external crystal oscillator (32kHzECO) provides precision timing with minimal power consumption using an external 32.768-kHz watch crystal (see Figure 6-3). The 32kHzECO also connects directly to the sleep timer and provides the source for the RTC. The RTC uses a 1 second interrupt to implement the RTC functionality in firmware. The oscillator works in two distinct power modes. This allows users to trade off power consumption with noise immunity from neighboring circuits. The GPIO pins connected to the external crystal and capacitors are fixed. Figure 6-3. 32kHzECO Block Diagram It is recommended that the exte rnal 32.768-kHz watch crystal have a load capacitance (CL) of 6 pF or 12.5 pF. Check the crystal manufacturer's datasheet. The two external capacitors, CL1 and CL2, are typically of the same value, and their total capacitance, CL1CL2 / (CL1 + CL2), including pin and trace capacitance, should equal the crystal CL value. For more infor- mation, refer to application note AN54439: PSoC 3 and PSoC 5 External Oscillators. See also pin capacitance specifications in the “GPIO” section on page 76.

6.1.2.3 Digital System Interconnect

The DSI provides rout ing for clocks taken from external clock oscillators connected to I/O. The oscillators can also be generated within the device in the digital system and UDBs. While the primary DSI clock input provides access to all clocking resources, up to eight other D SI clocks (internally or external ly generated) may be routed directly to the eight digital clock dividers. This is only possible if there are multiple precision clock sources.

6.1.3 Clock Distribution

All seven clock sources are inputs to the central clock distribution system. The distributi on system is designed to create multiple high precision clocks. These clocks are customized for the design’s requirements and eliminate the common problems found with limited resolution prescalers attached to peripherals. The clock distribution system generates several types of clock trees.  The system clock is used to select and supply the fastest clock in the system for general system clock requirements and clock synchronization of the PSoC device.  Bus clock 16-bit divider uses the system clock to generate the system’s bus clock used for data transfers and the CPU. The CPU clock is directly derived from the bus clock.  Eight fully programmable 16-bit clock dividers generate digital system clocks for general use in the digital system, as configured by the design’s requirements. Digital system clocks can generate custom clocks derived from any of the seven clock sources for any purpose. Examples include baud rate generators, accurate PWM periods, and timer clocks, and many others. If more than eight digital clock dividers are required, the UDBs and fixed function timer/counter/PWMs can also generate clocks.  Four 16-bit clock dividers generate clocks for the analog system components that require clocking, such as ADCs and mixers. The analog clock dividers include skew control to ensure that critical analog events do not occur simultaneously with digital switching events. This is done to reduce analog system noise. Each clock divider consists of an 8-input multiplexer, a 16-bit clock divider (divide by 2 and higher) that generates ~50% duty cycle clocks, system clock resynchronization logic, and deglitch logic. The outputs from each digital clock tree can be routed into the digital system interconnect and then brought back into the clock system as an input, allowing clock chaining of up to 32 bits.

6.1.4 USB Clock Domain

The USB clock domain is unique in that it operates largely asynchronously from the main clock network. The USB logic contains a synchronous bus interface to the chip, while running on an asynchronous clock to process USB data. The USB logic requires a 48-MHz frequency. This frequency can be generated from different sources, including DSI clock at 48 MHz or doubled value of 24 MHz from internal oscillator, DSI signal, or crysta l oscillator.

6.2 Power System

The power system consists of sepa rate analog, digital, and I/O supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It also includes two internal 1.8 V regulators that provide the digital (VCCD) and analog (VCCA) supplies for the internal core logic. The output pins of the regulators (VCCD and VCCA) and the VDDIO pins must have capacitors connected as shown in Figure 6-4. The two V CCD pins must be shorted together, with as short a trace as possible, and connected to a 1 µF ±10% X5R capacitor. The power system also contains a sleep regulator, an I 2C regulator, and a hibernate regulator. Xo (Pin P15[2]) 32 kHz Crystal Osc XCLK32K 32 kHz crystal Capacitors External Components Xi (Pin P15[3])

Document Number: 001-84932 Rev. *N Page 27 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 6-4. PSoC Power System Notes  The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6.  You can power the device in internally regulated mode, where the voltage applied to the VDDx pins is as high as 5.5 V, and the internal regulators provide the core voltages. In this mode, do not apply power to the VCCx pins, and do not tie the VDDx pins to the VCCx pins.  You can also power the device in externally regulated mode, that is, by directly powering the VCCD and VCCA pins. In this configuration, the VDDD pins should be shorted to the VCCD pins and the VDDA pin should be shorted to the VCCA pin. The allowed supply range in this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by default, and should be disabled to reduce power consumption.  It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias specifications. With some capacitors, the actual capacitance can decrease considerably when the DC bias (VDDX or VCCX in Figure 6-4) is a significant percentage of the rated working voltage. VSSB VSSD VDDIO1 VDDIO2 VDDIO0 VDDIO3 VCCD VDDD VSSD VCCD VDDD VSSA VCCA VDDA Digital Regulators Analog Regulator Analog Domain Digital Domain I2C Regulator Sleep Regulator Hibernate Regulator I/O Supply I/O Supply I/O SupplyI/O Supply VDDIO2 VDDIO0 VDDIO3VDDIO1 0.1 µF 0.1 µF 0.1 µF 0.1 µF VDDD VDDD 1 µF 1 µF VDDA 0.1 µF 0.1 µF 0.1 µF

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6.2.1 Power Modes

PSoC 5LP devices have four different power modes, as shown in Table 6-2 and Table 6-3. The power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing battery life in low power and portable devices. PSoC 5LP power modes, in order of decreasing power consumption are:  Active  Alternate active  Sleep  Hibernate Active is the main processing mode. Its functionality is configurable. Each power controllable subsystem is enabled or disabled by using separate power configuration template registers. In alternate acti ve mode, fewer subsystems are enabled, reducing power. In sleep mode most resources are disabled regardless of the template settings. Sleep mode is optimized to provide timed sleep intervals and RTC functionality. The lowest power mode is hibernate, which retains register and SRAM state, but no clocks, and allows wakeup only from I/O pins. Figure 6-5 illustrates the allowable transitions between power modes. Sleep and hibernate modes should not be entered until all VDDIO supplies are at valid voltage levels. Table 6-2. Power Modes Power Modes Description Entry Condition Wakeup Source Active Clocks Regulator Active Primary mode of operation, all peripherals available (program- mable) Wakeup, reset, manual register entry Any interrupt Any (program- mable) All regulators available. Digital and analog regulators can be disabled if external regulation used. Alternate Active Similar to Active mode, and is typically configured to have fewer peripherals active to reduce power. One possible configuration is to use the UDBs for processing, with the CPU turned off Manual register entry Any interrupt Any (program- mable) All regulators available. Digital and analog regulators can be disabled if external regulation used. Sleep All subsystems automatically disabled Manual register entry Comparator, PICU, I 2C, RTC, CTW, LVD ILO/kHzECO Both digital and analog regulators buzzed. Digital and analog regulators can be disabled if external regulation used. Hibernate All subsystems automatically disabled Lowest power consuming mode with all peripherals and internal regulators disabled, except hibernate regulator is enabled Configuration and memory contents retained Manual register entry PICU Only hibernate regulator active. Table 6-3. Power Modes Wakeup Time and Power Consumption Sleep Modes Wakeup Time Current (Typ) Code Execution Digital Resources Analog Resources Clock Sources Available Wakeup Sources Reset Sources Active – 3.1 mA [8] Yes All All All – All Alternate Active – – User defined All All All – All Sleep <25 µs 2 µA No I 2C Comparator ILO/kHzECO Comparator, PICU, I2C, RTC, CTW, LVD XRES, LVD, WDR Hibernate <200 µs 300 nA No None None None PICU XRES Note 8. Bus clock off. Execute from CP U instruction buffer at 6 MHz. See Table 11-2 on page 68.

Document Number: 001-84932 Rev. *N Page 29 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 6-5. Power Mode Transitions

6.2.1.1 Active Mode

Active mode is the primary operating mode of the device. When in active mode, the active confi guration template bits control which available resources are enabled or disabled. When a resource is disabled, the digita l clocks are gated, analog bias currents are disabled, and leakage currents are reduced as appropriate. User firmware can dynamically control subsystem power by setting and clearing bi ts in the active configuration template. The CPU can disable itself, in which case the CPU is automatically reenabled at the next wakeup event. When a wakeup event occurs, the global mode is always returned to active, and the CPU is automatically enabled, regardless of its template settings. Active mode is the default global power mode upon boot.

6.2.1.2 Alternate Active Mode

Alternate Active mode is very similar to Active mode. In alternate active mode, fewer subsystems are enabled, to reduce power consumption. One possible configuration is to turn off the CPU and flash, and run peripherals at full speed.

6.2.1.3 Sleep Mode

Sleep mode reduces power consumption when a resume time of 15 µs is acceptable. The wake time is used to ensure that the regulator outputs are stable enough to directly enter active mode.

6.2.1.4 Hibernate Mode

In hibernate mode nearly all of the internal functions are disabled. Internal voltages are re duced to the minimal level to keep vital systems alive. Confi guration state is preserved in hibernate mode and SRAM memory is retained. GPIOs configured as digital outputs maintain their previous values and external GPIO pin interrupt settings are preserved. The device can only return from hibernate mode in response to an external I/O interrupt. The resume time from hibernate mode is less than 100 µs. To achieve an extremely low current, the hibernate regulator has limited capacity. This limits the frequency of any signal prese nt on the input pins; no GPIO should toggle at a rate greater than 10 kHz while in hibernate mode. If pins must be toggled at a high rate while in a low power mode, use sleep mode instead.

6.2.1.5 Wakeup Events

Wakeup events are configurable and can come from an interrupt or device reset. A wakeup event restores the system to active mode. Firmware enabled interrupt sources include internally generated interrupts, power supervisor, central timewheel, and I/O interrupts. Internal interrupt sources can come from a variety of peripherals, such as analog comparators and UDBs. The central timewheel provides periodic interrupts to allow the system to wake up, poll peripherals, or perform real-time functions. Reset event sources include the external reset pin (XRES), WDT, and Precision Reset (PRES).

6.2.2 Boost Converter

Applications that use a supply voltage of less than 1.71 V, such as solar panels or single cell battery supplies, may use the on-chip boost converter to generate a minimum of 1.8 V supply voltage. The boost converter may also be used in any system that requires a higher operating voltage than the supply provides such as driving 5.0 V LCD gla ss in a 3.3 V system. With the addition of an inductor, Schottky diode, and capacitors, it produces a selectable output voltage sourcing enough current to operate the PSoC and other on-board components. The boost converter accepts an input voltage V BAT from 0.5 V to 3.6 V, and can start up with VBAT as low as 0.5 V. The converter provides a user configurable output voltage of 1.8 to 5.0 V (VOUT) in 100 mV increments. V BAT is typically less than V OUT; if VBAT is greater than or equal to V OUT, then VOUT will be slightly less than VBAT due to resistive losses in the boost converter. The block can deliver up to 50 mA (I BOOST) depending on configuration to both the PSoC device and external components. The sum of all current sinks in the design including the PSoC device, PSoC I/O pin loads, and external component loads must be less than the I BOOST specified maximum current. Four pins are associated with the boost converter: VBAT, VSSB, VBOOST, and IND. The boosted output voltage is sensed at the VBOOST pin and must be connected directly to the chip’s supply inputs; VDDA, VDDD, and VDDIO if used to power the PSoC device. The boost converter requires four components in addition to those required in a non-boost design, as shown in Figure 6-6 on page 30. A 22 µF capacitor (C BAT) is required close to the VBAT pin to provide local bulk storage of the battery voltage and provide regulator stability. A diode between the battery and VBAT pin should not be used for rever se polarity protection because the diodes forward voltage drop reduces the V BAT v o l t a g e . Between the VBAT and IND pins, an inductor of 4.7 µH, 10 µH, or 22 µH is required. The inductor value can be optimized to increase the boost converter efficiency based on input voltage, output voltage, temperature, and current. Inductor size is determined by following the design guidance in this chapter and electrical specifications. The inductor must be placed within 1cm of the V BAT and IND pins and have a minimum saturation current of 750 mA. Between the IND and VBOOST pins a Schottky diode must be placed within 1 cm of the pins. The Schottky diode shall have a forward current rating of at least 1.0 A and a reverse voltage of at least 20 V. A 22 µF bulk capacitor (C BOOST) must be connected close to V BOOST to provide regulator output stability. It is important to sum the total capacitance connected to the VBOOST pin and ensure the maximum CBOOST specification is not exceeded. All capacitors must be rated for a minimum of 10 V to minimize capacitive losses due to voltage de-rating. Active Manual Hibernate Alternate Active Sleep

Document Number: 001-84932 Rev. *N Page 31 of 139 PSoC® 5LP: CY8C58LP Family Datasheet The switching frequency is set t o 400 kHz using an oscillator integrated into the boost converter. The boost converter can be operated in two different modes: active and standby. Active mode is the normal mode of operation where the boost regulator actively generates a regulated output voltage. In standby mode, most boost functions are di sabled, thus reducing power consumption of the boost circuit. Only minimal power is provided, typically < 5 µA to power the PSoC device in Sleep mode. The boost typically draws 250 µA in active mode and 25 µA in standby mode. The boost operating modes must be used in conjunction with chip power modes to minimize total power consumption. Table 6-4 lists the boost power modes available in different chip power modes.

6.2.2.1 Boost Firmware Requirements

To ensure boost inrush current is within specification at startup, the Enable Fast IMO During Startup value must be unchecked in the PSoC Creator IDE. The Enable Fast IMO During Startup option is found in PSoC Creator in the design wide resources (cydwr) file System tab. Un-checking this option configures the device to run at 12 MHz vs 48 MHz during startup while configuring the device. The slower clock speed results in reduced current draw through the boost circuit.

6.2.2.2 Boost Design Process

Correct operation of the boos t converter requires specific component values determined for each designs unique operating conditions. The C BAT capacitor, Inductor, Schottky diode, and CBOOST capacitor components are required with the values specified in the electrical specifications, Table 11-7 on page 74 . The only variable component value is the inductor LBOOST which is primarily sized for correct operation of the boost across operating conditions and secondarily for efficiency. Additional operating region constraints exist for V OUT, VBAT, IOUT, and TA. The following steps must be followed to determine boost converter operating parameters and LBOOST value. 1. Choose desired VBAT, VOUT, TA, and IOUT operating condition ranges for the application. 2. Determine if VBAT and VOUT ranges fit the boost operating range based on the TA range over VBAT and VOUT chart, Figure 11-8 on page 74. If the operating ranges are not met, modify the operating conditions or use an external boost regulator. 3. Determine if the desired ambient temperature (TA) range fits the ambient temperature operating range based on the TA range over VBAT and VOUT chart, Figure 11-8 on page 74. If the temperature range is not met, modify the operating condi- tions and return to step 2, or use an external boost regulator. 4. Determine if the desired output current (IOUT) range fits the output current operating range based on the IOUT range over VBAT and VOUT chart, Figure 11-9 on page 74. If the output current range is not met, modify the operating conditions and return to step 2, or use an external boost regulator. 5. Find the allowed inductor values based on the L BOOST values over VBAT and VOUT chart, Figure 11-10 on page 74. 6. Based on the allowed inductor values, inductor dimensions, inductor cost, boost efficiency, and VRIPPLE choose the optimum inductor value for the system. Boost efficiency and V RIPPLE typical values are provided in the Efficiency vs VBAT and VRIPPLE vs VBAT charts, Figure 11-11 on page 75 through Figure 11-14 on page 75. In general, if high efficiency and low VRIPPLE are most important, then the highest allowed inductor value should be used. If low inductor cost or small inductor size are most important, then one of the smaller allowed inductor values should be used. If the allowed inductor(s) efficiency, V RIPPLE, cost or dimensions are not acceptable for the application than an external boost regulator should be used.

6.3 Reset

CY8C58LP has multiple internal and external reset sources available. The reset sources are:  Power source monitoring - The analog and digital power voltages, VDDA, VDDD, VCCA, and VCCD are monitored in several different modes during power up, active mode, and sleep mode (buzzing). If any of the voltages goes outside predetermined ranges then a reset is generated. The monitors are programmable to generate an interrupt to the processor under certain conditions before reaching the reset thresholds.  External - The device can be reset from an external source by pulling the reset pin (XRES) low. The XRES pin includes an internal pull-up to VDDIO1. VDDD, VDDA, and VDDIO1 must all have voltage applied before the part comes out of reset.  Watchdog timer - A watchdog timer monitors the execution of instructions by the processor. If the watchdog timer is not reset by firmware within a certain period of time, the watchdog timer generates a reset.  Software - The device can be reset under program control. Table 6-4. Chip and Boost Power Modes Compatibility Chip Power Modes Boost Power Modes Chip-active or alternate active mode Boost must be operated in its active mode. Chip-sleep mode Boost can be operated in either active or standby mode. In boost standby mode, the chip must wake up periodi- cally for boost active-mode refresh. Chip-hibernate mode Boost can be operated in its active mode. However, it is recommended not to use the boost in chip hibernate mode due to the higher current consumption in boost active mode.

Document Number: 001-84932 Rev. *N Page 32 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 6-7. Resets The term system reset indicates that the processor as well as analog and digital peripherals and registers are reset. A reset status register show s some of the resets or power voltage monitoring interrupts. The program may examine this register to detect and report certain exception conditions. Thi s register is cleared after a power-on reset. For details see the Technical Reference Manual.

6.3.1 Reset Sources

6.3.1.1 Power Voltage Level Monitors

 IPOR - Initial Power-on-Reset At initial power on, IPOR monitors the power voltages VDDD, VDDA, VCCD and VCCA. The trip level is not precise. It is set to approximately 1 volt (0.75 V to 1.45 V). This is below the lowest specified operating voltage but high enough for the internal circuits to be reset and to hold their reset state. The monitor generates a reset pulse that is at least 150 ns wide. It may be much wider if one or more of the voltages ramps up slowly. After boot, the IPOR circuit is disabled and voltage supervision is handed off to the precise low-voltage reset (PRES) circuit.  PRES - Precise Low-Voltage Reset This circuit monitors the outputs of the analog and digital internal regulators after power up. The regulator outputs are compared to a precise reference voltage. The response to a PRES trip is identical to an IPOR reset. In normal operating mode, the program cannot disable the digital PRES circuit. The analog regulator can be disabled, which also disables the analog portion of the PRES. The PRES circuit is disabled automatically during sleep and hibernate modes, with one exception: During sleep mode the regulators are periodically activated (buzzed) to provide supervisory services and to reduce wakeup time. At these times the PRES circuit is also buzzed to allow periodic voltage monitoring.  ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Interrupt circuits are available to detect when VDDA and VDDD go outside a voltage range. For AHVI, VDDA is compared to a fixed trip level. For ALVI and DLVI, VDDA and VDDD are compared to trip levels that are programmable, as listed in Table 6-5. ALVI and DLVI can also be configured to generate a device reset instead of an interrupt. The monitors are disabled until after IPOR. During sleep mode these circuits are periodically activated (buzzed). If an interrupt occurs during buzzing then the system first enters its wakeup sequence. The interrupt is then recognized and may be serviced. The buzz frequency is adjustable, and should be set to be less than the minimum time that any voltage is expected to be out of range. For details on how to adjust the buzz frequency, see the TRM.

6.3.1.2 Other Reset Sources

 XRES - External Reset PSoC 5LP has a dedicated XRES pin, which holds the part in reset while held active (low). The response to an XRES is the same as to an IPOR reset. The external reset is active low. It includes an internal pull-up resistor. XRES is active during sleep and hibernate modes. After XRES has been deasserted, at least 10 µs must elapse before it can be reasserted.  SRES - Software Reset A reset can be commanded under program control by setting a bit in the software reset register. This is done either direc tly by the program or indirectly by DMA access. The response to a SRES is the same as after an IPOR reset. Another register bit exists to disable this function.  WRES - Watchdog Timer Reset The watchdog reset detects when the software program is no longer being executed correctly. To indicate to the watchdog timer that it is running correctly, the program must periodically reset the timer. If the timer is not reset before a user-specified amount of time, then a reset is generated. Note IPOR disables the watchdog function. The program must enable the watchdog function at an appropriate point in the code by setting a register bit. When this bit is set, it cannot be cleared again except by an IPOR power on reset event. Reset Controller Watchdog Timer External Reset Power Voltage Level Monitors Software Reset Register VDDD VDDA Reset Pin System Reset Processor Interrupt Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Interrupt Supply Normal Volt- age Range Available Trip Settings DLVI VDDD 1.71 V-5.5 V 1.70 V-5.45 V in 250 mV increments ALVI VDDA 1.71 V-5.5 V 1.70 V-5.45 V in 250 mV increments AHVI VDDA 1.71 V-5.5 V 5.75 V

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6.4 I/O System and Routing

PSoC I/Os are extremely flexible. Every GPIO has analog and digital I/O capability. All I/Os have a large number of drive modes, which are set at POR. PSoC also provides up to four individual I/O voltage domains through the VDDIO pins. There are two types of I/O pins on every device; those with USB provide a third type. Both general purpose I/O (GPIO) and special I/O (SIO) provide similar digital functionality. The primary differences are their analog capability and drive strength. Devices that include USB also provide two USBIO pins that support specific USB functionality as well as limited GPIO capability. All I/O pins are available for use as digital inputs and outputs for both the CPU and digital peripherals. In addition, all I/O pins can generate an interrupt. The flexible and advanced capabilities o f the PSoC I/O, combined with any signal to any pin routability, greatly simplify circuit design and board layout. All GPIO pins can be used for analog input, CapSense [9], and LCD segment drive, while SIO pins are used for voltages in excess of VDDA and for programmable output voltages.  Features supported by both GPIO and SIO:  User programmable port reset state  Separate I/O supplies and voltages for up to four groups of I/O  Digital peripherals use DSI to connect the pins  Input or output or both for CPU and DMA  Eight drive modes  Every pin can be an interrupt source configured as rising edge, falling edge or both edges. If required, level sensitive interrupts are supported through the DSI  Dedicated port interrupt vector for each port  Slew rate controlled digital output drive mode  Access port control and configuration registers on either port basis or pin basis  Separat e port read (PS) an d writ e (DR) da ta re gist ers to avoid read modify write errors  Special functionality on a pin by pin basis  Additional features only provided on the GPIO pins:  LCD segment drive on LCD equipped devices  CapSense[9]  Analog input and output capability  Continuous 100 µA clamp current capability  Standard drive strength down to 1.71 V  Additional features only provided on SIO pins:  Higher drive strength than GPIO  Hot swap capability (5 V tolerance at any operating VDD)  Programmable and regulated high input and output drive levels down to 1.2 V  No analog input, CapSense, or LCD capability  Over voltage tolerance up to 5.5 V  SIO can act as a general purpose analog comparator  USBIO features:  Full speed USB 2.0 compliant I/O  Highest drive strength for general purpose use  Input, output, or both for CPU and DMA  Input, output, or both for digital peripherals  Digital output (CMOS) drive mode  Each pin can be an interrupt source configured as rising edge, falling edge, or both edges Note 9. GPIOs with opamp outputs are not recommended for use with Cap Sense.

Document Number: 001-84932 Rev. *N Page 34 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 6-8. GPIO Block Diagram Drive Logic PRT[x]DM0 PRT[x]DR PIN Digital Output Path Digital Input Path PRT[x]SLW LCD Logic & MUX PRT[x]DM1 PRT[x]DM2 PRT[x]LCD_EN PRT[x]LCD_COM_SEG Analog Analog Mux Analog Global Digital System Output PRT[x]BYP PRT[x]BIE Bidirectional Control Capsense Global Control Switches Pin Interrupt Signal Digital System Input PRT[x]PS PRT[x]CTL Input Buffer Disable Display Data Interrupt Logic PICU[x]INTTYPE[y] PICU[x]INTSTAT Vddio Vddio Vddio Slew Cntl LCD Bias Bus 5 PRT[x]AMUX PRT[x]AG CAPS[x]CFG1 OE In PRT[x]SYNC_OUT PRT[x]DBL_SYNC_IN PICU[x]INTSTAT Naming Convention Port Number Pin Number 1 0

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6.4.1 Drive Modes

Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are used for each pin (DM[2:0] ) and set in the PRTxDM[2:0] registers. Figure 6-11 depicts a simplified pin view based on each of the eight drive modes. Table 6-6 shows the I/O pin’s drive state based on the port data register value or digital array signal if bypass mode is selected. Note that the actual I/O pin voltag e is determined by a combination of the selected drive mode and the load at the pin. For example, if a GPIO pin is configured f or resistive pull-up mode and driven high while the pin is floatin g, the voltage measured at the pin is a high logic state. If the same GPIO pin is externally tied to ground then the voltage unmeasured at the pin is a low logic state. Figure 6-11. Drive Mode Table 6-6. Drive Modes Diagram Drive Mode PRTxDM2 PRTxDM1 PRTxDM0 PRTxDR = 1 PRTxDR = 0

0 High-impedance analog 0 0 0 High-Z High-Z

1 High-impedance digital 0 0 1 High-Z High-Z

2 Resistive pull-up

[10] 0 1 0 Res High (5K) Strong Low

3 Resistive pull-down [10] 0 1 1 Strong High Res Low (5K)

4 Open drain, drives low 1 0 0 High-Z Strong Low

5 Open drain, drive high 1 0 1 Strong High High-Z

6 Strong drive 1 1 0 Strong High Strong Low

7 Resistive pull-up and pull-down

[10] 1 1 1 Res High (5K) Res Low (5K) Out In Pin Out In Pin Out In Pin Out In Pin Out In Pin Out In Pin Out In Pin Out In Pin 0. High Impedance Analog 1. High Impedance Digital 2. Resistive Pull-Up 3. Resistive Pull-Down 4. Open Drain, Drives Low 5. Open Drain, Drives High 6. Strong Drive 7. Resistive Pull-Up and Pull-Down VDD VDD VDD VDD VDD An An An An AnAnAnAn connection is driven from either the Digital System (when the Digital Output terminal is connected) or the Data Register (when HW connection is disabled). connection drives the Pin State register, and the Digital System if the Digital Input terminal is enabled and connected. connection connects to the Analog System. Note 10. Resistive pull-up and pull-down are not available with SIO in regulated output mode.

Document Number: 001-84932 Rev. *N Page 37 of 139 PSoC® 5LP: CY8C58LP Family Datasheet The USBIO pins (P15[7] and P15[6]), when enabled for I/O mode, have limited drive mode control. The drive mode is set using th e PRT15.DM0[7, 6] register. A resistive pull option is also available at the USBIO pins, which can be enabled using the PRT15.DM1[7, 6] register. When enabled for USB mode, the drive mode control has no impact on the configuration of the USB pins. Unlike the GPIO and SIO configurations, the port wide configuration registers d o not configure the USB drive mode bits. Table 6-7 shows the drive mode configuration for the USBIO pins.  High impedance analog The default reset state with both the output driver and digital input buffer turned off. This prevents any current from flowing in the I/O’s digital input buffer due to a floating voltage. Th is state is recommended for pins that are floating or that support an analog voltage. High impedance analog pins do not provide digital input functionality. To achieve the lowest chip current in sleep modes, all I/Os must either be configured to the high impedance analog mode, or have their pins driven to a power supply rail by the PSoC device or by external circuitry.  High impedance digital The input buffer is enabled for digital signal input. This is t he standard high impedance (HiZ) state recommended for digital inputs.  Resistive pull-up or resistive pull-down Resistive pull-up or pull-down, respectively, provides a series resistance in one of the data states and strong drive in the other. Pins can be used for dig ital input and output in these modes. Interfacing to mech anical switches is a common application for these modes. Resistive pull-up and pull-down are not available with SIO in regulated output mode.  Open drain, drives high and open drain, drives low Open drain modes provide high impedance in one of the data states and strong drive in the other. Pins can be used for digital input and output in these modes. A common application for these modes is driving the I 2C bus signal lines.  Strong drive Provides a strong CMOS output drive in either high or low state. This is the standard output mode for pins. Strong Drive mode pins must not be used as inputs under normal circumstances. This mode is often used to drive digital output signals or external FETs.  Resistive pull-up and pull-down Similar to the resistive pull-up and resistive pull-down modes except the pin is always in series with a resistor. The high data state is pull-up while the low data state is pull-down. This mode is most often used when other signals that may cause shorts can drive the bus. Resistive pull-up and pull-down are not available with SIO in regulated output mode.

6.4.2 Pin Registers

Registers to configure and interact with pins come in two forms that may be used interchangeably. All I/O registers are available in the standard port form, wher e each bit of the register corresponds to one of the port pins. This register form is efficient for quickly reconfiguring multiple p ort pins at the same time. I/O registers are also available in pin form, which combines th e eight most commonly used port register bits into a single register for each pin. This enables very fast configuration changes to individual pins with a single register write.

6.4.3 Bidirectional Mode

High speed bidirectional capability allows pins to provide both the high impedance digital drive mode for input signals and a second user selected drive mode such as strong drive (set using PRTxDM[2:0] registers) for output signals on the same pin, based on the state of an auxiliary control bus signal. The bidirectional capability is useful for processor busses and communications interfaces such as the SPI Slave MISO pin that requires dynamic hardware control of the output buffer. The auxiliary control bus routes up to 16 UDB or digital peripheral generated output enable signals to one or more pins.

6.4.4 Slew Rate Limited Mode

GPIO and SIO pins have fast and slow output slew rate options for strong and open drain drive modes, not resistive drive modes. Because it results in reduced EMI, the slow edge rate option is recommended for signals that are not speed critical, generally less than 1 MHz. The fast slew rate is for signals between 1 MHz and 33 MHz. The slew rate is indiv idually configurable for each pin, and is set by the PRTxSLW registers. Table 6-7. USBIO Drive Modes (P15[7] and P15[6]) PRT15.DM1[7,6] Pull up enable PRT15.DM0[7,6] Drive Mode enable PRT15.DR[7,6] = 1 PRT15.DR[7,6] = 0 Description 0 0 High Z Strong Low Op en Drain, Strong Low 0 1 Strong High Strong Low Strong Outputs 1 0 Res High (5k) Strong Low Resi stive Pull Up, Strong Low 1 1 Strong High Strong Low Strong Outputs

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6.4.5 Pin Interrupts

All GPIO and SIO pins are able to generate interrupts to the system. All eight pins in each port interface to their own Port Interrupt Control Unit (PICU) and associated interrupt vector. Each pin of the port is independently configurable to detect rising edge, falling edge, both edge interrupts, or to not generate an interrupt. Depending on the configured mode for each pin, each time an interrupt event occurs on a pin, its corresponding status bit of the interrupt status register is set to “1” and an interrupt reques t is sent to the interrupt controller. Each PICU has its own interru pt vector in the interrupt controller and the pin status register providing easy determination of the interrupt source down to the pin level. Port pin interrupts remain active in all sleep modes allowing the PSoC device to wake from an ex ternally generated interrupt. While level sensitive interrupts are not directly supported; Universal Digital Blocks (UDB) pr ovide this functionality to th e system when needed.

6.4.6 Input Buffer Mode

GPIO and SIO input buffers can be configured at the port level for the default CMOS input thresholds or the optional LVTTL input thresholds. All input buffers incorporate Schmitt triggers for input hysteresis. Additionally, individual pin input buffers can be disabled in any drive mode.

6.4.7 I/O Power Supplies

Up to four I/O pin power supplies are provided depending on the device and package. Each I/O supply must be less than or equal to the voltage on the chip’s analog (VDDA) pin. This feature allows users to provide different I/O voltage levels for differ ent pins on the device. Refer to the specific device package pinout to determine VDDIO capability for a given port and pin. The SIO port pins support an additiona l regulated high output capability, as described in Adjustable Output Level.

6.4.8 Analog Connections

These connections apply only to GPIO pins. All GPIO pins may be used as analog inputs or outputs. The analog voltage present on the pin must not exceed the VDDIO supply voltage to which the GPIO belongs. Each GPIO may connect to one of the analog global busses or to one of the analog mux buses to connect any pin to any internal analog resource such as ADC or comparators. In addition, select pins provide direct connections to specific analog features such as the high current DACs or uncommitted opamps.

6.4.9 CapSense

This section applies only to GPIO pins. All GPIO pins may be used to create CapSense buttons and sliders [11]. See the “CapSense” section on page 59 for more information.

6.4.10 LCD Segment Drive

This section applies only to GPIO pins. All GPIO pins may be used to generate Segment and Common drive signals for direct glass drive of LCD glass. See the “LCD Direct Drive” section on page 58 for details.

6.4.11 Adjustable Output Level

This section applies only to SIO pins. SIO port pins support th e ability to provide a regulated high output level for interface to external signals that are low er in voltage than the SIO’s respective VDDIO. SIO pins are individually configurable to output either the standard VDDIO level or the regulated output, which is based on an internally generated reference. Typically a voltage DAC (VDAC) is used to generate the reference (see Figure 6-12). The “DAC” section on page 59 has more details on VDAC use and reference routing to the SIO pins. Resistive pull-up and pull-down drive modes are not available with SIO in regulated output mode.

6.4.12 Adjustable Input Level

This section applies only to SIO pins. SIO pins by default support the standard CMOS and LVTTL input levels but also support a differential mode with programmable levels. SIO pins are grouped into pairs. Each pair shares a reference generator block which, is used to set the digital input buffer reference level for interface to external signals that differ in voltage from VDDIO . The reference sets the pins voltage threshold for a high logic level (see Figure 6-12). Available input thresholds are:  0.5 × VDDIO  0.4 × VDDIO  0.5 × VREF  VREF Typically a voltage DAC (VDAC) generates the VREF reference. DAC on page 59 has more details on VDAC use and reference routing to the SIO pins. Figure 6-12. SIO Reference for Input and Output PIN Drive Logic Driver Vhigh Reference GeneratorSIO_Ref Digital Input Digital Output Input Path Output Path Vinref Voutref Note 11. GPIOs with opamp outputs are not recommended for use with CapSense.

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6.4.13 SIO as Comparator

This section applies only to SIO pins. The adjustable input level feature of the SIOs as explained in the Adjustable Input Level on page 38 can be used to construct a comparator. The threshold for the comparator is provided by the SIO's reference generator. The reference generator has the option to set the analog signal routed through the analog global line as threshold for the comparator. Note that a pair of SIO pins share the same threshold. The digital input path in Figure 6-9 on page 35 illustrates this functionality. In the figure, ‘Reference level’ is the analog signal routed through the analog global. The hysteresis feature can also be enabled for the input buffer of the SIO, which increases noise immunity for the comparator.

6.4.14 Hot Swap

This section applies only to SIO pins. SIO pins support ‘hot swap’ capability to plug into an application without loading the signals that are connected to the SIO pins even when no power is applied to the PSoC device. This allows the unpowered PSoC to maintain a high impedance load to the external device while also preventing the PSoC from being powered through a SIO pin’s protection diode. Powering the device up or down while connected to an operational I2C bus may cause transient states on the SIO pins. The overall I2C bus design should take this into account.

6.4.15 Overvoltage Tolerance

All I/O pins provide an overvoltage tolerance feature at any operating VDD.  There are no current limitations for the SIO pins as they present a high impedance load to the external circuit.  The GPIO pins must be limited to 100 µA using a current limiting resistor. GPIO pins clamp the pin voltage to approximately one diode above the VDDIO supply.  In case of a GPIO pin configured for analog input/output, the analog voltage on the pin must not exceed the VDDIO supply voltage to which the GPIO belongs. A common application for this feature is connection to a bus such as I2C where different devices are running from different supply voltages. In the I 2C case, the PSoC chip is configured into the Open Drain, Drives Low mode for the SIO pin. This allows an external pull-up to pull the I2C bus voltage above the PSoC pin supply. For example, the PSoC chip could operate at 1.8 V, and an external device could run from 5 V. Note that the SIO pin’s VIH and VIL levels are dete rmined by the associated VDDIO supply pin. The SIO pin must be in one of the following modes: 0 (high impedance analog), 1 (high impedance digital), or 4 (open drain drives low). See Figure 6-11 for details. Absolute maximum ratings for the device must be observed for all I/O pins.

6.4.16 Reset Configuration

While reset is active all I/Os are reset to and held in the Hig h Impedance Analog state. After reset is released, the state can be reprogrammed on a port-by-port basis to pull-down or pull-up. To ensure correct reset operation, the port reset configuration data is stored in special nonvolatile registers. The stored res et data is automatically transferred to the port reset configurati on registers at reset release.

6.4.17 Low Power Functionality

In all low power modes the I/O pins retain their state until the part is awakened and changed or reset. To awaken the part, use a pin interrupt, because the port interrupt logic continues to function in all low power modes.

6.4.18 Special Pin Functionality

Some pins on the device include additional special functionality in addition to their GPIO or SIO functionality. The specific special function pins are listed in “Pinouts” on page 6. The special features are:  Digital  4- to 25-MHz crystal oscillator  32.768-kHz crystal oscillator  Wake from sleep on I2C address match. Any pin can be used for I2C if wake from sleep is not required.  JTAG interface pins  SWD interface pins  SWV interface pins  TRACEPORT interface pins  External reset  Analog  Opamp inputs and outputs  High current IDAC outputs  External reference inputs

6.4.19 JTAG Boundary Scan

The device supports standard JTAG boundary scan chains on all pins for board level test.

Document Number: 001-84932 Rev. *N Page 40 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 7. Digital Subsystem The digital programm able system creates a pplication specific combinations of both standard and advanced digital peripherals and custom logic functions. These peripherals and logic are then interconnected to each other and to any pin on the device, providing a high level of design flexibility and IP security. The features of the digital programmable system are outlined here to provide an overview of capabilities and architecture. You do not need to interact directly with the programmable digital system at the hardware and regi ster level. PSoC Creator provides a high level schematic capture graphical interface to automatically place and route resources similar to PLDs. The main components of the digital programmable system are:  Universal Digital Blocks (UDB) - These form the core functionality of the digital programmable system. UDBs are a collection of uncommitted logic (PLD) and structural logic (Datapath) optimized to create all common embedded peripherals and customized functionality that are application or design specific.  Universal Digital Block array - UDB blocks are arrayed within a matrix of programmable interconnect. The UDB array structure is homogeneous and allows for flexible mapping of digital functions onto the array. The array supports extensive and flexible routing interconnects between UDBs and the Digital System Interconnect.  Digital System Interconnect (DSI) - Digital signals from Universal Digital Blocks (UDBs), fixed function peripherals, I/O pins, interrupts, DMA, and other system core signals are attached to the Digital System Interconnect to implement full featured device connectivity. The DSI allows any digital function to any pin or other feature routability when used with the Universal Digital Block array. Figure 7-1. CY8C58LP Digital Programmable Architecture

7.1 Example Peripherals

The flexibility of the CY8C58LP family’s UDBs and analog blocks allow the user to create a wide range of components (peripherals). The most common peripherals were built and characterized by Cypress and are shown in the PSoC Creator component catalog, however, users may also create their own custom components using PSoC Creator. Using PSoC Creator, users may also create their ow n components for reuse within their organization, for example sensor interfaces, proprietary algorithms, and display interfaces. The number of components available through PSoC Creator is too numerous to list in the datasheet, and the list is always growing. An example of a component available for use in CY8C58LP family, but, not explicitly called out in this datasheet is the UART component.

7.1.1 Example Digital Components

The following is a sample of the digital components available in PSoC Creator for the CY8C58LP family. The exact amount of hardware resources (UDBs, routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component.  Communications  I2C  UART  SPI  Functions  EMIF  PWMs  Timers  Counters  Logic  NOT  OR  XOR  AND

7.1.2 Example Analog Components

The following is a sample of the analog components available in PSoC Creator for the CY8C58LP family. The exact amount of hardware resources (SC/CT blocks, routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component.  Amplifiers  TIA  PGA  opamp  ADCs  Delta-Sigma  Successive Approximation (SAR)  DACs  Current  Voltage  PWM  Comparators  Mixers IO Port Digital Core System and Fixed Function Peripherals UDB Array UDB Array IO PortIO Port IO Port DSI Routing Interface DSI Routing Interface Digital Core System and Fixed Function Peripherals UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB

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7.1.3 Example System Function Components

The following is a sample of the system function components available in PSoC Creator for the CY8C58LP family. The exact amount of hardware resources (UDBs, DFB taps, SC/CT blocks, routing, RAM, flash) used by a component varies with the features selected in PSoC Creator for the component.  CapSense  LCD Drive  LCD Control  Filters

7.1.4 Designing with PSoC Creator

7.1.4.1 More Than a Typical IDE

A successful design tool allows for the rapid development and deployment of both simple and complex designs. It reduces or eliminates any learning curve. It makes the integration of a new design into the production stream straightforward. PSoC Creator is that design tool. PSoC Creator is a full featured Integrated Development Environment (IDE) for hardware and software design. It is optimized specifically for PSoC devices and combines a modern, powerful software development platform with a sophisticated graphical design tool. This unique combination of tools makes PSoC Creator the most flexible embedded design platform available. Graphical design entry simplifies the task of configuring a particular part. You can select the required functionality from an extensive catalog of components and place it in your design. All components are parameterized and have an editor dialog that allows you to tailor functionality to your needs. PSoC Creator automatically configures clocks and routes the I/O to the selected pins and then generates APIs to give the application complete control over the hardware. Changing the PSoC device configuration is as simple as adding a new component, setting its parameters, and rebuilding the project. At any stage of development you are free to change the hardware configuration and even the target processor. To retarget your application (hardware and software) to new devices, even from 8- to 32-bit families, just select the new device and rebuild. You also have the ability to change the C compiler and evaluate an alternative. Components are designed for portability and are validated against all devices, from all families, and against a ll supported tool chains. Switching compilers is as easy as editing the from the project options a nd rebuilding the application wit h no errors from the generated APIs or boot code.

7.1.4.2 Component Catalog

The component catalog is a repository of reusable design elements that select device f unctionality and customize your PSoC device. It is populated with an impressive selection of content; from simple primitives such as l ogic gates and device registers, through the digital timers, counters and PWMs, plus analog components such as ADCs, DACs, and filters, and communication protocols, such as I 2C, USB, and CAN. See Example Peripherals on page 40 for more details about available peripherals. All content is fully characterized and carefully documented in datasheets with code examples, AC/DC specifications, and user code ready APIs.

7.1.4.3 Design Reuse

The symbol editor gives you the ability to develop reusable components that can significantly reduce future design time. Just draw a symbol and associate that symbol with your proven design. PSoC Creator allows for the placement of the new symbol anywhere in the component catalog along with the content provided by Cypress. You can then reuse your content as many times as you want, and in any number of projects, without ever having to revisit the details of the implementation.

7.1.4.4 Software Development

Anchoring the tool is a moder n, highly customizable user interface. It includes project management and integrated editors for C and assembler source code, as well the design entry tools. Project build control leverages compiler technology from top commercial vendors such as Arm Limited, Keil™, and CodeSourcery (GNU). Free versions of Keil C51 and GNU C Compiler (GCC) for Arm, with no restrictions on code size or end product distribution, are include d with the tool distribution. Upgrading to more optimizing compilers is a snap with support for the professional Keil C51 product and Arm RealView™ compiler.

7.1.4.5 Nonintrusive Debugging

With JTAG (4-wire) and SWD (2-wire) debug connectivity available on all devices, the PSoC Creator debugger offers full control over the target dev ice with minimum intrusion. Breakpoints and code execution commands are all readily available from toolbar buttons and an impressive lineup of windows—register, locals, watch, call stack, memory and peripherals—make for an unparalleled level of visibility into t he system. PSoC Creator contains a ll the tools necessary to complete a design, and then to maintain and extend that design for years to come. All steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity.

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7.2 Universal Digital Block

The Universal Digital Block (UDB) represents an evolutionary step to the next generation of PSoC embedded digital peripheral functionality. The architecture in first generation PSoC digita l blocks provides coarse progra mmability in which a few fixed functions with a small number of options are available. The new UDB architecture is the optimal balance between configuration granularity and efficient imple mentation. A cornerstone of this approach is to provide the ability to customize the devices digital operation to match application requirements. To achieve this, UDBs consist of a combination of uncommitted logic (PLD), structured logic (Datapath), and a flexible routin g scheme to provide interconnect between these elements, I/O connections, and other peripherals. UDB functionality ranges from simple self contained functions that are implemented in one UDB, or even a portion of a UDB (unused resources are available for other functions), to more complex functions that require multiple UDBs. Examples of basic functions are timers, counters, CRC generators, PWMs, dead band generators, and communications functions, such as UARTs, SPI, and I 2C. Also, the PLD blocks and connectivity provide full featured general purpose programmable logic within the limits of the available resources. Figure 7-2. UDB Block Diagram The main component blocks of the UDB are:  PLD blocks - There are two small PLDs per UDB. These blocks take inputs from the routing array and form registered or combinational sum-of-products logic. PLDs are used to implement state machines, state bits, and combinational logic equations. PLD configuration is automatically generated from graphical primitives.  Datapath Module - This 8-bit wide datapath contains structured logic to implement a dynamically configurable ALU, a variety of compare configurations and condition generation. This block also contains input/output FIFOs, which are the primary parallel data interface between the CPU/DMA system and the UDB.  Status and Control Module - The primary role of this block is to provide a way for CPU firmware to interact and synchronize with UDB operation.  Clock and Reset Module - This block provides the UDB clocks and reset selection and control.

7.2.1 PLD Module

The primary purpose of the PLD blocks is to implement logic expressions, state machines, sequencers, look up tables, and decoders. In the simplest use model, consider the PLD blocks as a standalone resource onto which general purpose RTL is synthesized and mapped. The more common and efficient use model is to create digital functions from a combination of PLD and datapath blocks, where the PLD implements only the random logic and state portion of the function while the datapath (ALU) implements the more structured elements. Figure 7-3. PLD 12C4 Structure One 12C4 PLD block is shown in Figure 7-3. This PLD has 12 inputs, which feed across eight product terms. Each product term (AND function) can be from 1 to 12 inputs wide, and in a given product term, the true (T) or complement (C) of each input can be selected. The product terms are summed (OR function) to create the PLD outputs. A sum can be from 1 to 8 product terms wide. The 'C' in 12C4 indicates that the width of the OR gate (in this case 8) is constant across all outputs (rather than variab le as in a 22V10 device). This PLA like structure gives maximum flexibility and insures that all inputs and outputs are permutable for ease of allocation by the software tools. There are two 12C4 PLDs in each UDB.

7.2.2 Datapath Module

The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band generators, and many others. PLD 12C4 (8 PTs) PLD 12C4 (8 PTs) Datapath Clock and Reset Control Routing Channel Datapath Chaining PLD Chaining Status and Control PT0 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC TC PT1 PT2 PT3 PT4 PT5 PT6 PT7 TTTTTTTT TTTTTTTT TTTTTTTT TTTTTTTT AND Array OR Array MC0 MC1 MC2 OUT0 OUT1 OUT2 OUT3 MC3 Carry In Carry Out

Document Number: 001-84932 Rev. *N Page 43 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 7-4. Datapath Top Level

7.2.2.1 Working Registers

The datapath contains six prima ry working registers, which are accessed by CPU firmware or DMA during normal operation.

7.2.2.2 Dynamic Configuration RAM

Dynamic configuration is the ability to change the datapath function and internal configuration on a cycle-by-cycle basis, under sequencer control. This is implemented using the 8-word x 16-bit configuration RAM, which stores eight unique 16-bit wide configurations. The address input to this RAM controls the sequence, and can be routed from any block connected to the UDB routing matrix, most typically PLD logic, I/O pins, or from the outputs of this or other datapath blocks. ALU The ALU performs eight general purpose functions. They are:  Increment  Decrement  Add  Subtract  Logical AND  Logical OR  Logical XOR  Pass, used to pass a value through the ALU to the shift register, mask, or another UDB register Independent of the ALU operation, these functions are available:  Shift left  Shift right  Nibble swap  Bitwise OR mask PI ALU Mask Shift Data Registers Output Muxes FIFOs Accumulators PO Output to Programmable Routing Chaining Dynamic Configuration RAM

8 Word X 16 Bit

(To/From Programmable Routing) Input from Programmable Routing Input Muxes To/From Next Datapath To/From Previous Datapath Datapath Control PHUB System Bus R/W Access to All Registers Conditions: 2 Compares,

2 Zero Detect, 2 Ones

Table 7-1. Working Datapath Registers Name Function Description A0 and A1 Accumulators These are sources and sinks for the ALU and also sources for the compares. D0 and D1 Data Registers The se are sources for the ALU and sources for the compares. F0 and F1 FIFOs These are the primary interface to the system bus. They can be a data source for the data registers and accumulators or they can capture data from the accumu- lators or ALU. Each FIFO is four bytes deep.

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7.2.2.3 Conditionals

Each datapath has two compares, with bit masking options. Compare operands include the two accumulators and the two data registers in a variety of configurations. Other conditions include zero detect, all ones detect, and overflow. These conditions are the primary datapath outputs, a selection of which can be driven out to the UDB routing matrix. Conditional computation can use the built in chaining to neighboring UDBs to operate on wider data widths without the need to use routing resources.

7.2.2.4 Variable MSB

The most significant bit of an arithmetic and shift function can be programmatically specified. This supports variable width CRC and PRS functions, and in conjunction with ALU output masking, can implement arbitrary width timers, counters and shift blocks.

7.2.2.5 Built-in CRC/PRS

The datapath has built in support for single cycle Cyclic Redundancy Check (CRC) computation and Pseudo Random Sequence (PRS) generation of arbitrary width and arbitrary polynomial. CRC/PRS functions longer than 8 bits may be implemented in conjunction with PLD logic, or built in chaining may be use to extend the function into neighboring UDBs.

7.2.2.6 Input/Output FIFOs

Each datapath contains two four-byte deep FIFOs, which can be independently configured as an input buffer (system bus writes to the FIFO, datapath internal reads the FIFO), or an output buffer (datapath internal writes to the FIFO, the system bus reads from the FIFO). The FIFOs generate status that are selectable as datapath outputs and can ther efore be driven to the routing, to interact with sequencers, interrupts, or DMA. Figure 7-5. Example FIFO Configurations

7.2.2.7 Chaining

The datapath can be configured to chain conditions and signals such as carries and shift data with neighboring datapaths to create higher precision arithmetic, shift, CRC/PRS functions.

7.2.2.8 Time Multiplexing

In applications that are over sampled, or do not need high clock rates, the single ALU block in the datapath can be efficiently shared with two sets of registers and condition generators. Carry and shift out data from the ALU are registered and can be selected as inputs in subsequent cycles. This provides support for 16-bit functions in one (8-bit) datapath.

7.2.2.9 Datapath I/O

There are six inputs and six outputs that connect the datapath to the routing matrix. Inputs f rom the routing provide the configuration for the datapath operation to perform in each cycle, and the serial data inputs. Inputs can be routed from other UDB blocks, other device peripherals, device I/O pins, and so on. The outputs to the routing can be selected from the generated conditions, and the serial data outputs. Outputs can be routed to other UDB blocks, device perip herals, interrupt and DMA controller, I/O pins, and so on.

7.2.3 Status and Control Module

The primary purpose of this circuitry is to coordinate CPU firmware interaction with internal UDB operation. Figure 7-6. Status and Control Registers The bits of the control register, which may be written to by th e system bus, are used to drive into the routing matrix, and thus provide firmware with the opportunity to control the state of UDB processing. The status register is read-only and it allows internal UDB state to be read out onto the system bus directly from internal routing. This allows firmware to monitor the state of UDB processing. Each bit of these registers has programmable connections to the routing matrix and routing connections are made depending on the requirements of the application.

7.2.3.1 Usage Examples

As an example of control input, a bit in the control register c an be allocated as a function enable bit. There are multiple ways to enable a function. In one method the control bit output would be routed to the clock control block in one or more UDBs and serve as a clock enable for the selected UDB blocks. A status example is a case where a PLD or datapath block generated a condition, such as a “compare true” condition that is captured and latched by the status register and then read (and cleared) by CPU firmware.

7.2.3.2 Clock Generation

Each subcomponent block of a UDB including the two PLDs, the datapath, and Status and Control, has a clock selection and control block. This promotes a fine granularity with respect to allocating clocking resources to UDB component blocks and allows unused UDB resources to be used by other functions for maximum system efficiency. System Bus System Bus A0/A1/ALU D0/D1 A0/A1/ALU System Bus A0/A1/ALU System Bus TX/RX Dual Capture Dual Buffer Routing Channel 8-bit Status Register (Read Only) 8-bit Control Register (Write/Read) System Bus

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7.3 UDB Array Description

Figure 7-7 shows an example of a 16 UDB array. In addition to the array core, there are a DSI routing interfaces at the top a nd bottom of the array. Other interfaces that are not explicitly shown include the system interfaces for bus and clock distribution. The UDB array includes multiple horizontal and vertical routing channels each comprised of 96 wires. The wire connections to UDBs, at horizontal/vertical intersection and at the DSI interface are highly permutable providing efficient automatic routing in PSoC Creator. Additionally the routing allows wire by wire segmentation along the vertical and horizontal routing to further increase routing flexibility and capability. Figure 7-7. Digital System Interface Structure

7.3.1 UDB Array Programmable Resources

Figure 7-8 shows an example of how functions are mapped into a bank of 16 UDBs. The primary programmable resources of the UDB are two PLDs, one datapath and one status/control register. These resources are allocated independently, because they have independently selectable clocks, and therefore unused blocks are allocated to other unrelated functions. An example of this is the 8-bit Timer in the upper left corner of the array. This function only requires one datapath in the UDB, and therefore the PLD resources may be allocated to another function. A function such as a Quadrature Decoder may require more PLD logic than one UDB can supply and in this case can utilize the unused PLD blo cks in the 8-bit Timer UDB. Programmable resources in the UDB array are generally homogeneous so functions can be mapped to arbitrary boundaries in the array. Figure 7-8. Function Mapping Example in a Bank of UDBs

7.4 DSI Routing Interface Description

The DSI routing interface is a continuation of the horizontal and vertical routing channels at the top and bottom of the UDB array core. It provides general purpose programmable routing between device peripherals, including UDBs, I/Os, analog peripherals, interrupts, DMA and fixed function peripherals. Figure 7-9 illustrates the concept of the digital system interconnect, which connects the UDB array routing matrix with other device peripherals. Any digital core or fixed function peripheral that needs programmable routing is connected to this interface. Signals in this category include:  Interrupt requests from all digital peripherals in the system.  DMA requests from all digital peripherals in the system.  Digital peripheral data signals that need flexible routing to I/Os.  Digital peripheral data signals that need connections to UDBs.  Connections to the interrupt and DMA controllers.  Connection to I/O pins.  Connection to analog system digital signals. UDB UDB HV B UDB UDB HV A UDB UDB HV B HV A UDB UDB HV A UDB UDB HV B UDB UDB HV A HV B HV B HV A HV B HV A HV A HV B HV A HV B UDB UDB UDB UDB System Connections System Connections UDB UDB HV B UDB UDB HV A UDB UDB HV B HV A UDB HV A UDB HV B UDB HV A HV B UDB UDB UDBUDB UDB UDB UART Logic 12-Bit PWM I2C Slave 8-Bit SPI 12-Bit SPI Logic 8-Bit Timer 16-Bit PYRS UDB 8-Bit Timer Quadrature Decoder 16-Bit PWM Sequencer

Document Number: 001-84932 Rev. *N Page 46 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 7-9. Digital System Interconnect Interrupt and DMA routing is very flexible in the CY8C58LP programmable architecture. In addition to the numerous fixed function peripherals that can generate interrupt requests, any data signal in the UDB array routing can also be used to generate a request. A single peripheral may generate multiple independent interrupt requests simplifying system and firmware design. Figure 7-10 shows the structure of the IDMUX (Interrupt/DMA Multiplexer). Figure 7-10. Interrupt and DMA Processing in the IDMUX

7.4.1 I/O Port Routing

There are a total of 20 DSI routes to a typical 8-bit I/O port, 16 for data and four for drive strength control. When an I/O pin is connected to the routing, there are two primary connections available, an input and an output. In conjunction with drive strengt h control, this can implement a bidirectional I/O pin. A data output signal has the option to b e single synchronized (pipelined) and a data input signal has the option to be double synchronized. The synchronization clock is the system clock (see Figure 6-1). Normally all inputs from pins are synchronized as this is required if the CPU interacts with the signal or any signal derived from it. Asynchronous inputs have rare uses. An example of this is a feed through of combinational PLD logic from input pins to output pins. Figure 7-11. I/O Pin Synchronization Routing Figure 7-12. I/O Pin Output Connectivity There are four more DSI connections to a given I/O port to implement dynamic output en able control of pins. This connectivity gives a range of o ptions, from fully ganged 8-bits controlled by one signal, to up to four individually controlled pins. The output enable signal is useful for creating tri-state bidirectional pins and buses. Figure 7-13. I/O Pin Output Enable Connectivity UDB ARRAY Digital System Routing I/F Digital System Routing I/F CAN Interrupt ControllerI2C IO Port Pins DMA Controller IO Port Pins Delta- Sigma ADC ComparatorsDACSSC/CT Blocks Global Clocks EMIFGlobal Clocks Timer Counters SAR ADC DMA termout (IRQs) DMA Controller Interrupt Controller Fixed Function IRQs Edge Detect Edge Detect IRQs UDB Array Fixed Function DRQs DRQs Interrupt and DMA Processing in IDMUX DO DI Port i PIN 0 DO PIN1 DO PIN2 DO PIN3 DO PIN4 DO PIN5 DO PIN6 DO PIN7 DO

8 IO Data Output Connections from the

UDB Array Digital System Interface Port i PIN 0 OE PIN1 OE PIN2 OE PIN3 OE PIN4 OE PIN5 OE PIN6 OE PIN7 OE

4 IO Control Signal Connections from

UDB Array Digital System Interface

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7.5 CAN

The CAN peripheral is a fully functional Controller Area Network (CAN) supporting communication baud rates up to 1 Mbps. The CAN controller implements the CAN2.0A and CAN2.0B specifications as defined in the Bosch specification and conforms to the ISO-11898-1 standard. The CAN protocol was originally designed for automotive applications with a focus on a high level of fault detection. This ensures high communication reliability at a low cost. Because of its success in automotive applications, CAN is used as a standard communication protocol for motion oriented machine control networks (CANOpen) and factory automation applications (DeviceNet). The CAN controller features allow the efficient implementation of higher level protocols without affecting the performance of the microcontroller CPU. Full config uration support is provided in PSoC Creator. Figure 7-14. CAN Bus System Implementation

7.5.1 CAN Features

 CAN2.0A/B protocol implementation - ISO 11898 compliant  Standard and extended frames with up to 8 bytes of data per frame  Message filter capabilities  Remote Transmission Request (RTR) support  Programmable bit rate up to 1 Mbps  Listen Only mode  SW readable error counter and indicator  Sleep mode: Wake the device from sleep with activity on the Rx pin  Supports two or three wire interface to external transceiver (Tx, Rx, and Enable). The three-wire interface is compatible with the Philips PHY; the PHY is not included on-chip. The three wires can be routed to any I/O  Enhanced interrupt controller  CAN receive and transmit buffers status  CAN controller error status including BusOff  Receive path  16 receive buffers each with its own message filter  Enhanced hardware message filter implementation that covers the ID, IDE and RTR  DeviceNet addressing support  Multiple receive buffers linkable to build a larger receive message array  Automatic transmission request (RTR) response handler  Lost received message notification  Transmit path  Eight transmit buffers  Programmable transmit priority  Round robin  Fixed priority  Message transmissions abort capability

7.5.2 Software Tools Support

CAN Controller configuration integrated into PSoC Creator:  CAN Configuration walkthrough with bit timing analyzer  Receive filter setup CAN Node 1 PSoC CAN Controller CAN Transceiver Tx RxEn CAN Node 2 CAN Node n CAN_H CAN_L CAN_H CAN_L CAN_H CAN_L CAN Drivers CAN Bus

Document Number: 001-84932 Rev. *N Page 48 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 7-15. CAN Controller Block Diagram

7.6 USB

PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0 transceiver supporting all four USB transfer types: control, interrupt, bulk, and isochronous. PSoC Creator provides full configuration support. USB interfaces to hosts through two dedicated USBIO pins, which are detailed in the I/O System and Routing on page 33. USB includes the following features:  Eight unidirectional data endpoints  One bidirectional control endpoint 0 (EP0)  Shared 512-byte buffer for the eight data endpoints  Dedicated 8-byte buffer for EP0  Three memory modes  Manual Memory Management with No DMA Access  Manual Memory Management with Manual DMA Access  Automatic Memory Management with Automatic DMA Access  Internal 3.3 V regulator for transceiver  Internal 48 MHz oscillator that auto locks to USB bus clock, requiring no external crystal for USB (USB equipped parts only)  Interrupts on bus and each endpoint event, with device wakeup  USB Reset, Suspend, and Resume operations  Bus powered and self powered modes Figure 7-16. USB TxMessage0 TxReq TxAbort TxMessage7 TxReq TxAbort TxMessage1 TxReq TxAbort TxMessage6 TxReq TxAbort Priority Arbiter RxMessage0 RxMessage15 RxMessage1 RxMessage14 RxMessage Handler Acceptance Code 0 Acceptance Mask 0 Acceptance Code 1 Acceptance Mask 1 Acceptance Code 14 Acceptance Mask 14 Acceptance Code 15 Acceptance Mask 15 RTR RxMessages 0-15 Tx CAN Framer CRC Generator Rx CAN Framer CRC Check Bit Timing Error Detection CRC Form ACK Bit Stuffing Bit Error Overload Arbitration TxInterrupt Request (if enabled) RxInterrupt Request (if enabled) Error Status Χ Error Active Η Error Passive Bus Off Tx Error Counter Rx Error Counter ErrInterrupt Request (if enabled) WakeUp Request Rx Buffer Status RxMessage Available Tx Buffer Status TxReq Pending Rx Tx S I E (Serial Interface Engine) D–Interrupts System Bus External 22 Ω Resistors

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7.7 Timers, Counters, and PWMs

The Timer/Counter/PWM peripheral is a 16-bit dedicated peripheral providing three of the most common embedded peripheral features. As almost all embedded systems use some combination of timers, counters, and PWMs. Four of them have been included on this PSoC device family. Additional and more advanced functionality timers, counters, and PWMs can also be instantiated in Universal Dig ital Blocks (UDBs) as required. PSoC Creator allows you to choose the timer, counter, and PWM features that you need. The too l set utilizes the most optimal resources available. The Timer/Counter/PWM peripheral can select from multiple clock sources, with input and output signals connected through the DSI routing. DSI routing allows input and output connections to any device pin and any internal digital signal accessible through the DSI. Each of the four instances has a compare output, terminal count output (optional complementary compare output), and programmable interrupt request line. The Timer/Counter/PWMs are conf igurable as free running, one shot, or Enable input controlled. The peripheral has timer rese t and capture inputs, and a kill input for control of the comparator outputs. The peripheral supports full 16-bit capture. Timer/Counter/PWM features include:  16-bit timer/counter/PWM (down count only)  Selectable clock source  PWM comparator (configurable for LT, LTE, EQ, GTE, GT)  Period reload on start, reset, and terminal count  Interrupt on terminal count, compare true, or capture  Dynamic counter reads  Timer capture mode  Count while enable signal is asserted mode  Free run mode  One-shot mode (stop at end of period)  Complementary PWM outputs with deadband  PWM output kill Figure 7-17. Timer/Counter/PWM

7.8 I2C

PSoC includes a single fixed-function I2C peripheral. Additional I2C interfaces can be instantiated using Universal Digital Blocks (UDBs) in PSoC Creator, as required. The I2C peripheral provides a synchronous two-wire interface designed to interface the PSoC device with a two-wire I2C serial communication bus. It is compatible[13] with I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O may be implemented with GPIO or SIO in open-drain modes. To eliminate the need for excessive CPU intervention and overhead, I2C specific support is provided for status detection and generation of framing bits. I2C operates as a slave, a master, or multimaster (Slave and Master) [13]. In slave mode, the unit always listens for a start condition to begin sending or receiving data. Master mode supplies the ability to generate the Start and Stop conditions and initiate transactions. Multimaster mode provides clock synchronization and arbitration to allow multipl e masters on the same bus. If Master mode is enabled and Slave mode is not enabled, the block does not generate interrupts on externally generated Start conditions. I2C interfaces through the DSI routing and allows direct connections to any GPIO or SIO pins. I 2C provides hardware address detect of a 7-bit address without CPU intervention. Additionally the device can wake from low power modes on a 7-bit hardware address match. If wakeup functionality is required, I2C pin connections are limited to one of two specific pairs of SIO pins. See descriptions of SCL and SDA pins in Pin Descriptions on page 12. I2C features include:  Slave and master, transmitter, and receiver operation  Byte processing for low CPU overhead  Interrupt or polling CPU interface  Support for bus speeds up to 1 Mbps  7 or 10-bit addressing (10-bit addressing requires firmware support)  SMBus operation (through firmware support - SMBus supported in hardware in UDBs)  7-bit hardware address compare  Wake from low power modes on address match  Glitch filtering (active and alternate-active modes only) Data transfers follow the format shown in Figure 7-18. After the START condition (S), a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction b it (R/W) - a 'zero' indicates a t ransmission (WRITE), a 'one' indicates a request for data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master. Timer / Counter / PWM 16-bit Clock Reset Enable Capture Kill IRQ Compare TC / Compare! Notes 12. The I2C peripheral is non-compliant with the NXP I2C specification in the following areas: analog glitch filter, I/O VOL/IOL, I/O hysteresis. The I2C Block has a digital glitch filter (not available in sleep mode). The Fast-mode minimum fall-time specification can be met by setting the I/Os to slow speed mode. See the I/O Electrical Specifications in Inputs and Outputs on page 76 for details. 13. Fixed-block I2C does not support undefined bus conditions, nor does it support Repeated Start in Slave mode. These conditions should be avoided, or the UDB-based I2C component should be used instead.

Document Number: 001-84932 Rev. *N Page 50 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 7-18. I2C Complete Transfer Timing

7.8.1 External Electrical Connections

As Figure 7-19 shows, the I 2C bus requires external pull-up resistors (RP). These resistors are primarily determined by the supply voltage, bus speed, and bus capacitance. For detailed information on how to calculate the optimum pull-up resistor value for your design, we recommend using the UM10204 I2C-bus specification and user manual Rev 6, or newer, available from the NXP website at www.nxp.com. Figure 7-19. Connection of Devices to the I 2C Bus For most designs, the default values in Table 7-2 will provide excellent performance without any calculations. The default values were chosen to use standard resistor values between the minimum and maximum limits. The values in Table 7-2 work for designs with 1.8 V to 5.0V V DD, less than 200-pF bus capaci- tance (CB), up to 25 µA of total input leakage (I IL), up to 0.4 V output voltage level (VOL), and a max VIH of 0.7 * VDD. Standard Mode and Fast Mode can use either GPIO or SIO PSoC pins. Fast Mode Plus requires use of SIO pins to meet the V OL spec at 20 mA. Calculation of custom pull-up resistor values is required; if your design does not meet the default assumptions, you use series resistors (RS) to limit injected noise, or you need to maximize the resistor value for low power consumption. Calculation of the ideal pull-up resistor value involves findin g a value between the limits set by three equations detailed in the NXP I 2C specification. These equations are: Equation 1: Equation 2: Equation 3: Equation parameters: V DD = Nominal supply voltage for I2C bus VOL = Maximum output low voltage of bus devices. IOL= Low-level output current from I2C specification TR = Rise Time of bus from I2C specification CB = Capacitance of each bus line including pins and PCB traces VIH = Minimum high-level input voltage of all bus devices VNH = Minimum high-level input noise margin from I 2C specifi- cation IIH = Total input leakage current of all devices on the bus The supply voltage (V DD) limits the minimum pull-up resistor value due to bus devices maximum low output voltage (V OL) specifications. Lower pull-up resistance increases current though the pins and can, therefore, exceed the spec conditions of V OH. Equation 1 is derived using Ohm's law to determine the minimum resistance that will still meet the V OL specification at 3 mA for standard and fast modes, and 20 mA for fast mode plus at the given V DD. Equation 2 determines the maximum pull-up resistance due to bus capacitance. Total bus capacitance is comprised of all pin, wire, and trace capacitance on the bus. The higher the bus capacitance, the lower the pull-up resistance required to meet the specified bus speeds rise time due to RC delays. Choosing a pull-up resistance higher than allowed can result in failing timing requirements resulting in communication errors. Most designs with five or less I 2C devices and up to 20 centimeters of bus trace length have less than 100 pF of bus capacitance. A secondary effect that limits the maximum pull-up resistor value is total bus leakage calculated in Equation 3. The primary source of leakage is I/O pins connected to the bus. If leakage is too high, the pull-ups will have difficulty maintaining an acceptable V IH level causing communication err ors. Most designs with five or less I2C devices on the bus have less than 10 µA of total leakage current. SDA SCL 1 - 7 8 9 1 - 7 8 9 1 - 7 8 9 START Condition ADDRESS R/W ACK DATA ACK DATA ACK STOP Condition Table 7-2. Recommended default Pull-up Resistor Values RP Units Standard Mode – 100 kbps 4.7 k, 5% Ω Fast Mode – 400 kbps 1.74 k, 1% Ω Fast Mode Plus – 1 Mbps 620, 5% Ω RPMIN VDD max() VOL– max()() IOL min()()⁄= RPMAX TR max() 0.8473 CB max()×⁄= RPMAX VDD min() VIH min()– VNH min() IIH max()⁄+=

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7.9 Digital Filter Block

Some devices in the CY8C58LP family of devices have a dedicated HW accelerator block used for digital filtering. The DFB has a dedicated multiplier and accumulator that calculates a 24-bit by 24-bit multiply accumulate in one system clock cycle. This enables the mapping of a direct form FIR filter that approaches a computation rate of one FIR tap for each clock cycle. The MCU can imp lement any of the functions performed by this block, but at a slower rate that consumes significant MCU bandwidth. The PSoC Creator interface provides a wizard to implement FIR and IIR digital filters with coefficients for LPF, BPF, HPF, Notch and arbitrary shape filters. 64 pairs of data and coefficients are stored. This enables a 64 tap FIR filter or up to 4 16 tap filters of either FIR or IIR formulation. Figure 7-20. DFB Application Diagram (pwr/gnd not shown) The typical use model is for data to be supplied to the DFB over the system bus from another on- chip system data source such as an ADC. The data typically passes through main memory or is directly transferred from another chip resource through DMA. The DFB processes this data and passes the result to another on chip resource such as a DAC or main memory through DMA on the system bus. Data movement in or out of the DFB is typically controlled by the system DMA controller but can be moved directly by the MCU. 8. Analog Subsystem The analog programmable system creates application specific combinations of both standard and advanced analog signal processing blocks. These blo cks are then interconnected to each other and also to any pin on the device, providing a high level of design flexibility and IP security. The features of th e analog subsystem are outlined here to provide an overview of capabilities and architecture.  Flexible, configurable analog routing architecture provided by analog globals, analog mux bus, and analog local buses  High resolution Delta-Sigma ADC  Two successive approximation (SAR) ADCs  Four 8-bit DACs that provide either voltage or current output  Four comparators with optional connection to configurable LUT outputs  Four configurable switched capacitor/continuos time (SC/CT) blocks for functions that include opamp, unity gain buffer, programmable gain amplifier, transimpedance amplifier, and mixer  Four opamps for internal use and connection to GPIO that can be used as high current output buffers  CapSense subsystem to enable capacitive touch sensing  Precision reference for generating an accurate analog voltage for internal analog blocks Digital Filter Block write_data read_data System Bus DMA CTRL Data Source (PHUB) Data Dest (PHUB) addrDigital Routing BUSCLK DMA Request

Document Number: 001-84932 Rev. *N Page 52 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 8-1. Analog Subsystem Block Diagram The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and various analog resources and also connections from one analog resource to another. PSoC Creator also provides component libraries that allow you to configure the various analog blocks to perform application specific functions (PGA, transimpedance amplifier, voltage DAC, current DAC, and so on). The tool also generates API interface libraries that allow you to write firmware that allows the communication between the analog peripheral and CPU/Memory.

8.1 Analog Routing

The PSoC 5LP family of devices has a flexible analog routing architecture that provides the capability to connect GPIOs and different analog blocks, and also route signals between different analog blocks. One of the strong p oints of this flexible routin g architecture is that it allows dynamic routing of input and output connections to the different analog blocks. For information on how to make pin selections for optimal analog routing, refer to t he application note, AN58304 - PSoC® 3 and PSoC® 5 - Pin Selection for Analog Designs.

8.1.1 Features

 Flexible, configurable analog routing architecture  16 analog globals (AG) and two analog mux buses (AMUXBUS) to connect GPIOs and the analog blocks  Each GPIO is connected to one analog global and one analog mux bus  Eight analog local buses (abus) to route signals between the different analog blocks  Multiplexers and switches for input and output selection of the analog blocks

8.1.2 Functional Description

Analog globals (AGs) and analog mux buses (AMUXBUS) provide analog connectivity between GPIOs and the various analog blocks. There are 16 AGs in the PSoC 5LP family. The analog routing architecture is divided into four quadrants as shown in Figure 8-2. Each quadrant has four analog globals connected to the corresponding AG through an analog switch. The analog mux bus is a shared routing resource that connects to every GPIO through an analog switch. There are two AMUXBUS routes in PSoC 5LP, one in the left half (AMUXBUSL) and one in the right half (AMUXBUSR), as shown in Figure 8-2. Analog local buses (abus) are routing resources located within the analog subsystem a nd are used to route signals between different analog blocks. There are eight abus routes in PSoC 5LP, four in the left half (abusl [0:3]) and four in the right half (abusr [0:3]) as shown in Figure 8-2. Using the abus saves the analog globals and analog mux buses from being used for interconnecting the analog blocks. Multiplexers and switches exist on the various buses to direct signals into and out of the analog blocks. A multiplexer can have only one connection on at a time, whereas a switch can have multiple connections on simultaneously. In Figure 8-2, multiplexers are indicated by grayed ovals and switches are indicated by transparent ovals. Analog Interface SC/CT Block CMP CMPCMPCMP CapSense Subsystem DSI Array Clock Distribution Decimator Config & Status Registers PHUB CPU Comparators GPIO Port GPIO Port DACDAC DelSig ADC DAC DAC Op Amp Op Amp A N A L O G R O U T I N G A N A L O G R O U T I N G Op Amp Op Amp SC/CT Block SC/CT BlockSC/CT Block SAR ADC SAR ADC Precision Reference

Document Number: 001-84932 Rev. *N Page 53 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 8-2. CY8C58LP Analog Interconnect Vddio0 SIO P12[3] SIO P12[2] GPIO P15[3] GPIO P15[2] SIO P12[1] SIO P12[0] GPIO P3[7] GPIO P3[6] Vddio3 Vccd Vssd Vddd GPIO P6[0] GPIO P6[3] GPIO P6[2] GPIO P6[1] GPIO P15[4] GPIO P15[5] GPIO P2[0] GPIO P2[4] GPIO P2[3] GPIO P2[2] GPIO P2[1] Vddio2 GPIO P2[5] GPIO P2[7] GPIO P2[6] SIO P12[4] SIO P12[5] GPIO P6[4] GPIO P6[5] GPIO P6[6] GPIO P6[7] Vddio1 SIO P12[6] SIO P12[7] USB IO P15[6] USB IO P15[7] Vddd Vssd Vccd GPXT P15[0] GPXT P15[1] GPIO P3[5] GPIO P3[4] GPIO P3[3] GPIO P3[2] GPIO P3[1] AGR[4] AGR[7] AGR[6] AGR[5] AGL[0] AGL[3] AGL[2] AGL[1] AGR[0] AGR[3] AGR[2] AGR[1] *** * Denotes pins on all packages DSM VIDAC 76543210 76543210 76543210 76543210 comp0 comp2 comp1 comp3 COMPARATOR AGL[4] AGL[7] AGL[6] AGL[5] AGL[0] AGL[3] AGL[2] AGL[1] AGR[0] AGR[3] AGR[2] AGR[1] AGR[4] AGR[7] AGR[6] AGR[5] Notes: AMUXBUSRAMUXBUSL i3i2 Rev #60 10-Feb-2012 opamp0 Vssa Vssd Vcca GPIO P0[5] GPIO P0[7] * GPIO P1[3] GPIO P1[2] GPIO P1[1] GPIO P1[0] * * * * GPIO P1[4] * GPIO P1[5] * GPIO P1[6]* GPIO P1[7]* GPIO P5[7] GPIO P5[6] GPIO P5[5] GPIO P5[4] GPIO P4[4] GPIO P4[7] GPIO P4[6] GPIO P4[5] GPIO P5[2] GPIO P5[3] GPIO P5[1] GPIO P5[0] GPIO P4[3] GPIO P4[2] ABUSL0 * ** * * AGL[4] AGL[7] AGL[6] AGL[5] GPIO P4[0] GPIO P4[1] vssa AMUXBUSL AMUXBUSR AMUXBUSL AMUXBUSR AMUXBUSL AMUXBUSR ABUSL1 ABUSL2 ABUSL3 ABUSR3 ABUSR2 ABUSR1 ABUSR0 ExVrefL ExVrefR Ind Vssb Vboost XRES Vssd * * * * Vbat ExVrefRExVrefL qtz_ref refs GPIO P3[0] GPIO P0[6] * LPFin0 out0 in1 out1 sc0 sc1 sc2 sc3 Vin Vref out out out SC/CT out Mux Group Switch Group Connection Large ( ~200 Ohms) Small ( ~870 Ohms ) Switch Resistance Vin Vref Vin Vref Vin Vref Vss ref TS ADC GPIO P0[0] GPIO P0[1] GPIO P0[2] GPIO P0[3] GPIO P0[4] AMUXBUSR AMUXBUSL ANALOG GLOBALS ANALOG BUS 0123 3210 ANALOG BUS ANALOG GLOBALS refbufrrefbuflin out ref in out ref vssa CAPSENSE Vssa SAR ADC Vp (+) Vn (-) (+) Vp (-) Vn ExVrefL2ExVrefL1 refs refs Vrefhi_outVrefhi_out ExVrefL1 opamp2 opamp3 opamp1 ExVrefL2 cmp0_vref (1.024V) vref_cmp1 (0.256V) Vdda sc0_bgref (1.024V) refbuf_vref1 (1.024V) refbuf_vref2 (1.2V) dac_vref (0.256V) dsm0_vcm_vref1 (0.8V) dsm0_qtz_vref2 (1.2V) SAR_vref2 (1.2V) SAR_vref1 (1.024V) abuf_vref_int (1.024V) 32100123 LCD signals are not shown. Vdda VBE vref_vss_ext sc2_bgref (1.024V) sc1_bgref (1.024V) sc3_bgref (1.024V) dsm0_vcm_vref2 (0.7V) vcmsel[1:0] Vdda/3 Vdda/4 refmux[2:0] dsm0_qtz_vref1 (1.024V) Vdda Vdda/2 refmux[2:0] SAR_vref2 (1.2V) SAR_vref1 (1.024V) Vdda Vdda/2 refmux[2:0] vcm DAC0 DAC2 DAC1 DAC3 DSM0 +- +- +-+- SAR0 SAR1 cmp_muxvn[1:0] Vdda/2 bg_vda_swabusl0 cmp1_vref cmp1_vref cmp1_vref refsel[1:0] refbufl_ cmp refbufr_ cmp cmp0_vref (1.024V) abuf_vref_int (1.024V) bg_vda_res_en refbuf_vref1 (1.024V) refbuf_vref2 (1.2V) refsel[1:0] swout swin swout swin swfol swfolswfol swfol swinn swinn swinp swinp swinp swinn swinp swinn LPF vssd en_resvda en_resvda To preserve detail of this figure, this figure is best viewed with a PDF display program or printed on a 11” × 17” paper.

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8.2 Delta-sigma ADC

The CY8C58LP device contains one delta-sigma ADC. This ADC offers differential input, high resolution and excellent linearity, making it a good ADC choice for both audio signal processing and measurement applications. The converter's nominal operation is 16 bits at 48 ksps. The ADC can be configured to output 20-bit resolution at data rates of up to 1 87 sps. At a fixed clock rate, resolution can be traded for faster data rates as shown in Table 8-1 and Figure 8-3. Figure 8-3. Delta-sigma ADC Sample Rates, Range = ±1.024 V

8.2.1 Functional Description

The ADC connects and configures three basic components, input buffer, delta-sigma modulator, and decimator. The basic block diagram is shown in Figure 8-4. The signal from the input muxes is delivered to the delta-sigma modulator either directly or through the input buffer. The delta-sigma modulator performs the actual analog to digital conversion. The modulator over-samples the input and generates a seria l data stream output. This high speed data stream is not useful for most applications without some type of post processing, and so is passed to the decimator through the Analog Interface block. The decimator converts the high speed serial data stream into parallel ADC results. The modulator/decimator frequency response is [(sin x)/x] Figure 8-4. Delta-sigma ADC Block Diagram Resolution and sample rate are controlled by the Decimator. Data is pipelined in the decimator; the output is a function of the last four samples. When the input multiplexer is switched, the output data is not valid until after the fourth sample after th e switch.

8.2.2 Operational Modes

The ADC can be configured by the user to operate in one of four modes: Single Sample, Multi Sample, Continuous, or Multi Sample (Turbo). All four modes a re started by either a write to the start bit in a control register or an assertion of the Star t of Conversion (SoC) signal. When t he conversion is complete, a status bit is set and the output signal End of Conversion (EoC) asserts high and remains high until the value is read by either the DMA controller or the CPU.

8.2.2.1 Single Sample

In Single Sample mode, the ADC performs one sample conversion on a trigger. In this mode, the ADC stays in standby state waiting for the SoC signal to be asserted. When SoC is signaled the ADC performs four successive conversions. The first three conversions prime the decimator. The ADC result is valid and available after the fourth conversion, at which time the EoC signal is generated. To detect the end of conversion, the system may poll a control register for status or configure the external EoC signal to generate an interrupt or invoke a DMA request. When the transfer is done the ADC reenters the standby state where it stays until another SoC event.

8.2.2.2 Continuous

Continuous sample mode is used to take multiple successive samples of a single input signal. Multiplexing multiple inputs should not be done with this mode. There is a latency of three conversion times before the firs t conversion result is availabl e. This is the time required to prime the decimator. After the fir st result, successive conversions are available at the selected sample rate.

8.2.2.3 Multi Sample

Multi sample mode is similar to continuous mode except that the ADC is reset between samples. This mode is useful when the input is switched between multip le signals. The decimator is re-primed between each sample so that previous samples do not affect the current conversion. Upon completion of a sample, the next sample is automatically initiated. The results can be transferred using either firmware polling, interrupt, or DMA. Table 8-1. Delta-sigma ADC Performance Bits Maximum Sample Rate (sps) SINAD (dB) 20 187 – 16 48 k 84 12 192 k 66 8 384 k 431000 10000 100000 1000000e Rate, sps 100 6 8 10 12 14 16 18 20 22 Sample Resolution, bits Continuous Multi-Sample Multi-SampleTurbo Delta Sigma Modulator Decimator 12 to 20 Bit Result EOC SOC Positive Input Mux Negative Input Mux (Analog Routing) Input Buffer

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8.2.2.4 Multi Sample (Turbo)

The multi sample (turbo) mode operates identical to the Multi-sample mode for resolutions of 8 to 16 bits. For resolutions of 17 to 20 bits, the performance is about four times faster th an the multi sample mode, because the ADC is only reset once at the end of conversion. More information on output formats is provided in the Technical Reference Manual.

8.2.3 Start of Conversion Input

The SoC signal is used to start an ADC conversion. A digital clock or UDB output can be used to drive this input. It can be used when the sampling period must be longer than the ADC conversion time or when the ADC must be synchronized to other hardware. This signal is optional and does not need to be connected if ADC is running in a continuous mode.

8.2.4 End of Conversion Output

The EoC signal goes high at the end of each ADC conversion. This signal may be used to trigger either an interrupt or DMA request.

8.3 Successive Approximation ADC

The CY8C58LP family of devices has two Successive Approximation (SAR) ADCs. These ADCs are 12-bit at up to 1 Msps, with single-ended or differential inputs, making them useful for a wide variety of sampling and control applications.

8.3.1 Functional Description

In a SAR ADC an analog input signal is sampled and compared with the output of a DAC. A binary search algorithm is applied to the DAC and used to determine the output bits in succession from MSB to LSB. A block diagram of one SAR ADC is shown in Figure 8-5. Figure 8-5. SAR ADC Block Diagram The input is connected to the analog globals and muxes. The frequency of the clock is 18 times the sample rate; the clock rate ranges from 1 to 18 MHz.

8.3.2 Conversion Signals

Writing a start bit or assertion of a start of frame (SOF) signal is used to start a conversion. SOF can be used in applications where the sampling period is longer than the conversion time, or when the ADC needs to be synchronized to other hardware. This signal is optional and does not need to be connected if the SAR ADC is running in a continuous mode. A digital clock or UDB output can be used to drive this input. When the SAR is first powered up or awakened from any of the sleeping modes, there is a power up wait time of 10 µs before it is ready to start the first conversion. When the conversion is complete, a status bit is set and the output signal end of frame (EOF) asserts and remains asserted until the value is read by either the DMA controller or the CPU . The EOF signal may be used to trigger an interrupt or a DMA request.

8.3.3 Operational Modes

A ONE_SHOT control bit is used to set the SAR ADC conversion mode to either continuous or one conversion per SOF signal. DMA transfer of continuous samples, without CPU intervention, is supported.

8.4 Comparators

The CY8C58LP family of devices contains four comparators. Comparators have these features:  Input offset factory trimmed to less than 5 mV  Rail-to-rail common mode input range (VSSA to VDDA)  Speed and power can be traded off by using one of three modes: fast, slow, or ultra low power  Comparator outputs can be routed to look up tables to perform simple logic functions and then can also be routed to digital blocks  The positive input of the comparators may be optionally passed through a low pass filter. Two filters are provided  Comparator inputs can be connections to GPIO, DAC outputs and SC block outputs

8.4.1 Input and Output Interface

The positive and negative inputs to the comparators come from the analog global buses, the analog mux line, the analog local bus and precision reference through multiplexers. The output from each comparator could be r outed to any of the two input LUTs. The output of that LUT is routed to the UDB DSI. S/H DAC array vin vrefp vrefn comparator SAR digital D0:D11 clock autozero reset clock D0:D11 power filtering POWER GROUND vrefp vrefn

Document Number: 001-84932 Rev. *N Page 56 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 8-6. Analog Comparator

8.4.2 LUT

The CY8C58LP family of devices contains four LUTs. The LUT is a two input, one output lookup table that is driven by any one or two of the comparators in the chip. The output of any LUT is routed to the digital system interface of the UDB array. From the digital system interface of the UDB array, these signals can be connected to UDBs, DMA controller, I/O, or the interrupt controller. The LUT control word written to a register sets the logic function on the output. The available LUT functions and the associated control word is shown in Table 8-2 ANAIF comp 2 comp 0 comp 1 comp 3 LUT 0 LUT 1 LUT 2 LUT 3 4 4 4 4 4 4 4 From Analog Routing From Analog Routing From Analog Routing From Analog Routing UDBs Table 8-2. LUT Function vs. Program Word and Inputs Control Word Output (A and B are LUT inputs) 0000b FALSE (‘0’) 0001b A AND B 0010b A AND (NOT B) 0011b A 0100b (NOT A) AND B 0101b B 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b NOT B 1011b A OR (NOT B) 1100b NOT A 1101b (NOT A) OR B 1110b A NAND B 1111b TRUE (‘1’)

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8.5 Opamps

The CY8C58LP family of devices contain four general purpose opamps. Figure 8-7. Opamp The opamp is uncommitted and can be configured as a gain stage or voltage follower on external or internal signals. See Figure 8-8. In any configuration, the input and output signals can all be connected to the internal global signals and monitored with an ADC, or comparator. The configurations are implemented with switches between the signals and GPIO pins. Figure 8-8. Opamp Configurations The opamp has three speed modes, slow, medium, and fast. The slow mode consumes the least amount of quiescent power and the fast mode consumes the most power. The inputs are able to swing rail-to-rail. The output swing is capable of rail-to-rail operation at low current output, within 50 mV of the rails. Whe n driving high current loads (about 25 mA) the output voltage may only get within 500 mV of the rails.

8.6 Programmable SC/CT Blocks

The CY8C58LP family of devices contains four switched capacitor/continuous time (SC/CT) blocks. Each switched capacitor/continuous time block is built around a single rail-to-rail high bandwidth opamp. Switched capacitor is a circuit design technique that uses capacitors plus switches instead of resistors to create analog functions. These circuits work by moving charge between capacitors by opening and closing different switches. Nonoverlapping in phase clock signals control the switches, so that not all switches are ON simultaneously. The PSoC Creator tool offers a user friendly interface, which allows you to easily program the SC/CT blocks. Switch control and clock phase control configuration is done by PSoC Creator so users only need to determine the application use parameters such as gain, amplifier polarity, V REF connection, and so on. The same opamps and block interfaces are also connectable to an array of resistors which allows the construction of a variety of continuous time functions. The opamp and resistor array is programmable to perform various analog functions including  Naked Operational Amplifier - Continuous Mode  Unity-Gain Buffer - Continuous Mode  Programmable Gain Amplifier (PGA) - Continuous Mode  Transimpedance Amplifier (TIA) - Continuous Mode  Up/Down Mixer - Continuous Mode  Sample and Hold Mixer (NRZ S/H) - Switched Cap Mode  First Order Analog to Digital Modulator - Switched Cap Mode

8.6.1 Naked Opamp

The Naked Opamp presents both inputs and the output for connection to internal or external signals. The opamp has a unity gain bandwidth greater than 6.0 MHz and output drive current up to 650 µA. This is sufficient for buffering internal signals (such as DAC outputs) and driving external loads greater than 7.5 kohms.

8.6.2 Unity Gain

The Unity Gain buffer is a Naked Opamp with the output directly connected to the inverting input for a gain of 1.00. It has a -3 dB bandwidth greater than 6.0 MHz.

8.6.3 PGA

The PGA amplifies an external or internal signal. The PGA can be configured to operate in inverting mode or noninverting mode. The PGA function may be configured for both positive and negative gains as high as 50 and 49 respectively. The gain is adjusted by changing the values of R1 and R2 as illustrated in Figure 8-9. The schematic in Figure 8-9 shows the configuration and possible resistor settings for the PGA. The gain is switched from inverting and non inverting by changing the shared select value of the both the input muxes. The bandwidth for each gain case is listed in Table 8-3. Opamp VREF GPIO GPIO = Analog Switch GPIO Analog Global Bus Analog Internal Bus Analog Global Bus Opamp Vout to Pin Vin Vout to GPIO Vp to GPIO b) External Uncommitted Opamp a) Voltage Follower Vout to Pin Vp Vn To Internal Signals c) Internal Uncommitted Opamp Vn to GPIO GPIO Pin Opamp Opamp

Document Number: 001-84932 Rev. *N Page 58 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 8-9. PGA Resistor Settings The PGA is used in applications where the input signal may not be large enough to achieve the desired resolution in the ADC, or dynamic range of another SC/CT block such as a mixer. The gain is adjustable at runtime, including changing the gain of the PGA prior to each ADC sample.

8.6.4 TIA

The Transimpedance Amplifier (TIA) converts an internal or external current to an output voltage. The TIA uses an internal feedback resistor in a continuous time configuration to convert input current to output voltage.For an input current Iin, the output voltage is VREF - Iin x Rfb, where VREF is the value placed on the non inverting input. The feedback resistor Rfb is programmable between 20 K Ω a n d 1MΩ through a configuration register. Table 8-4 shows the possible values of Rfb and associated configuration settings. Figure 8-10. Continuous Time TIA Schematic The TIA configuration is used for applications where an external sensor's output is current as a function of some type of stimulus such as temperature, light, magnetic flux etc. In a common application, the voltage DAC output can be connected to the V REF TIA input to allow calibration of the external sensor bias current by adjusting the voltage DAC output voltage.

8.7 LCD Direct Drive

The PSoC Liquid Crystal Display (LCD) driver system is a highly configurable peripheral designed to allow PSoC to directly drive a broad range of LCD glass. All voltages are generated on chip, eliminating the need for external components. With a high multiplex ratio of up to 1/16, the CY8C58LP family LCD driver system can drive a maximum of 736 segments. The PSoC LCD driver module was also designed with the conservative power budget of portable devices in mind, enabling different LCD drive modes and power down modes to conserve power. PSoC Creator provides an LCD segment drive component. The component wizard provides easy and flexible configuration of LCD resources. You can specify pins for segments and commons along with other options. The software configures the device to meet the required specifications. This is possible because of the programmability inherent to PSoC devices. Key features of the PSoC LCD segment system are:  LCD panel direct driving  Type A (standard) and Type B (low power) waveform support  Wide operating voltage range support (2 V to 5 V) for LCD panels  Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels  Internal bias voltage generation through internal resistor ladder  Up to 62 total common and segment outputs  Up to 1/16 multiplex for a maximum of 16 backplane/common outputs  Up to 62 front plane/segment outputs for direct drive  Drives up to 736 total segments (16 backplane x 46 front plane)  Up to 64 levels of software controlled contrast  Ability to move display data from memory buffer to LCD driver through DMA (without CPU intervention)  Adjustable LCD refresh rate from 10 Hz to 150 Hz  Ability to invert LCD display for negative image  Three LCD driver drive modes, allowing power optimization Figure 8-11. LCD System Table 8-3. Bandwidth Gain Bandwidth 16 . 0 M H z 24 340 kHz 48 220 kHz 50 215 kHz Table 8-4. Feedback Resistor Settings Configuration Word Nominal Rfb (KΩ) 000b 20 001b 30 010b 40 011b 60 100b 120 101b 250 110b 500 111b 1000 R1 R2 20 k to 980 k S 20 k or 40 k1 Vin Vref Vref Vin Vref Vout Iin Rfb LCD Driver Block UDB DMA Display RAM LCD DAC PIN Global Clock PHUB

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8.7.1 LCD Segment Pin Driver

Each GPIO pin contains an LCD driver circuit. The LCD driver buffers the appropriate output of the LCD DAC to directly drive the glass of the LCD. A register setting determines whether the pin is a common or segment. The pin’s LCD driver then selects one of the six bias voltages to drive the I/O pin, as appropria te for the display data.

8.7.2 Display Data Flow

The LCD segment driver system reads display data and generates the proper output v oltages to the LCD glass to produce the desired image. Display data resides in a memory buffer in the system SRAM. Each time you need to change the common and segment driver voltages, the next set of pixel data moves from the memory buffer into the Port Data Registers via DMA.

8.7.3 UDB and LCD Segment Control

A UDB is configured to generate the global LCD control signals and clocking. This set of signals is routed to each LCD pin driver through a set of dedicated LCD global routing channels. In addition to generating the global LCD control signals, the UDB also produces a DMA request to initiate the transfer of the nex t frame of LCD data.

8.7.4 LCD DAC

The LCD DAC generates the con trast control and bias voltage for the LCD system. The LCD DAC produces up to five LCD drive voltages plus ground, based on the selected bias ratio. The bias voltages are driven out to GPIO pins on a dedicated LCD bias bus, as required.

8.8 CapSense

The CapSense system provides a versatile and efficient means for measuring capacitance in applications such as touch sense buttons, sliders, proximity detection, etc. The CapSense system uses a configuration of system resources, including a few hardware functions primarily targeted for CapSense. Specific resource usage is detailed in the CapSense component in PSoC Creator. A capacitive sensing method using a Delta-Sigma Modulator (CSD) is used. It provides capacitance sensing using a switched capacitor technique with a delta-sigma modulator to convert the sensing current to a digital code.

8.9 Temp Sensor

Die temperature is used to establish programming parameters for writing flash. Die temperature is measured using a dedicated sensor based on a forward biased transistor. The temperature sensor has its own auxiliary ADC.

8.10 DAC

The CY8C58LP parts contain four Digital to Analog Convertors (DACs). Each DAC is 8-bit and can be configured for either voltage or current output. The DACs support CapSense, power supply regulation, and waveform generation. Each DAC has the following features.  Adjustable voltage or current output in 255 steps  Programmable step size (range selection)  Eight bits of calibration to correct ± 25% of gain error  Source and sink option for current output  8 Msps conversion rate for current output  1 Msps conversion rate for voltage output  Monotonic in nature  Data and strobe inputs can be provided by the CPU or DMA, or routed directly from the DSI  Dedicated low-resistance output pin for high-current mode Figure 8-12. DAC Block Diagram

8.10.1 Current DAC

The current DAC (IDAC) can be configured for the ranges 0 to 31.875 µA, 0 to 255 µA, and 0 to 2.04 mA. The IDAC can be configured to source or sink current.

8.10.2 Voltage DAC

For the voltage DAC (VDAC), the current DAC output is routed through resistors. The two ranges available for the VDAC are 0 to 1.02 V and 0 to 4.08 V. In voltage mode any load connected to the output of a DAC should be purely capacitive (the output of the VDAC is not buffered). Reference Source Scaler I source Range 1x , 8x , 64x I sink Range 1x , 8x , 64x R Vout Iout

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8.11 Up/Down Mixer

In continuous time mode, the SC/CT block components are used to build an up or down mixer. Any mixing application contains an input signal frequency and a local oscillator frequency. The polarity of the clock, Fclk, s witches the amplifier between inverting or noninverting gain . The output is the product of th e input and the switching function from the local oscillator, wit h frequency components at the local oscillator plus and minus the signal frequency (Fclk + Fin and Fclk - Fin) and reduced-level frequency components at odd integer multiples of the local oscillator frequency. The local oscillator frequency is provided by the selected clock source for the mixer. Continuous time up and down mixing works for applications with input signals and local oscillator frequencies up to 1 MHz. Figure 8-13. Mixer Configuration

8.12 Sample and Hold

The main application for a sample and hold, is to hold a value stable while an ADC is performing a conversion. Some applications require multiple signals to be sampled simultaneously, such as for power calculations (V and I). PSoC Creator offers a sample and hold component to support this function. Figure 8-14. Sample and Hold Topology (Φ1 and Φ2 are opposite phases of a clock)

8.12.1 Down Mixer

The S+H can be used as a mixer to down convert an input signal. This circuit is a high bandwidth passive sample network that can sample input signals up to 14 MHz. This sampled value is then held using the opamp with a maximum clock rate of 4 MHz. The output frequency is at the difference between the input frequency and the highest integer multiple of the Local Oscillator that is less than the input.

8.12.2 First Order Modulator - SC Mode

A first order modulator is cons tructed by placing the switched capacitor block in an integrator mode and using a comparator to provide a 1-bit feedback to the input. Depending on this bit, a reference voltage is either subtracted or added to the input signal. The block output is the output of the comparator and not the integrator in the modulator case. The signal is downshifted and buffered and then processed by a decimator to make a delta-sigma converter or a counter to make an incremental converter. The accuracy of the sampled data from the first-order modulator is determined from several factors. The main application for this modulator is for a low frequency ADC with high accuracy. Applications include strain gauges, thermocouples, precision voltage, and current measurement. Vref Vout Rmix 0 20 k or 40 k Rmix 0 20 k or 40 k sc_clk sc_clk Vin C2 = 1.7 pF C1 = 850 fF V i n V ref V out C1 C2 2C3 C4 Vref V ref Φ Φ Φ Φ Φ Φ Φ Φ Φ Φ Φ Φ

Document Number: 001-84932 Rev. *N Page 61 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 9. Programming, Debug Interfaces, Resources The Cortex-M3 has internal debugging components, tightly integrated with the CPU, providing the following features:  JTAG or SWD access  Flash Patch and Breakpoint (FPB) block for implementing breakpoints and code patches  Data Watchpoint and Trigger (DWT) block for implementing watchpoints, trigger resources, and system profiling  Embedded Trace Macrocell (ETM) for instruction trace  Instrumentation Trace Macrocell (ITM) for support of printf-style debugging PSoC devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. Four interfaces are available: JTAG, SWD, SWV, and TRACEPORT. JTAG and SWD support all programming and debug features of the device. JTAG also supports standard JTAG scan chains for board level test and chaining multiple JTAG devices to a single JTAG connection. The SWV and TRACEPORT provide trace output from the DWT, ETM, and ITM. TRACEPORT is faster but uses more pins. SWV is slower but uses only one pin. For more information on PSoC 5 programming, refer to the PSoC 5 Device Programming Specification. Cortex-M3 debug and trace functionality enables full device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The PSoC Creator IDE software provides fully integrated programming and debug support for PSoC devices. The low cost MiniProg3 programmer and debugger is designed to provide full programming and debug support of PSoC devices in conjunction with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV interfaces are fully compatible with industry standard third party tools. All Cortex-M3 debug and trace modules are disabled by default and can only be enabled in firmware. If not enabled, the only way to reenable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables them. Disabling debug and trace features, robust flash protection, and hiding custom a nalog and digital functionality inside the PSoC device provide a level of security not possible with multichip application solutions. Additionally, all device interfaces can be permanently disabled (Device Security) for applications conce rned about phishi ng attacks due to a maliciously reprogrammed device. Permanently disabling interfaces is not recommended in most applications because the designer then cannot access the device later. Because all programming, debug, and test interfaces are disabled when Device Security is enabled, PSoCs with Device Security enabled may not be returned for failure analysis.

9.1 JTAG Interface

The IEEE 1149.1 compliant JTAG interface exists on four or five pins (the nTRST pin is optional). The JTAG clock frequency can be up to 12 MHz, or 1/3 of the CPU clock frequency for 8 and 16-bit transfers, or 1/5 of the CPU clock frequency for 32-bit transfers, whichever is least. By default, the JTAG pins are enabled on new devices but the JTAG interface can be disabled, allowing these pins to be used as General Purpose I/O (GPIO) instead. The JTAG interface is used for programming the flash memory, debugging, I/O scan chains, and JTAG device chaining.

Document Number: 001-84932 Rev. *N Page 62 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 9-1. JTAG Interface Connections between PSoC 5LP and Programmer TCK (P1[1] TMS (P1[0]) 5 GND GND TCK TMS 5 XRES Host Programmer PSoC 5 TDO TDI (P1[4]) TDI TDO (P1[3]) nTRST 6 nTRST (P1[5]) 6 1 The voltage levels of Host Programmer and the PSoC 5 voltage domains involved in Programming should be same. The Port 1 JTAG pins and XRES pin are powered by VDDIO1. So, VDDIO1 of PSoC 5 should be at same voltage level as host VDD. Rest of PSoC 5 voltage domains ( VDDD, VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same voltage level as host Programmer. 2 Vdda must be greater than or equal to all other power supplies (Vddd, Vddios) in PSoC 5. 3 For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have the capability to toggle power (Vddd, Vdda, All Vddio s) to PSoC 5. This may typically require external interface circuitry to toggle power which will depend on the programming setup. The power supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other supplies. 4 For JTAG Programming, Device reset can also be done without connecting to the XRES pin or Power cycle mode by using the TMS,TCK,TDI, TDO pins of PSoC 5, and writing to a specific register. But this requires that the DPS setting in NVL is not equal to Debug Ports Disabled 5 By default, PSoC 5 is configured for 4-wire JTAG mode unless user changes the DPS setting. So the TMS pin is unidirectional. But if the DPS setting is changed to non-JTAG mode, the TMS pin in JTAG is bi -directional as the SWD Protocol has to be used for acquiring the PSoC 5 device initially. After switching from SWD to JTAG mode, the TMS pin will be uni-directional. In such a case, unidirectional buffer should not be used on TMS line. 6 nTRST JTAG pin (P1[5]) cannot be used to reset the JTAG TAP controlller during first time programming of PSoC 5 as the default setting is 4-wire JTAG (nTRST disabled). Use the TMS, TCK pins to do a reset of JTAG TAP controller. VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3 1, 2, 3, 4 VSSD, VSSA XRES 4 VDD VDD

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9.2 SWD Interface

The SWD interface is the preferred alternative to the JTAG interface. It requires only two pins instead of the four or fiv e needed by JTAG. SWD provides all of the programming and debugging features of JTAG at the same speed. SWD does not provide access to scan chains or device chaining. The SWD clock frequency can be up to 1/3 of the CPU clock frequency. SWD uses two pins, either two of the JTAG pins (TMS and TCK) or the USBIO D+ and D- pins. The USBIO pins are useful for in system programming of USB solu tions that would otherwise require a separate programming connector. One pin is used for the data clock and the other is used for data input and output. SWD can be enabled on only one of the pin pairs at a time. This only happens if, within 8 μs (key window) after reset, that pin pair (JTAG or USB) receives a predetermined acquire sequence of 1s and 0s. If the NVL latches are set for SWD (see Section 5.5), this sequence need not be applied to the JTAG pin pair. The acquire sequence must always be applied to the USB pin pair. SWD is used for debugging or for programming the flash memory. The SWD interface can be enabled from the JTAG interface or disabled, allowing its pins to be used as GPIO. Unlike JTAG, the SWD interface can always be reacquired on any device during the key window. It can then be used to reenable the JTAG interface, if desired. When using SWD or JTAG pins as standard GPIO, make sure that the GPIO functionality and PCB circuits do not interfere with SWD or JTAG use. Figure 9-2. SWD Interface Connections between PSoC 5LP and Programmer VSSD, VSSA VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3 1, 2, 3 SWDCK (P1[1] or P15[7]) SWDIO (P1[0] or P15[6]) XRES 3 GND GND SWDCK SWDIO XRES Host Programmer PSoC 5 VDD

1 The voltage levels of the Host Programmer and the PSoC 5 voltage domains involved in

programming should be the same. The XRES pin is powered by VDDIO1. The USB SWD pins are powered by VDDD. So for Programming using the USB SWD pins with XRES pin, the VDDD, VDDIO1 of PSoC 5 should be at the same voltage level as Host VDD. Rest of PSoC 5 voltage domains ( VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same voltage level as host Programmer. The Port 1 SWD pins are powered by VDDIO1. So VDDIO1 of PSoC 5 should be at same voltage level as host VDD for Port 1 SWD programming. Rest of PSoC 5 voltage domains ( VDDD, VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same voltage level as host Programmer. 2 Vdda must be greater than or equal to all other power supplies (Vddd, Vddio s) in PSoC 5. 3 For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have the capability to toggle power (Vddd, Vdda, All Vddio s) to PSoC 5. This may typically require external interface circuitry to toggle power which will depend on the programming setup. The power supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other supplies. VDD

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9.3 Debug Features

The CY8C58LP supports the following debug features:  Halt and single-step the CPU  View and change CPU and peripheral registers, and RAM addresses  Six program address breakpoints and two literal access breakpoints  Data watchpoint events to CPU  Patch and remap instruction from flash to SRAM  Debugging at the full speed of the CPU  Compatible with PSoC Creator and MiniProg3 programmer and debugger  Standard JTAG programming and debugging interfaces make CY8C58LP compatible with other popular third-party tools (for example, Arm / Keil)

9.4 Trace Features

The following trace features are supported:  Instruction trace  Data watchpoint on access to data address, address range, or data value  Trace trigger on data watchpoint  Debug exception trigger  Code profiling  Counters for measuring clock cycles, folded instructions, load/store operations, sleep cycles, cycles per instruction, interrupt overhead  Interrupt events trace  Software event monitoring, “printf-style” debugging

9.5 SWV and TRACEPORT Interfaces

The SWV and TRACEPORT interfaces provide trace data to a debug host via the Cypress MiniProg3 or an external trace port analyzer. The 5 pin TRACEPORT is used for rapid transmission of large trace streams. The single pin SWV mode is used to minimize the number of trace pins. SWV is shared with a JTAG pin. If debugging and tracing are done at the same time then SWD may be used with either SWV or TRACEPORT, or JTAG may be used with TRACEPORT, as shown in Table 9-1.

9.6 Programming Features

The JTAG and SWD interfaces provide full programming support. The entire device can be erased, programmed, and verified. Designers can increase flash protection levels to protect firmware IP. Flash protection can only be reset after a full device erase. Individual flash blocks can be erased, programmed, and verified, if block security settings permit.

9.7 Device Security

PSoC 5LP offers an advanced security feature called device security, which permanently disables all test, programming, and debug ports, protecting your application from external access. The device security is activat ed by programming a 32-bit key (0x50536F43) to a Write Once Latch (WOL). The WOL is a type of nonvolatile latch (NVL). The cell itself is an NVL with additional logic wrapped around it. Each WOL device contains four bytes (32 bits) of data. The wrapper outputs a ‘1’ if a super-majority (28 of 32) of its bits match a pre-determined pattern (0x50536F43); it outputs a ‘0’ if this majority is not reached. When the output is 1, the Write Once NV latch locks the part out of Debug and Test modes; it also permanently gates off the ability to erase or alter the contents of the latch. Matching all bits is intentionally not required, so that single (or few) bit failures do not deassert the WOL output. The state of the NVL bits after wafer processing is truly random with no tendency toward 1 or 0. The WOL only locks the part a fter the correct 32-bit key (0x50536F43) is loaded into the NVL's volatile memory, programmed into the NVL's nonvolatile cells, and the part is reset. The output of the WOL is only sampled on reset and used to disable the access. This pr ecaution prevents anyone from reading, erasing, or altering the contents of the internal memory. The user can write the key into the WOL to lock out external access only if no flash p rotection is set (see “Flash Security” section on page 19). However, after setting the values in the WOL, a user still has access to the part until it is reset. Therefore, a user can write the key into the WOL, program the flash protection data, and then reset the part to lock it. If the device is protected with a WOL setting, Cypress cannot perform failure analysis and, therefore, cannot accept RMAs from customers. The WOL can be read out via SWD port to electrically identify protected parts. The user can write the key in WOL to lock out external access only if no flash protection is set. For more information on how to take full advantage of the security features in PSoC see the PSoC 5 TRM. Disclaimer Note the following details of the flash code protection features on Cypress devices. Cypress products meet the specifications contained in their particular Cypress datasheets. C ypress believes that its family of products is one of the most secure families of its kind on t he market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of t hese methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantl y evolving. We at Cypress are committed to continuously improving the code protection features of our products. Table 9-1. Debug Configurations Debug and Trace Configuration GPIO Pins Used All debug and trace disabled 0 JTAG 4 or 5 SWD 2 SWV 1 TRACEPORT 5 JTAG + TRACEPORT 9 or 10 SWD + SWV 3 SWD + TRACEPORT 7

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9.8 CSP Package Bootloader

A factory-installed bootloader program is included in all devices with CSP packages. The bootloader is compatible with PSoC Creator 3.0 bootloadable project files, and has the following features:  I2C-based  SCLK and SDAT available at P1[6] and P1[7], respectively  External pull-up resistors required  I2C slave, address 4, data rate = 100 kbps  Single application  Wait 2 seconds for bootload command  Other bootloader options are as set by the PSoC Creator 3.0 Bootloader Component default  Occupies the bottom 9 Kbytes of flash For more information on this bootloader, see the following Cypress application notes:  AN73854, PSoC 3 and PSoC 5 LP Introduction to Bootloaders  AN60317, PSoC 3 and PSoC 5 LP I2C Bootloader Note that a PSoC Creator bootloadable project must be associated with .hex and .elf files for a bootloader project that is configured for the target device. Bootloader .hex and .elf fil es can be found at www.cypress.com/go/PSoC5LPdatasheet. The factory-installed bootloader can be overwritten using JTAG or SWD programming.

Document Number: 001-84932 Rev. *N Page 66 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 10. Development Support The CY8C58LP family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit psoc.cypress.com/getting-started to find out more.

10.1 Documentation

A suite of documentation, to ensure that you can find answers to your questions quickly, supports the CY8C58LP family. This section contains a list of some of the key documents. Software User Guide : A step-by-step guide for using PSoC Creator. The software user guide shows you how the PSoC Creator build process works in detail, how to use source control with PSoC Creator, and much more. Component Datasheets : The flexibility of PSoC allows the creation of new peripherals (components) long after the device has gone into production. Component datasheets provide all of the information needed to select and use a particular component, including a functional description, API documentation, example code, and AC/DC specifications. Application Notes: PSoC application notes discuss a particular application of PSoC in depth; examples include brushless DC motor control and on-chip filtering. Application notes often include example projects in addition to the application note document. Technical Reference Manual: PSoC Creator makes designing with PSoC as easy as dragging a peripheral onto a schematic, but, when low level details of the PSoC device are required, use the technical reference manual (TRM) as your guide. Note Visit www.arm.com for detailed documentation about the Cortex-M3 CPU.

10.2 Online

In addition to print documentation, the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world, 24 hours a day, 7 days a week.

10.3 Tools

With industry standard cores, programming, and debugging interfaces, the CY8C58LP family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use PSoC Creator IDE, supported third party compilers, programmers, debuggers, and development kits.

Document Number: 001-84932 Rev. *N Page 67 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11. Electrical Specifications Specifications are valid for –40 °C ≤ TA ≤ 105 °C and TJ ≤ 120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, see the component datasheets for full AC/DC specifications of individual functions. See the Example Peripherals on page 40 for further explanation of PSoC Creator components.

11.1 Absolute Maximum Ratings

Table 11-1. Absolute Maximum Ratings DC Specifications[14] Parameter Description Conditions Min Typ Max Units VDDA Analog supply voltage relative to VSSA –0.5 – 6 V VDDD Digital supply voltage relative to VSSD –0.5 – 6 V VDDIO I/O supply voltage relative to VSSD –0.5 – 6 V VCCA Direct analog core voltage input –0.5 – 1.95 V VCCD Direct digital core voltage input –0.5 – 1.95 V VSSA Analog ground voltage V SSD – 0.5 – V SSD + 0.5 V VGPIO [15] DC input voltage on GPIO Inc ludes signals sourced by VDDA and routed internal to the pin. VSSD – 0.5 – V DDIO + 0.5 V VSIO DC input voltage on SIO Output disabled V SSD – 0.5 – 7 V Output enabled V SSD – 0.5 – 6 V VIND Voltage at boost converter input 0.5 – 5.5 V VBAT Boost converter supply V SSD – 0.5 – 5.5 V IVDDIO Current per VDDIO supply pin – – 100 mA IGPIO GPIO current –30 – 41 mA ISIO SIO current –49 – 28 mA IUSBIO USBIO current –56 – 59 mA VEXTREF ADC external reference inputs Pins P0[3], P3[2] – – 2 V LU Latch up current [16] –140 – 140 mA ESDHBM Electrostatic discharge voltage Human body model 2000 – – V ESDCDM ESD voltage Charge device model 500 – – V Notes 14. Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification. 15. The VDDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin ≤ VDDIO ≤ VDDA. 16. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test.

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11.2 Device Level Specifications

Specifications are valid for –40 °C ≤ TA ≤ 105 °C and TJ ≤ 120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Unless otherwise specified, all charts and graphs show typical values. Notes 17. The power supplies can be brought up in any sequence. However, once stable, VDDA must be greater than or equal to all other supplies. 18. The VDDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin ≤ VDDIO ≤ VDDA. 19. Guaranteed by design, not production tested. 20. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular system from the device datasheet and component datasheets. 21. Based on device characterization (Not production tested). Table 11-2. DC Specifications Parameter Description Conditions Min Typ Max Units VDDA Analog supply voltage and input to analog core regulator Analog core regulator enabled 1.8 – 5.5 V VDDA Analog supply voltage, analog regulator bypassed Analog core reg ulator disabled 1.71 1.8 1.89 V VDDD Digital supply voltage relative to VSSD Digital core regulator enabled 1.8 – V DDA [17] V–– V DDA + 0.1[19] VDDD Digital supply voltage, digital regulator bypassed Digital core regulator disabled 1.71 1.8 1.89 V VDDIO [18] I/O supply voltage relative to VSSIO 1.71 – V DDA [17] V–– V DDA + 0.1[19] VCCA Direct analog core voltage input (Analog regulator bypass) Analog core regulator disabled 1.71 1.8 1.89 V VCCD Direct digital core voltage input (Digital regulator bypass) Digital core regulator disabled 1.71 1.8 1.89 V IDD [20] Active Mode Sum of digital and analog IDDD + IDDA. IDDIOX for I/Os not included. IMO enabled, bus clock and CPU clock enabled. CPU executing complex program from flash. VDDX = 2.7 V to 5.5 V; FCPU = 3 MHz[21] T = –40 °C – 1.9 3.8 mA T = 85 °C – 2 3.8 T = 105 °C – 2 3.8 V DDX = 2.7 V to 5.5 V; FCPU = 6 MHz T = –40 °C – 3.1 5 T = 25 °C – 3.1 5 T = 85 °C – 3.2 5 T = 105 °C – 3.2 5 V DDX = 2.7 V to 5.5 V; FCPU = 12 MHz[21] T = –40 °C – 5.4 7 T = 25 °C – 5.4 7 T = 85 °C – 5.6 7 T = 105 °C – 5.6 7 VDDX = 2.7 V to 5.5 V; FCPU = 24 MHz[21] T = –40 °C – 8.9 10.5 T = 25 °C – 8.9 10.5 T = 85 °C – 9.1 10.5 T = 105 °C – 9.1 10.5 VDDX = 2.7 V to 5.5 V; FCPU = 48 MHz[21] T = –40 °C – 15.5 17 T = 25 °C – 15.4 17 T = 85 °C – 15.7 17 T = 105 °C – 15.7 17.25 V DDX = 2.7 V to 5.5 V; FCPU = 62 MHz T = –40 °C – 18 19.5 T = 25 °C – 18 19.5 T = 85 °C – 18.5 19.5 T = 105 °C – 19 21 VDDX = 2.7 V to 5.5 V; FCPU = 74 MHz T = –40 °C – 26.5 30 T = 25 °C – 26.5 30 T = 85 °C – 27 30 T = 105 °C – 27 30 VDDX = 2.7 V to 5.5 V; FCPU = 80 MHz, IMO = 3 MHz with PLL T = –40 °C – 22 25.5 T = 25 °C – 22 25.5 T = 85 °C – 22.5 25.5 T = 105 °C – 22.5 25.5

Document Number: 001-84932 Rev. *N Page 69 of 139 PSoC® 5LP: CY8C58LP Family Datasheet IDD [22] Sleep Mode [23] CPU = OFF RTC = ON (= ECO32K ON, in low-power mode) Sleep timer = ON (= ILO ON at 1 kHz)[24] WDT = OFF I2C Wake = OFF Comparator = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode V DD = VDDIO = 4.5–5.5 V T = 85 °C – 5 16 T = 105 °C – 5 16 V DD = VDDIO = 2.7–3.6 V T = 25 °C – 2 3.6 T = 85 °C – 4.2 16 T = 105 °C – 4.2 16 V DD = VDDIO = 1.71–1.95 V T = 85 °C – 4.2 16 T = 105 °C – 4.2 16 Comparator = ON CPU = OFF RTC = OFF Sleep timer = OFF WDT = OFF I 2C Wake = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode V DD = VDDIO = I2C Wake = ON CPU = OFF RTC = OFF Sleep timer = OFF WDT = OFF Comparator = OFF POR = ON Boost = OFF SIO pins in single ended input, unregulated output mode V DD = VDDIO = Table 11-2. DC Specifications (continued) Parameter Description Conditions Min Typ Max Units Notes 22. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular system from the device datasheet and component datasheets. 23. If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV. 24. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off. 25. Based on device characterization (Not production tested).

Document Number: 001-84932 Rev. *N Page 70 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-1. Active Mode Current vs FCPU, VDD = 3.3 V, Temperature = 25 °C Figure 11-2. IDD vs Frequency at 25 °C Figure 11-3. Active Mode Current vs Temperature and FCPU, VDD = 3.3 V Figure 11-4. Active Mode Current vs VDD and Temperature, FCPU = 24 MHz IDD [26] Hibernate Mode Hibernate mode current All regulators and oscillators off. SRAM retention GPIO interrupts are active Boost = OFF SIO pins in single ended input, unregulated output mode V DD = VDDIO = 4.5–5.5 V T = –40 °C – 0.2 2 µA T = 25 °C – 0.24 2 T = 85 °C – 2.6 15 T = 105 °C – 2.6 15 VDD = VDDIO = 2.7–3.6 V T = 25 °C – 0.3 2 T = 85 °C – 2 15 T = 105 °C – 2 15 V DD = VDDIO = 1.71–1.95 V T = –40 °C – 0.9 2 T = 25 °C – 0.11 2 T = 85 °C – 1.8 15 T = 105 °C – 1.8 15 I DDAR [27] Analog current consumption while device is reset V DDA ≤ 3.6 V – 0.3 0.6 mA VDDA > 3.6 V – 1.4 3.3 mA IDDDR [27] Digital current consumption while device is reset V DDD ≤ 3.6 V – 1.1 3.1 mA VDDD > 3.6 V – 0.7 3.1 mA IDD_PROG Current consumption while device programming. Sum of digital, analog, and I/Os: IDDD + IDDA + IDDIOX. –1 5 2 1 m A Table 11-2. DC Specifications (continued) Parameter Description Conditions Min Typ Max Units nt, mA 0 2 04 06 08 0 Curren CPU Frequency, MHz /g1006/g1008/g3/g68/g44/g460/g3/g374/g381/g374/g882/g104/g94/g17/g3/g373/g381/g282/g286 Notes 26. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular system from the device datasheet and component datasheets. 27. Based on device characterization (Not production tested). 0.4 0.5 0.6 0.7 A/MHz 0.1 0.2 0.3 0 2 04 06 08 0 IDD, mA Bus Clock, MHz t, mA

80 MHz

24 MHz

• 4 0 - 2 00 2 04 06 08 0 1 0 0 Curren Temperature, ° C

6 MHz

t, mA 105 ° C 25 ° C Curren VDD, V -40 ° C

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11.3 Power Regulators

Specifications are valid for –40 °C ≤ TA ≤ 105 °C and TJ ≤ 120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.

11.3.1 Digital Core Regulator

Figure 11-5. Analog and Digital Regulators, VCC vs VDD, 10 mA Load Figure 11-6. Digital Regulator PSRR vs Frequency and VDD Table 11-3. AC Specifications Parameter Description Conditions Min Typ Max Units FCPU CPU frequency 1.71 V ≤ VDDD ≤ 5.5 V DC – 80.01 MHz FBUSCLK Bus frequency 1.71 V ≤ VDDD ≤ 5.5 V DC – 80.01 MHz SVDD [28] VDD ramp rate – – 0.066 V/µs TIO_INIT [28] Time from VDDD/VDDA/VCCD/VCCA ≥ IPOR to I/O ports set to their reset states – – 10 µs TSTARTUP [28] Time from VDDD/VDDA/VCCD/VCCA ≥ PRES to CPU executing code at reset vector VCCA/VDDA = regulated from VDDA/VDDD, no PLL used, fast IMO boot mode (48 MHz typ.) – – 33 µs VCCA/VCCD = regulated from VDDA/VDDD, no PLL used, slow IMO boot mode (12 MHz typ.) – – 66 µs TSLEEP [28] Wakeup from sleep mode – Application of non-LVD interrupt to beginning of execution of next CPU instruction – – 25 µs THIBERNATE [28] Wakeup from hibernate mode – Application of external interrupt to beginning of execution of next CPU instruction – – 150 µs Note 28. Based on device characterization (Not production tested). Table 11-4. Digital Core Regulator DC Specifications Parameter Description Conditions Min Typ Max Units VDDD Input voltage 1.8 – 5.5 V VCCD Output voltage – 1.80 – V Regulator output capacitor ±10%, X5R ceramic or better. The two VCCD pins must be shorted together, with as short a trace as possible, see “Power System” section on page 26 0.9 1 1.1 µF 100 R, dB 0.1 1 10 100 1000 PSRR Frequency, kHz Vdd=4.5V Vdd=3.6V Vdd=2.7V

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11.3.2 Analog Core Regulator

Figure 11-7. Analog Regulator PSRR vs Frequency and VDD

11.3.3 Inductive Boost Regulator

Unless otherwise specified, operating conditions are: VBAT = 0.5 V–3.6 V, VOUT = 1.8 V–5.0 V, IOUT = 0 mA–50 mA, and graphs show typical values. Table 11-5. Analog Core Regulator DC Specifications Parameter Description Conditions Min Typ Max Units VDDA Input voltage 1.8 – 5.5 V VCCA Output voltage – 1.80 – V Regulator output capacitor ±10%, X5R ceramic or better 0.9 1 1.1 µF 100 R, dB 0.1 1 10 100 1000 PSRR Frequency, KHz Vdd=4.5V Vdd=3.6V Vdd=2.7V Table 11-6. Inductive Boost Regulator DC Specifications Parameter Description Conditions Min Typ Max Units VOUT Boost output voltage[29] vsel = 1.8 V in register BOOST_CR0 1.71 1.8 1.89 V vsel = 1.9 V in register BOOST_CR0 1.81 1.90 2.00 V vsel = 2.0 V in register BOOST_CR0 1.90 2.00 2.10 V vsel = 2.4 V in register BOOST_CR0 2.16 2.40 2.64 V vsel = 2.7 V in register BOOST_CR0 2.43 2.70 2.97 V vsel = 3.0 V in register BOOST_CR0 2.70 3.00 3.30 V vsel = 3.3 V in register BOOST_CR0 2.97 3.30 3.63 V vsel = 3.6 V in register BOOST_CR0 3.24 3.60 3.96 V vsel = 5.0 V in register BOOST_CR0 4.50 5.00 5.50 V VBAT Input voltage to boost[30] IOUT = 0 mA–5 mA vsel = 1.8 V–2.0 V, TA = 0 °C–70 °C 0.5 – 0.8 V IOUT = 0 mA–15 mA vsel = 1.8 V–5.0 V[31], TA = –10 °C–85 °C 1.6 – 3.6 V IOUT = 0 mA–25 mA vsel = 1.8 V–2.7 V, TA = –10 °C–85 °C 0.8 – 1.6 V IOUT = 0 mA–50 mA vsel = 1.8 V–3.3 V[31], TA = –40 °C–85 °C 1.8 – 2.5 V vsel = 1.8 V–3.3 V[31], TA = –10 °C–85 °C 1.3 – 2.5 V vsel = 2.5 V–5.0 V[31], TA = –10 °C–85 °C 2.5 – 3.6 V

Document Number: 001-84932 Rev. *N Page 73 of 139 PSoC® 5LP: CY8C58LP Family Datasheet IOUT Output current TA = 0 °C–70 °C V BAT = 0.5 V–0.8 V 0 – 5 mA TA = –10 °C–85 °C V BAT = 1.6 V–3.6 V 0 – 15 mA VBAT = 0.8 V–1.6 V 0 – 25 mA VBAT = 1.3 V–2.5 V 0 – 50 mA VBAT = 2.5 V–3.6 V 0 – 50 mA TA = –40 °C–85 °C V BAT = 1.8 V–2.5 V 0 – 50 mA ILPK Inductor peak current – – 700 mA IQ Quiescent current Boost active mode – 250 – µA Boost sleep mode, IOUT < 1 µA – 25 – µA RegLOAD Load regulation – – 10 % RegLINE Line regulation – – 10 % Table 11-6. Inductive Boost Regulator DC Specifications (continued) Parameter Description Conditions Min Typ Max Units Notes 29. Listed vsel options are characterized. Additional VSEL options are valid and guaranteed by design. 30. The boost will start at all valid VBAT conditions including down to VBAT = 0.5 V. 31. If VBAT is greater than or equal to VOUT boost setting, then VOUT will be less than VBAT due to resistive losses in the boost circuit.

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11.4 Inputs and Outputs

Specifications are valid for –40 °C ≤ TA ≤ 105 °C and TJ ≤ 120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Unless otherwise specified, all charts and graphs show typical values. When the power supplies ramp up, the pin voltages are indeterminate until both VDDIO and VDDA reach the IPOR voltage, which can be as high as 1.45 V. At that point, the pins change to their normal NVL settings.

11.4.1 GPIO

Table 11-8. GPIO DC Specifications Parameter Description Conditions Min Typ Max Units VIH Input voltage high threshold CM OS Input, PRT[x]CTL = 0 0.7 × VDDIO –– V VIL Input voltage low threshold CMO S Input, PRT[x]CTL = 0 – – 0.3 × VDDIO V VIH Input voltage high threshold LV TTL Input, PRT[x]CTL = 1, VDDIO < 2.7 V 0.7 x VDDIO –– V VIH Input voltage high threshold LVTTL Input, PRT[x]CTL = 1, VDDIO ≥ 2.7 V 2.0 – – V VIL Input voltage low threshold LVTTL Input, PRT[x]CTL = 1, V DDIO < 2.7 V – – 0.3 x VDDIO V VIL Input voltage low threshold L VTTL Input, PRT[x]CTL = 1, VDDIO ≥ 2.7 V – – 0.8 V VOH Output voltage high I OH = 4 mA at 3.3 VDDIO VDDIO – 0.6 – – V IOH = 1 mA at 1.8 VDDIO VDDIO – 0.5 – – V VOL Output voltage low I OL = 8 mA at 3.3 VDDIO –– 0 . 6 V IOL = 3 mA at 3.3 VDDIO –– 0 . 4 V IOL = 4 mA at 1.8 VDDIO –– 0 . 6 V Rpullup Pull-up resistor 3.5 5.6 8.5 k Ω Rpulldown Pull-down resistor 3.5 5.6 8.5 k Ω IIL Input leakage current (absolute value)[34] 25 °C, VDDIO = 3.0 V – – 2 nA All other GPIOs – 5 9 pF VH Input voltage hysteresis (Schmitt-Trigger)[34] –4 0 – m V Idiode Current through protection diode to VDDIO and VSSIO –– 1 0 0 µ A Rglobal Resistance pin to analog global bus 25 °C, VDDIO = 3.0 V – 320 – Ω Rmux Resistance pin to analog mux bus25 °C, VDDIO = 3.0 V – 220 – Ω Notes 34. Based on device characterization (Not production tested). 35. For information on designing with PSoC oscillators, refer to the application note, AN54439 - PSoC® 3 and PSoC 5 External Oscillator.

Document Number: 001-84932 Rev. *N Page 77 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-15. GPIO Output High Voltage and Current Figure 11-16. GPIO Output Low Voltage and Current Table 11-9. GPIO AC Specifications[36] Parameter Description Conditions Min Typ Max Units TriseF Rise time in Fast Strong Mode 3.3 V V DDIO Cload = 25 pF – – 6 ns TfallF Fall time in F ast Strong Mode 3.3 V V DDIO Cload = 25 pF – – 6 ns TriseS Rise time in Slow Strong Mode 3.3 V V DDIO Cload = 25 pF – – 60 ns TfallS Fall time in Slow Strong Mode 3.3 V V DDIO Cload = 25 pF – – 60 ns Fgpioout GPIO output operating frequency 2.7 V < VDDIO < 5.5 V, fast strong drive mode 90/10% V DDIO into 25 pF – – 33 MHz 1.71 V < VDDIO < 2.7 V, fast strong drive mode 90/10% V DDIO into 25 pF – – 20 MHz 3.3 V < VDDIO < 5.5 V, slow strong drive mode 90/10% V DDIO into 25 pF – – 7 MHz 1.71 V < VDDIO < 3.3 V, slow strong drive mode 90/10% VDDIO into 25 pF – – 3.5 MHz Fgpioin GPIO input operating frequency 90/10% V DDIO –– 3 3 M H z Note 36. Based on device characterization (Not production tested).

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11.4.2 SIO

Table 11-10. SIO DC Specifications Parameter Description Conditions Min Typ Max Units Vinmax Maximum input voltage All allowed values of Vddio and VDDD, see Absolute Maximum Ratings on page 67 –– 5 . 5 V Vinref Input voltage reference (differential input mode) 0.5 – 0.52 × VDDIO V Voutref Output voltage reference (regulated output mode) VDDIO > 3.7 1 – V DDIO – 1 V VDDIO < 3.7 1 – V DDIO – 0.5 V VIH Input voltage high threshold GPIO mode CMOS input 0.7 × VDDIO ––V Differential input mode[37] Hysteresis disabled SIO_ref + 0.2 – – V VIL Input voltage low threshold GPIO mode CMOS input – – 0.3 × VDDIO V Differential input mode[37] Hysteresis disabled – – SIO_ref – 0.2 V VOH Output voltage high Unregulated mode I OH = 4 mA, VDDIO = 3.3 V V DDIO – 0.4 – – V Regulated mode[37] IOH = 1 mA SIO_ref – 0.65 – SIO_ref + 0.2 V IOH = 0.1 mA SIO_ref – 0.3 – SIO_ref + 0.2 V no load, IOH = 0 SIO_ref – 0.1 – SIO_ref + 0.1 V VOL Output voltage low V DDIO = 3.30 V, IOL = 25 mA – – 0.8 V VDDIO = 3.30 V, IOL = 20 mA – – 0.4 V VDDIO = 1.80 V, IOL = 4 mA – – 0.4 V Rpullup Pull-up resistor 3.5 5.6 8.5 k Ω Rpulldown Pull-down resistor 3.5 5.6 8.5 k Ω IIL Input leakage current (absolute value)[38] VIH < Vddsio 25 °C, Vddsio = 3.0 V, V IH = 3.0 V – – 14 nA VIH > Vddsio 25 °C, Vddsio = 0 V, V IH = 3.0 V – – 10 µA CIN Input Capacitance[38] –– 9 p F VH Input voltage hysteresis (Schmitt-Trigger)[38] Single ended mode (GPIO mode) – 115 – mV Differential mode – 50 – mV Idiode Current through protection diode to VSSIO – – 100 µA Notes 37. See Figure 6-9 on page 35 and Figure 6-12 on page 38 for more information on SIO reference. 38. Based on device characterization (Not production tested).

Document Number: 001-84932 Rev. *N Page 80 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 11-11 SIO AC Specifications[39] Parameter Description Conditions Min Typ Max Units TriseF Rise time in fast strong mode (90/10%) Cload = 25 pF, VDDIO = 3.3 V – – 12 ns TfallF Fall time in fast strong mode (90/10%) Cload = 25 pF, VDDIO = 3.3 V – – 12 ns TriseS Rise time in slow strong mode (90/10%) Cload = 25 pF, VDDIO = 3.0 V – – 75 ns TfallS Fall time in slow strong mode (90/10%) Cload = 25 pF, VDDIO = 3.0 V – – 60 ns Fsioout SIO output operating frequency 2.7 V < VDDIO < 5.5 V, Unregu- lated output (GPIO) mode, fast strong drive mode 90/10% VDDIO into 25 pF – – 33 MHz 1.71 V < VDDIO < 2.7 V, Unregu- lated output (GPIO) mode, fast strong drive mode 90/10% V DDIO into 25 pF – – 16 MHz 3.3 V < VDDIO < 5.5 V, Unregu- lated output (GPIO) mode, slow strong drive mode 90/10% VDDIO into 25 pF – – 5 MHz 1.71 V < VDDIO < 3.3 V, Unregu- lated output (GPIO) mode, slow strong drive mode 90/10% VDDIO into 25 pF – – 4 MHz 2.7 V < VDDIO < 5.5 V, Regulated output mode, fast strong drive mode Output continuously switching into 25 pF ––2 0 M H z

1.71 V < V

DDIO < 2.7 V, Regulated output mode, fast strong drive mode Output continuously switching into 25 pF ––1 0 M H z 1.71 V < VDDIO < 5.5 V, Regulated output mode, slow strong drive mode Output continuously switching into 25 pF –– 2 . 5 M H z Fsioin SIO input operating frequency 1.71 V < VDDIO < 5.5 V 90/10% V DDIO ––3 3 M H z Note 39. Based on device characterization (Not production tested).

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11.4.3 USBIO

For operation in GPIO mode, the standard range for VDDD applies, see Device Level Specifications on page 68. Table 11-13. USBIO DC Specifications Parameter Description Conditions Min Typ Max Units Rusbi USB D+ pull-up resistance[40] With idle bus 0.900 – 1.575 k Ω Rusba USB D+ pull-up resistance [40] While receiving traffic 1.425 – 3.090 k Ω Vohusb Static output high [40] 15 kΩ ±5% to Vss, internal pull-up enabled 2.8 – 3.6 V Volusb Static output low [40] 15 kΩ ±5% to Vss, internal pull-up enabled –– 0 . 3 V Vihgpio Input voltage high, GPIO mode [40] VDDD = 1.8 V 1.5 – – V VDDD = 3.3 V 2 – – V VDDD = 5.0 V 2 – – V Vilgpio Input voltage low, GPIO mode [40] VDDD = 1.8 V – – 0.8 V VDDD = 3.3 V – – 0.8 V VDDD = 5.0 V – – 0.8 V Vohgpio Output voltage high, GPIO mode [40] IOH = 4 mA, VDDD = 1.8 V 1.6 – – V IOH = 4 mA, VDDD = 3.3 V 3.1 – – V IOH = 4 mA, VDDD = 5.0 V 4.2 – – V Volgpio Output voltage low, GPIO mode [40] IOL = 4 mA, VDDD = 1.8 V – – 0.3 V IOL = 4 mA, VDDD = 3.3 V – – 0.3 V IOL = 4 mA, VDDD = 5.0 V – – 0.3 V Vdi Differential input sensitivity |(D+)–(D–)| – – 0.2 V Vcm Differential input common mode range 0.8 – 2.5 V Vse Single ended receiver threshold 0.8 – 2 V Rps2 PS/2 pull-up resistance [40] In PS/2 mode, with PS/2 pull-up enabled 3– 7 k Ω Rext External USB series resistor [40] In series with each USB pin 21.78 (–1%) 22 22.22 (+1%) Ω Zo USB driver output impedance [40] Including Rext 28 – 44 Ω CIN USB transceiver input capacitance – – 20 pF IIL [40] Input leakage current (absolute value)[40] 25 °C, VDDD = 3.0 V – – 2 nA Note 40. Based on device characterization (Not production tested).

Document Number: 001-84932 Rev. *N Page 84 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-24. USBIO Output Low Voltage and Current, GPIO Mode

11.4.4 XRES

Table 11-15. USB Driver AC Specifications[42] Parameter Description Conditions Min Typ Max Units Tr Transition rise time – – 20 ns Tf Transition fall time – – 20 ns TR Rise/fall time matching V USB_5, VUSB_3.3, see USB DC Specifications on page 114 90% – 111% Vcrs Output signal crossover voltage 1.3 – 2 V Table 11-16. XRES DC Specifications Parameter Description Conditions Min Typ Max Units VIH Input voltage high threshold 0.7 × VDDIO –– V VIL Input voltage low threshold – – 0.3 × VDDIO V Rpullup Pull-up resistor 3.5 5.6 8.5 k Ω CIN Input capacitance[42] –3 p F VH Input voltage hysteresis (Schmitt-Trigger)[42] –1 0 0 – m V Idiode Current through protection diode to VDDIO and VSSIO – – 100 µA Table 11-17. XRES AC Specifications[42] Parameter Description Conditions Min Typ Max Units TRESET Reset pulse width 1 – – µs Note 42. Based on device characterization (Not production tested).

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11.5 Analog Peripherals

Specifications are valid for –40 °C ≤ TA ≤ 105 °C and TJ ≤ 120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.

11.5.1 Opamp

Figure 11-25. Opamp Vos Histogram, 7020 samples/1755 parts, 30 °C, VDDA = 3.3 V Figure 11-26. Opamp Vos vs Temperature, VDDA = 5 V Table 11-18. Opamp DC Specifications Parameter Description Conditions Min Typ Max Units VI Input voltage range V SSA –V DDA V Vos Input offset voltage – – 2.5 mV Operating temperature –40 °C to 70 °C –– 2 m V TCVos Input offset voltage drift with temper- ature Power mode = high – – ±30 µV / °C Ge1 Gain error, unity gai n buffer mode Rload = 1 k Ω –– ± 0 . 1 % Cin Input capacitance Routing from pin – – 18 pF Vo Output voltage range 1 mA, source or sink, power mode = high VSSA + 0.05 – V DDA – 0.05 V Iout Output current capability, source or sink V SSA + 500 mV ≤ VOUT ≤ VDDA –500 mV, VDDA > 2.7 V 25 – – mA VSSA + 500 mV ≤ VOUT ≤ VDDA –500 mV, 1.7 V = VDDA ≤ 2.7 V 16 – – mA Idd Quiescent current [43] Power mode = min – 250 400 uA Power mode = low – 250 400 uA Power mode = med – 330 950 uA Power mode = high – 1000 2500 uA CMRR Common mode rejection ratio [43] 80 – – dB PSRR Power supply rejection ratio [43] VDDA ≥ 2.7 V 85 – – dB VDDA < 2.7 V 70 – – dB IIB Input bias current[43] 25 °C – 10 – pA Note 43. Based on device characterization (Not production tested). -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 Vos, mV 0.1 0.2 mV -0.3 -0.2 -0.1 - 4 0 - 2 00 2 04 06 08 0 1 0 0 Vos, Temperature, ° C

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11.5.2 Delta-Sigma ADC

Unless otherwise specified, operating conditions are:  Operation in continuous sample mode  fclk = 3.072 MHz for resolution = 16 to 20 bits; fclk = 6.144 MHz for resolution = 8 to 15 bits  Reference = 1.024 V internal reference bypassed on P3.2 or P0.3  Unless otherwise specified, all charts and graphs show typical values Table 11-20. 20-bit Delta-sigma ADC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution 8 – 20 bits Number of channels, single ended – – No. of GPIO – Number of channels, differential Differential pair is formed using a pair of GPIOs. –– No. of GPIO/2 – Monotonic Yes – – – – Ge Gain error Buffered, buffer gain = 1, Range = Gd Gain drift Buffered, buffer gain = 1, Range = ±1.024 V, 16-bit mode –– 5 0 ppm/° C Vos Input offset voltage Buffered, 16-bit mode, full voltage range –– ± 0 . 2 m V Buffered, 16-bit mode, TCVos Temperature coefficient, input offset voltage Buffer gain = 1, 16-bit, Range = ±1.024 V –– 1 µ V / ° C Input voltage range, single ended[45] VSSA –V DDA V Input voltage range, differential unbuf- fered[45] VSSA –V DDA V Input voltage range, differential, buffered[45] VSSA –V DDA – 1 V PSRRb Power supply rejection ratio, buffered[45] Buffer gain = 1, 16-bit, Range = ±1.024 V 90 – – dB CMRRb Common mode rejection ratio, buffered[45] Buffer gain = 1, 16 bit, Range = ±1.024 V 85 – – dB TA ≤ 105 °C 80 – – INL20 Integral non linearity[45] Range = ±1.024 V, unbuffered – – ±32 LSB DNL20 Differential non linearity[45] Range = ±1.024 V, unbuffered – – ±1 LSB INL16 Integral non linearity[45] Range = ±1.024 V, unbuffered – – ±2 LSB DNL16 Differential non linearity[45] Range = ±1.024 V, unbuffered – – ±1 LSB INL12 Integral non linearity[45] Range = ±1.024 V, unbuffered – – ±1 LSB DNL12 Differential non linearity[45] Range = ±1.024 V, unbuffered – – ±1 LSB INL8 Integral non linearity[45] Range = ±1.024 V, unbuffered – – ±1 LSB DNL8 Differential non linearity[45] Range = ±1.024 V, unbuffered – – ±1 LSB Note 45. Based on device characterization (not production tested).

Document Number: 001-84932 Rev. *N Page 89 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Rin_Buff ADC input resistance Input buffer used 10 – – M Ω Rin_ADC16 ADC input resistance Input buffer bypassed, 16-bit, Range = ±1.024 V –7 4 [46] –k Ω Rin_ADC12 ADC input resistance Input buffer bypassed, 12 bit, Range = ±1.024 V –1 4 8 [46] –k Ω Rin_ExtRef ADC external ref erence input resistance – 70 [46, 47] –k Ω Vextref ADC external reference input voltage, see also internal reference in Voltage Reference on page 93 Current Consumption IDD_20 IDDA + IDDD Current consumption, 20 bit[48] 187 sps, unbuffered – – 1.5 mA IDD_16 IDDA + IDDD Current consumption, 16 bit[48] 48 ksps, unbuffered – – 1.5 mA IDD_12 IDDA + IDDD Current consumption, 12 bit[48] 192 ksps, unbuffered – – 1.95 mA IDD_8 IDDA + IDDD Current consumption, 8 bit[48] 384 ksps, unbuffered – – 1.95 mA IBUFF Buffer current consumption[48] ––2 . 5 m A Table 11-20. 20-bit Delta-sigma ADC DC Specifications (continued) Parameter Description Conditions Min Typ Max Units Table 11-21. Delta-sigma ADC AC Specifications Parameter Description Conditions Min Typ Max Units Startup time – – 4 Samples THD Total harmonic distortion[48] Buffer gain = 1, 16 bit, Range = ±1.024 V – – 0.0032 % 20-Bit Resolution Mode SR20 Sample rate[48] Range = ±1.024 V, unbuffered 7.8 – 187 sps BW20 Input bandwidth at max sample rate[48] Range = ±1.024 V, unbuffered – 40 – Hz 16-Bit Resolution Mode SR16 Sample rate[48] Range = ±1.024 V, unbuffered 2 – 48 ksps BW16 Input bandwidth at max sample rate[48] Range = ±1.024 V, unbuffered – 11 – kHz SINAD16int Signal to noise ratio, 16-bit, internal reference [48] Range = ±1.024V, unbuffered 81 – – dB TA ≤ 105 °C 77 – – SINAD16ext Signal to noise ratio, 16-bit, external reference[48] Range = ±1.024 V, unbuffered 84 – – dB 12-Bit Resolution Mode SR12 Sample rate, continuous, high power[48] Range = ±1.024 V, unbuffered 4 – 192 ksps BW12 Input bandwidth at max sample rate[48] Range = ±1.024 V, unbuffered – 44 – kHz SINAD12int Signal to noise ratio, 12-bit, internal reference [48] Range = ±1.024 V, unbuffered 66 – – dB 8-Bit Resolution Mode SR8 Sample rate, continuous, high power[48] Range = ±1.024 V, unbuffered 8 – 384 ksps BW8 Input bandwidth at max sample rate[48] Range = ±1.024 V, unbuffered – 88 – kHz SINAD8int Signal to noise ratio, 8-bit, internal reference[48] Range = ±1.024 V, unbuffered 43 – – dB Notes 46. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual. 47. Recommend an external reference device with an output impedance <100 Ω, for example, the LM185/285/385 family. A 1 µF capacitor is recommended. For more information, see AN61290 - PSoC® 3 and PSoC 5LP Hardware Design Considerations. 48. Based on device characterization (not production tested).

Document Number: 001-84932 Rev. *N Page 91 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 11-23. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 16-bit, Internal Reference, Single Ended Sample Rate SPS Input Voltage Range 0 to VREF 0 to 2xVREF 0 to VDDA 0 to 6xVREF 2000 1.52 0.80 1.57 1.38 3000 1.63 0.87 1.64 1.43 6000 1.59 0.88 1.65 1.42 12000 1.59 0.85 1.62 1.40 24000 1.60 0.84 1.60 1.39 48000 1.57 0.83 1.57 1.36 Table 11-24. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 16-bit, Internal Reference, Differential Sample Rate SPS Input Voltage Range ± VREF ± VREF/2 ± VREF/4 ± VREF/8 ± VREF/16 32000 0.84 1.05 43750 0.83 1.06 48000 0.82 Table 11-25. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 20-bit, External Reference, Single Ended Sample Rate Input Voltage Range VSSA_to_VREF VSSA_to_2*VREF VSSA_to_VDDA VSSA_to_6*VREF 8 1.53 1.00 1.63 1.62 23 1.84 0.99 2.14 1.52 45 1.82 0.96 1.91 1.57 90 1.83 0.99 1.98 1.76 187 1.87 0.98 1.92 1.61

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11.5.3 Voltage Reference

Figure 11-39. Vref vs Temperature Figure 11-40. Vref Long-term D rift Table 11-27. Voltage Reference Specifications See ADC external reference specifications in Delta-Sigma ADC on page 88. Parameter Description Conditions Min Typ Max Units VREF [50] Precision reference voltage In itial trimming, 25 °C 1.023 (–0.1%) 1.024 1.025 (+0.1%) V After typical PCB assembly, post reflow Typical (non-optimized) board layout and 250 °C solder reflow. Device may be calibrated after assembly to improve performance. –40 °C – ±0.5 – % 25 °C – ±0.2 – % 85 °C – ±0.2 – % 105 °C – ±0.3 – % Temperature drift Long term drift[51] – 100 – ppm/Khr Thermal cycling drift (stability)[51] – 100 – ppm 1024 1024.5 1025 mV 1023 1023.5 1024 -40 -20 0 20 40 60 80 100 Vref, m Temperature, ° C 1.95V 1.8V 1.71V Notes 50. VREF is measured after packaging, and thus accounts for substrate and die attach stresses. 51. Based on device characterization (Not production tested).

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11.5.4 SAR ADC

Table 11-28. SAR ADC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution – – 12 bits Number of channels – single-ended – – No of GPIO Number of channels – differential Differential pair is formed us ing a pair of neighboring GPIO. – – No of GPIO/2 Monotonicity[52] Yes – – Ge Gain error [53] External reference – – ±0.1 % VOS Input offset voltage – – ±2 mV IDD Current consumption[52] ––1 m A Input voltage range – single-ended[52] VSSA –V DDA V Input voltage range – differential[52] V SSA –V DDA V PSRR Power supply rejection ratio [52] 70 – – dB CMRR Common mode rejection ratio 70 – – dB INL Integral non linearity [52] VDDA 1.71 to 5.5 V, 1 Msps, VREF 1 to 5.5 V, bypassed at ExtRef pin VDDA 2.0 to 3.6 V, 1 Msps, VREF 2 to VDDA, bypassed at ExtRef pin –– ± 1 . 2 L S B VDDA 1.71 to 5.5 V, 500 ksps, VREF 1 to 5.5 V, bypassed at ExtRef pin –– ± 1 . 3 L S B DNL Differential non linearity [52] VDDA 1.71 to 5.5 V, 1 Msps, VREF 1 to 5.5 V, bypassed at ExtRef pin –– + 2 / – 1 L S B VDDA 2.0 to 3.6 V, 1 Msps, VREF 2 to VDDA, bypassed at ExtRef pin No missing codes – – 1.7/–0.99 LSB VDDA 1.71 to 5.5 V, 500 ksps, VREF 1 to 5.5 V, bypassed at ExtRef pin No missing codes – – +2/–0.99 LSB RIN Input resistance[52] –1 8 0– k Ω Notes 52. Based on device characterization (Not production tested). 53. For total analog system Idd < 5 mA, depending on package used. With higher total analog system currents it is recommended that the SAR ADC be used in differential mode.

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11.5.5 Analog Globals

Table 11-30. Analog Globals DC Specifications Parameter Description Conditions Min Typ Max Units Rppag Resistance pin-to-pin through P2[4], AGL0, DSM INP , AGL1, P2[5][55, 57] VDDA = 3.0 V – 1500 2200 Ω VDDA = 1.71 V – 1200 1700 Ω Rppmuxbus Resistance pin-to-pin through P2[3], amuxbusL, P2[4][55, 57] VDDA = 3.0 V – 700 1100 Ω VDDA = 1.71 V – 600 900 Ω Table 11-31. Analog Globals AC Specifications Parameter Description Conditions Min Typ Max Units Inter-pair crosstalk for analog routes[56] 1 0 6 ––d B BWag Analog globals 3 db bandwidth [56] VDDA = 3.0 V, 25 °C – 26 – MHz Notes 55. Based on device characterization (Not production tested). 56. Pin P6[4] to del-sig ADC input; calculated, not measured. 57. The resistance of the analog global and analog mux bus is high if VDDA ≤ 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog mux bus under these conditions is not recommended.

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11.5.6 Comparator

Table 11-32. Comparator DC Specifications[58] Parameter Description Conditions Min Typ Max Units VOS Input offset voltage in fast mode Factory trim, Vdda > 2.7 V, Vin ≥ 0.5 V –1 0 m V Input offset voltage in slow mode Factory trim, Vin ≥ 0.5 V – 9 mV VOS Input offset voltage in fast mode[59] Custom trim – – 4 mV Input offset voltage in slow mode[59] Custom trim – – 4 mV VOS Input offset voltage in ultra low power mode –± 1 2 – m V TCVos Temperature coefficient, input offset voltage VCM = VDDA / 2, fast mode – 63 85 µV/°C VCM = VDDA / 2, slow mode – 15 20 VHYST Hysteresis Hysteresis enable mode – 10 32 mV VICM Input common mode voltage High current / fast mode V SSA –V DDA V Low current / slow mode V SSA –V DDA V Ultra low power mode V SSA –V DDA – 1.15 V CMRR Common mode rejection ratio – 50 – dB I CMP High current mode/fast mode – – 400 µA Low current mode/slow mode – – 100 µA Ultra low power mode – 6 – µA Table 11-33. Comparator AC Specifications[58] Parameter Description Conditions Min Typ Max Units TRESP Response time, high current mode[59] 50 mV overdrive, measured pin-to-pin – 75 110 ns Response time, low current mode [59] 50 mV overdrive, measured pin-to-pin – 155 200 ns Response time, ultra low power mode [59] 50 mV overdrive, measured pin-to-pin –5 5 – µ s Notes 58. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM. 59. Based on device characterization (Not production tested).

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11.5.7 Current Digital-to-analog Converter (IDAC)

All specifications are based on use of the low-resistance IDAC output pins (see Pin Descriptions on page 12 for details). See the IDAC component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-34. IDAC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution – – 8 bits IOUT Output current at code = 255 Range = 2.04 mA, code = 255, VDDA ≥ 2.7 V, Rload = 600 Ω –2 . 0 4 – m A Range = 2.04 mA, High mode, code = 255, VDDA ≤ 2.7 V, Rload = 300 Ω –2 . 0 4 – m A Range = 255 µA, code = 255, Rload = 600 Ω –2 5 5 – µ A Range = 31.875 µA, code = 255, Rload = 600 Ω – 31.875 – µA Monotonicity – – Yes Ezs Zero scale error – 0 ±1 LSB Eg Gain error Range = 2.04 mA – – ±2.5 % Range = 255 µA – – ±2.5 % Range = 31.875 µA – – ±3.5 % TC_Eg Temperature coefficient of gain error Range = 2.04 mA – – 0.045 % / °C Range = 255 µA – – 0.045 % / °C Range = 31.875 µA – – 0.05 % / °C INL Integral nonlinearity Sink mode, range = 255 µA, Codes 8–255, Rload = 2.4 kΩ, Cload = 15 pF –± 0 . 9± 1 L S B Source mode, range = 255 µA, Codes 8–255, Rload = 2.4 kΩ, Cload = 15 pF –± 1 . 2 ± 1 . 6 L S B Source mode, range = 31.875 µA, Codes 8–255, Rload = 20 kΩ, Cload = 15 pF [60] –± 0 . 9± 2 L S B Sink mode, range = 31.875 µA, Codes 8–255, Rload = 20 kΩ, Cload = 15 pF[60] –± 0 . 9± 2 L S B Source mode, range = 2.04 mA, Codes 8–255, Rload = 600 Ω, Cload = 15 pF[60] –± 0 . 9± 2 L S B Sink mode, range = 2.04 mA, Codes 8–255, Rload = 600 Ω, Cload = 15 pF [60] –± 0 . 6± 1 L S B Notes 60. Based on device characterization (Not production tested).

Document Number: 001-84932 Rev. *N Page 100 of 139 PSoC® 5LP: CY8C58LP Family Datasheet DNL Differential nonlinearity Sink mode, range = 255 µA, Rload = 2.4 kΩ, Cload = 15 pF –± 0 . 3± 1 L S B Source mode, range = 255 µA, Rload = 2.4 kΩ, Cload = 15 pF –± 0 . 3± 1 L S B Source mode, range = 31.875 µA, Rload = 20 kΩ, Cload = 15 pF[61] –± 0 . 2± 1 L S B Sink mode, range = 31.875 µA, Rload = 20 kΩ, Cload = 15 pF[61] –± 0 . 2± 1 L S B Source mode, range = 2.0 4 mA, Rload = 600 Ω, Cload = 15 pF[61] –± 0 . 2± 1 L S B Sink mode, range = 2.0 4 mA, Rload = 600 Ω, Cload = 15 pF[61] –± 0 . 2± 1 L S B Vcompliance Dropout voltage, source or sink mode Voltage headroom at max current, Rload to VDDA or Rload to VSSA, VDIFF from VDDA 1– – V IDD Operating current, code = 0 Slow mode, source mode, range = 31.875 µA – 44 100 µA Slow mode, source mode, range = 255 µA, – 33 100 µA Slow mode, source mode, range = 2.04 mA – 33 100 µA Slow mode, sink mode, range = 31.875 µA – 36 100 µA Slow mode, sink mode, range = 255 µA – 33 100 µA Slow mode, sink mode, range = 2.04 mA – 33 100 µA Fast mode, source mode, range = 31.875 µA – 310 500 µA Fast mode, source mode, range = 255 µA – 305 500 µA Fast mode, source mode, range = 2.04 mA – 305 500 µA Fast mode, sink mode, range = 31.875 µA – 310 500 µA Fast mode, sink mode, range = 255 µA – 300 500 µA Fast mode, sink mode, range = 2.04 mA – 300 500 µA Table 11-34. IDAC DC Specifications (continued) Parameter Description Conditions Min Typ Max Units Note 61. Based on device characterization (Not production tested).

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11.5.8 Voltage Digital to Analog Converter (VDAC)

See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Figure 11-61. VDAC INL vs Input Code, 1 V Mode Figure 11-62. VDA C DNL vs Input Code, 1 V Mode Table 11-36. VDAC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution – 8 – bits INL1 Integral nonlinearity 1 V scale – ±2.1 ±2.5 LSB INL4 Integral nonlinearity [63] 4 V scale – ±2.1 ±2.5 LSB DNL1 Differential nonlinearity 1 V scale – ±0.3 ±1 LSB DNL4 Differential nonlinearity [63] 4 V scale – ±0.3 ±1 LSB Rout Output resistance 1 V scale – 4 – k Ω

4 V scale – 16 – k Ω

VOUT Output voltage range, code = 255 1 V scale – 1.02 – V 4 V scale, Vdda = 5 V – 4.08 – V Monotonicity – – Yes – VOS Zero scale error – 0 ±0.9 LSB Eg Gain error 1 V scale – – ±2.5 % 4 V scale – – ±2.5 % TC_Eg Temperature coefficient, gain error 1 V scale – – 0.03 %FSR / ° C 4 V scale – – 0.03 %FSR / °C IDD Operating current[63] Slow mode – – 100 µA Fast mode – – 500 µA 0.5 LSB -0.5 0 32 64 96 128 160 192 224 256 INL, L Code, 8-bit 0.25 0.5 LSB -0.5 -0.25 0 32 64 96 128 160 192 224 256 DNL, Code, 8-bit Note 63. Based on device characterization (Not production tested).

Document Number: 001-84932 Rev. *N Page 106 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-69. VDAC Step Response, Codes 0x40 - 0xC0, 1 V Mode, Fast Mode, Vdda = 5 V Figure 11-70. VDAC Glitch Response, Codes 0x7F - 0x80, 1 V Mode, Fast Mode, Vdda = 5 V Figure 11-71. VDAC PSRR vs Frequency Figure 11-72. VDAC Voltage Noise, 1 V Mode, Fast Mode, Vdda = 5 V Table 11-37. VDAC AC Specifications[64] Parameter Description Conditions Min Typ Max Units FDAC Update rate 1 V scale – – 1000 ksps

4 V scale – – 250 ksps

TsettleP Settling time to 0.1%, step 25% to 75% 1 V scale, Cload = 15 pF – 0.45 1 µs 4 V scale, Cload = 15 pF – 0.8 3.2 µs TsettleN Settling time to 0.1%, step 75% to 25% 1 V scale, Cload = 15 pF – 0.45 1 µs 4 V scale, Cload = 15 pF – 0.7 3 µs Voltage noise Range = 1 V, fast mode, Vdda = 5V , 1 0k H z –7 5 0 – n V / s q r t H z 0.75 t, V 0.25 0.5 00 . 511 . 52 Vout Time, μs 0.52 0.54t, V 0.48 0.5 0 0.5 1 1.5 2 Vout Time, μs PSRR, dB 0.1 1 10 100 1000 P Frequency, kHz

4 V, code 0x7F 4 V, code 0xFF

0.01 0.1 1 10 100 nV/sq Frequency, kHz Note 64. Based on device characterization (Not production tested).

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11.5.9 Mixer

The mixer is created using a SC/CT analog block; see the Mixer component datasheet in PSoC Creator for full electrical specifications and APIs.

11.5.10 Transimpedance Amplifier

The TIA is created using a SC/CT analog block; see the TIA comp onent datasheet in PSoC Creator for full electrical specificati ons and APIs. Table 11-38. Mixer DC Specifications Parameter Description Conditions Min Typ Max Units VOS Input offset voltage High power mode, V IN = 1.024 V, VREF = 1.024 V ––1 5 m V Quiescent current – 0.9 2 mA G Gain – 0 – dB Table 11-39. Mixer AC Specifications[65] Parameter Description Conditions Min Typ Max Units fLO Local oscillator frequency Down mixer mode – – 4 MHz fin Input signal frequency Down mixer mode – – 14 MHz fLO Local oscillator frequency Up mixer mode – – 1 MHz fin Input signal frequency Up mixer mode – – 1 MHz SR Slew rate 3 – – V/µs Table 11-40. Transimpedance Amplifier (TIA) DC Specifications Parameter Description Conditions Min Typ Max Units VIOFF Input offset voltage – – 10 mV Rconv Conversion resistance [66] R = 20K; 40 pF load –25 – +35 % R = 30K; 40 pF load –25 – +35 % R = 40K; 40 pF load –25 – +35 % R = 80K; 40 pF load –25 – +35 % R = 120K; 40 pF load –25 – +35 % R = 250K; 40 pF load –25 – +35 % R= 500K; 40 pF load –25 – +35 % R = 1M; 40 pF load –25 – +35 % Quiescent current [65] –1 . 1 2 m A Table 11-41. Transimpedance Amplifier (TIA) AC Specifications[65] Parameter Description Conditions Min Typ Max Units BW Input bandwidth (–3 dB) R = 20K; –40 pF load 1200 – – kHz R = 120K; –40 pF load 240 – – kHz R = 1M; –40 pF load 25 – – kHz Notes 65. Based on device characterization (Not production tested). 66. Conversion resistance values are not calibrated. Calibrated values and details about calibration are provided in PSoC Creator component datasheets. External precision resistors can also be used.

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11.5.11 Programmable Gain Amplifier

The PGA is created using a SC/CT analog block; see the PGA component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, operating conditions are:  Operating temperature = 25 °C for typical values  Unless otherwise specified, all charts and graphs show typical values. Figure 11-73. PGA Voffset Histogram, 4096 samples/ 1024 parts Table 11-42. PGA DC Specifications Parameter Description Conditions Min Typ Max Units Vin Input voltage range Power mode = minimum Vssa – Vdda V Vos Input offset voltage Power mode = high, gain = 1 –– 1 0 m V TCVos Input offset voltage drift with temperature Power mode = high, gain = 1 –– ± 3 0 µ V /°C Ge1 Gain error, gain = 1 – – ±0.15 % Ge16 Gain error, gain = 16 – – ±2.5 % Ge50 Gain error, gain = 50 – – ±5 % Vonl DC output nonlinearity Gain = 1 – – ±0.01 % of FSR Cin Input capacitance – – 7 pF Voh Output voltage swing Power mode = high, gain = 1, Rload = 100 kΩ to V DDA / 2 VDDA – 0.15 – – V Vol Output voltage swing Power mode = high, gain = 1, Rload = 100 kΩ to VDDA / 2 –– V SSA + 0.15 V Vsrc Output voltage under load Iload = 250 µA, Vdda ≥ 2.7V, power mode = high –– 3 0 0 m V Idd Operating current [67] Power mode = high – 1.5 1.65 mA PSRR Power supply rejection ratio 48 – – dB Note 67. Based on device characterization (Not production tested).

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11.5.12 Temperature Sensor

11.5.13 LCD Direct Drive

Table 11-44. Temperature Sensor Specifications Parameter Description Conditions Min Typ Max Units Temp sensor accuracy Range: –40 °C to +105 °C – ±5 – °C Table 11-45. LCD Direct Drive DC Specifications[69] Parameter Description Conditions Min Typ Max Units ICC LCD Block (no glass) Device sleep mode with wakeup at 400Hz rate to refresh LCD, bus, clock = 3MHz, Vddio = Vdda = 3V, 8 commons, 16 segments, 1/5 duty cycle, 40 Hz frame rate, no glass connected –8 1– μA I CC_SEG Current per segment driver Strong drive mode – 260 – µA VBIAS LCD bias range (VBIAS refers to the main output voltage(V0) of LCD DAC) VDDA ≥ 3 V and VDDA ≥ VBIAS 2–5 V LCD bias step size V DDA ≥ 3 V and VDDA ≥ VBIAS – 9.1 × V DDA –m V LCD capacitance per segment/ common driver Drivers may be combined – 500 5000 pF Maximum segment DC offset V DDA ≥ 3 V and VDDA ≥ VBIAS –– 2 0 m V IOUT Output drive current per segment driver) VDDIO = 5.5 V, strong drive mode 355 – 710 µA Table 11-46. LCD Direct Drive AC Specifications[69] Parameter Description Conditions Min Typ Max Units fLCD LCD frame rate 10 50 150 Hz Note 69. Based on device characterization (Not production tested).

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11.6 Digital Peripherals

Specifications are valid for –40 °C ≤ TA ≤ 105 °C and TJ ≤ 120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.

11.6.1 Timer

The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for more information, see the Timer component datasheet in PSoC Creator. Table 11-47. Timer DC Specifications[70] Parameter Description Conditions Min Typ Max Units Block current consumption 16-bit timer, at listed input clock frequency –– – µ A

3 MHz – 15 – µA

12 MHz – 60 – µA

48 MHz – 260 – µA

80 MHz – 360 – µA

Table 11-48. Timer AC Specifications [70] Parameter Description Conditions Min Typ Max Units Operating frequency DC – 80.01 MHz Capture pulse width (Internal) [71] 15 – – ns Capture pulse width (external) 30 – – ns Timer resolution[71] 15 – – ns Enable pulse width[71] 15 – – ns Enable pulse width (external) 30 – – ns Reset pulse width[71] 15 – – ns Reset pulse width (external) 30 – – ns Notes 70. Based on device characterization (Not production tested). 71. For correct operation, the minimum Timer/Counter/PWM input pulse width is the period of bus clock.

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11.6.2 Counter

The following specifications app ly to the Timer/Counter/PWM per ipheral, in counter mode. Count ers can also be implemented in UDBs; for more information, see the Counter component datasheet in PSoC Creator. Table 11-49. Counter DC Specifications[72] Parameter Description Conditions Min Typ Max Units Block current consumption 16-bit counter, at listed input clock frequency –– – µ A Table 11-50. Counter AC Specifications[72] Parameter Description Conditions Min Typ Max Units Operating frequency DC – 80.01 MHz Capture pulse[73] 15 – – ns Resolution[73] 15 – – ns Pulse width[73] 15 – – ns Pulse width (external) 30 ns Enable pulse width[73] 15 – – ns Enable pulse width (external) 30 – – ns Reset pulse width[73] 15 – – ns Reset pulse width (external) 30 – – ns Notes 72. Based on device characterization (Not production tested). 73. For correct operation, the minimum Timer/Counter/PWM input pulse width is the period of bus clock.

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11.6.3 Pulse Width Modulation

The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented in UDBs; for more information, see the PWM component datasheet in PSoC Creator.

11.6.4 I2C

11.6.5 Controller Area Network

Table 11-51. PWM DC Specifications[74] Parameter Description Conditions Min Typ Max Units Block current consumption 16-bit PWM, at listed input clock frequency – – – µA

3 MHz –1 5– µ A

12 MHz –6 0– µ A

48 MHz –2 6 0– µ A

80 MHz –3 6 0– µ A

Table 11-52. PWM AC Specifications[74] Parameter Description Conditions Min Typ Max Units Operating frequency DC – 80.01 MHz Pulse width [75] 15 – – ns Pulse width (external) 30 – – ns Kill pulse width[75] 15 – – ns Kill pulse width (external) 30 – – ns Enable pulse width[75] 15 – – ns Enable pulse width (external) 30 – – ns Reset pulse width [75] 15 – – ns Reset pulse width (external) 30 – – ns Table 11-53. Fixed I2C DC Specifications[74] Parameter Description Conditions Min Typ Max Units Block current consumption Enable d, configured for 100 kbps – – 250 µ A Enabled, configured for 400 kbps – – 260 µA Table 11-54. Fixed I2C AC Specifications[76] Parameter Description Conditions Min Typ Max Units Bit rate – – 1 Mbps Table 11-55. CAN DC Specifications[74, 77] Parameter Description Conditions Min Typ Max Units IDD Block current consumption – – 200 µA Table 11-56. CAN AC Specifications[74, 77] Parameter Description Conditions Min Typ Max Units Bit rate Minimum 8 MHz clock – – 1 Mbit Notes 74. Based on device characterization (Not production tested). 75. For correct operation, the minimum Timer/Counter/PWM input pulse width is the period of bus clock. 76. Rise/fall time matching (TR) not guaranteed, see Table 11-15 on page 84. 77. Refer to ISO 11898 specification for details.

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11.6.6 Digital Filter Block

11.6.7 USB

Table 11-57. DFB DC Specifications[78] Parameter Description Conditions Min Typ Max Units DFB operating current 64-tap FIR at F DFB 500 kHz (6.7 ksps) – 0.16 0.27 mA 1 MHz (13.4 ksps) – 0.33 0.53 mA 10 MHz (134 ksps) – 3.3 5.3 mA 48 MHz (644 ksps) – 15.7 25.5 mA 80 MHz (1.07 Msps) – 26.0 42.5 mA Table 11-58. DFB AC Specifications[78] Parameter Description Conditions Min Typ Max Units FDFB DFB operating frequency DC – 80.01 MHz Table 11-59. USB DC Specifications Parameter Description Conditions Min Typ Max Units VUSB_5 Device supply (VDDD) for USB operation USB configured, USB regulator enabled 4.35 – 5.25 V VUSB_3.3 USB configured, USB regulator bypassed 3.15 – 3.6 V VUSB_3 USB configured, USB regulator bypassed[78] 2.85 – 3.6 V IUSB_Configured Device supply current in device active mode, bus clock and IMO = 24 MHz VDDD = 5 V, FCPU = 1.5 MHz – 10 – mA VDDD = 3.3 V, FCPU = 1.5 MHz – 8 – mA IUSB_Suspended Device supply current in device sleep mode VDDD = 5 V, connected to USB host, PICU configured to wake on USB resume signal –0 . 5–m A VDDD = 5 V, disconnected from USB host –0 . 3–m A VDDD = 3.3 V, connected to USB host, PICU configured to wake on USB resume signal –0 . 5–m A VDDD = 3.3 V, disconnected from USB host –0 . 3–m A Note 78. Rise/fall time matching (TR) not guaranteed, see Table 11-15 on page 84.

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11.6.8 Universal Digital Blocks (UDBs)

PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications, APIs, and example code. Figure 11-76. Clock to Output Performance Table 11-60. UDB AC Specifications[79] Parameter Description Conditions Min Typ Max Units Datapath Performance FMAX_TIMER Maximum frequency of 16-bit timer in a UDB pair – – 67.01 MHz FMAX_ADDER Maximum frequency of 16-bit adder in a UDB pair – – 67.01 MHz FMAX_CRC Maximum frequency of 16-bit CRC/PRS in a UDB pair – – 67.01 MHz PLD Performance FMAX_PLD Maximum frequency of a two-pass PLD function in a UDB pair – – 67.01 MHz Clock to Output Performance tCLK_OUT Propagation delay for clock in to data out, see Figure 11-76. 25 °C, VDDD ≥ 2.7 V – 20 25 ns tCLK_OUT Propagation delay for clock in to data out, see Figure 11-76. Worst-case placement, routing, and pin selection – – 55 ns Note 79. Based on device characterization (Not production tested).

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11.7 Memory

Specifications are valid for –40 °C ≤ TA ≤ 105 °C and TJ ≤ 120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.

11.7.1 Flash

11.7.2 EEPROM

Table 11-61. Flash DC Specifications Parameter Description Conditions Min Typ Max Units Erase and program voltage V DDD pin 1.71 – 5.5 V Table 11-62. Flash AC Specifications Parameter Description Conditions Min Typ Max Units TWRITE Row write time (erase + program) – 15 20 ms TERASE Row erase time – 10 13 ms Row program time – 5 7 ms TBULK Bulk erase time (256 KB) – – 140 ms Sector erase time (16 KB) – – 15 ms TPROG Total device programming time No overhead [80] – 5 7.5 seconds Flash data retention time, retention period measured from last erase cycle Ambient temp. TA ≤ 55 °C,

100 K erase/program cycles

20 – – years Ambient temp. TA ≤ 85 °C,

10 K erase/program cycles

10 – – Ambient temp. TA ≤ 105 °C,

10 K erase/program cycles,

≤ one year at T A ≥ 75 °C [80] 10 – – Table 11-63. EEPROM DC Specifications Parameter Description Conditions Min Typ Max Units Erase and program voltage 1.71 – 5.5 V Table 11-64. EEPROM AC Specifications Parameter Description Conditions Min Typ Max Units TWRITE Single row erase/write cycle time – 10 20 ms EEPROM data retention time, retention period measured from last erase cycle Ambient temp, TA ≤ 25 °C, 1M erase/program cycles 20 – – years Ambient temp, TA ≤ 55 °C, 100K erase/program cycles 20 – – Ambient temp. TA ≤ 85 °C, 10K erase/program cycles 10 – – Ambient temp. TA ≤ 105 °C, 10K erase/program cycles, ≤ one year at T A ≥75 °C 10 – – Note 80. See PSoC 5 Device Programming Specifications for a description of a low-overhead method of programming PSoC 5 flash.

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11.7.3 Nonvolatile Latches (NVL)

11.7.4 SRAM

Table 11-65. NVL DC Specifications Parameter Description Conditions Min Typ Max Units Erase and program voltage V DDD pin 1.71 – 5.5 V Table 11-66. NVL AC Specifications Parameter Description Conditions Min Typ Max Units NVL endurance Programmed at 25 °C 1K – – program/ erase cycles Programmed at 0 °C to 70 °C 100 – – program/ erase cycles NVL data retention time Ambient temp. T A ≤ 55 °C 20 – – years Ambient temp. TA ≤ 85 °C 10 – – Ambient temp. TA ≤ 105 °C, ≤ one year at TA ≥ 75 °C [81] 10 – – Table 11-67. SRAM DC Specifications Parameter Description Conditions Min Typ Max Units VSRAM SRAM retention voltage[82] 1.2 – – V Table 11-68. SRAM AC Specifications Parameter Description Conditions Min Typ Max Units FSRAM SRAM operating frequency DC – 80.01 MHz Notes 81. Cypress provides a retention calculator to calculate the retention lifetime based on customers' individual temperature profiles for operation over the –40 °C to +105 °C ambient temperature range. Contact customercare@cypress.com. 82. Based on device characterization (Not production tested).

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11.7.5 External Memory Interface

Figure 11-77. Asynchronous Write and Read Cycle Timing, No Wait States Tbus_clock Bus Clock EM_Addr EM_CE EM_WE EM_OE EM_Data Write Cycle Read Cycle Minimum of 4 bus clock cycles between successive EMIF accesses Trd_setup Trd_hold Twr_setup Table 11-69. Asynchronous Write and Read Timing Specifications[83] Parameter Description Conditions Min Typ Max Units Fbus_clock Bus clock frequency [84] –– 3 3 M H z Tbus_clock Bus clock period [85] 30.3 – – ns Twr_Setup Time from EM_dat a valid to rising edge of EM_WE and EM_CE Tbus_clock – 10 – – ns Trd_setup Time that EM_data must be valid before rising edge of EM_OE 5– – n s Trd_hold Time that EM_data must be valid after rising edge of EM_OE 5– – n s Notes 83. Based on device characterization (Not production tested). 84. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 76. 85. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency.

Document Number: 001-84932 Rev. *N Page 119 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-78. Synchronous Write and Read Cycle Timing, No Wait States Tbus_clock Bus Clock EM_Addr EM_CE EM_ADSC EM_Clock EM_WE EM_OE EM_Data Trd_setup Trd_hold Write Cycle Read Cycle Minimum of 4 bus clock cycles between successive EMIF accesses Twr_setup Table 11-70. Synchronous Write and Read Timing Specifications[86] Parameter Description Conditions Min Typ Max Units Fbus_clock Bus clock frequency [87] –– 3 3 M H z Tbus_clock Bus clock period [88] 30.3 – – ns Twr_Setup Time from EM_dat a valid to rising edge of EM_Clock Tbus_clock – 10 – – ns Trd_setup Time that EM_data must be valid before rising edge of EM_OE 5– – n s Trd_hold Time that EM_data must be valid after rising edge of EM_OE 5– – n s Notes 86. Based on device characterization (Not production tested). 87. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 76. 88. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency.

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11.8 PSoC System Resources

Specifications are valid for –40 °C ≤ TA ≤ 105 °C and TJ ≤ 120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.

11.8.1 POR with Brown Out

For brown out detect in regulated mode, V DDD and VDDA must be ≥ 2.0 V. Brown out detect is not available in externally regulat ed mode.

11.8.2 Voltage Monitors

Table 11-71. Precise Low-Voltage Reset (PRES) with Brown Out DC Specifications Parameter Description Conditions Min Typ Max Units PRESR Rising trip voltage Factory trim 1.64 – 1.68 V PRESF Falling trip voltage 1.62 – 1.66 V Table 11-72. Power-On-Reset (POR) with Brown Out AC Specifications[89] Parameter Description Conditions Min Typ Max Units PRES_TR[90] Response time – – 0.5 µs VDDD/VDDA droop rate Sleep mode – 5 – V/sec Table 11-73. Voltage Monitors DC Specifications Parameter Description Conditions Min Typ Max Units LVI Trip voltage LVI_A/D_SEL[3:0] = 0000b 1.68 1.73 1.77 V LVI_A/D_SEL[3:0] = 0001b 1.89 1.95 2.01 V LVI_A/D_SEL[3:0] = 0010b 2.14 2.20 2.27 V LVI_A/D_SEL[3:0] = 0011b 2.38 2.45 2.53 V LVI_A/D_SEL[3:0] = 0100b 2.62 2.71 2.79 V LVI_A/D_SEL[3:0] = 0101b 2.87 2.95 3.04 V LVI_A/D_SEL[3:0] = 0110b 3.11 3.21 3.31 V LVI_A/D_SEL[3:0] = 0111b 3.35 3.46 3.56 V LVI_A/D_SEL[3:0] = 1000b 3.59 3.70 3.81 V LVI_A/D_SEL[3:0] = 1001b 3.84 3.95 4.07 V LVI_A/D_SEL[3:0] = 1010b 4.08 4.20 4.33 V LVI_A/D_SEL[3:0] = 1011b 4.32 4.45 4.59 V LVI_A/D_SEL[3:0] = 1100b 4.56 4.70 4.84 V LVI_A/D_SEL[3:0] = 1101b 4.83 4.98 5.13 V LVI_A/D_SEL[3:0] = 1110b 5.05 5.21 5.37 V LVI_A/D_SEL[3:0] = 1111b 5.30 5.47 5.63 V HVI Trip voltage 5.57 5.75 5.92 V Table 11-74. Voltage Monitors AC Specifications Parameter Description Conditions Min Typ Max Units LVI_tr[90] Response time – – 1 µs Notes 89. Based on device characterization (Not production tested). 90. This value is calculated, not measured.

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11.8.3 Interrupt Controller

11.8.4 JTAG Interface

Figure 11-79. JTAG Interface Timing Table 11-75. Interrupt Controller AC Specifications Parameter Description Conditions Min Typ Max Units Delay from interrupt signal input to ISR code execution from main line code[91] – – 12 Tcy CPU Delay from interrupt signal input to ISR code execution from ISR code (tail-chaining)[91] – – 6 Tcy CPU TDI TCK T_TDI_setup TDO (1/f_TCK) T_TDI_hold T_TDO_valid T_TDO_hold TMS T_TMS_setup T_TMS_hold Table 11-76. JTAG Interface AC Specifications[92] Parameter Description Conditions Min Typ Max Units f_TCK TCK frequency 3.3 V ≤ VDDD ≤ 5 V – – 12 [93] MHz 1.71 V ≤ VDDD < 3.3 V – – 7 [93] MHz T_TDI_setup TDI setup before TCK high (T/10) – 5 – – ns T_TMS_setup TMS setup before TCK high T/4 – – T_TDI_hold TDI, TMS hold after TCK high T = 1/f_TCK max T/4 – – T_TDO_valid TCK low to TDO valid T = 1/f_TCK max – – 2T/5 T_TDO_hold TDO hold after TC K high T = 1/f_TCK max T/4 – – T_nTRST Minimum nTRST pulse width f_TCK = 2 MHz 8 – – ns Notes 92. Based on device characterization (Not production tested). 93. f_TCK must also be no more than 1/3 CPU clock frequency.

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11.8.5 SWD Interface

Figure 11-80. SWD Interface Timing

11.8.6 TPIU Interface

(PSoC input) SWDCK T_SWDI_setup SWDIO (PSoC output) (1/f_SWDCK) T_SWDI_hold T_SWDO_valid T_SWDO_hold Table 11-77. SWD Interface AC Specifications[94] Parameter Description Conditions Min Typ Max Units f_SWDCK SWDCLK frequency 3.3 V ≤ VDDD ≤ 5 V – – 12 [95] MHz 1.71 V ≤ VDDD < 3.3 V – – 7 [95] MHz 1.71 V ≤ VDDD < 3.3 V, SWD over USBIO pins –– 5 . 5 [95] MHz T_SWDI_setup SWDIO i nput setup before SWDCK high T = 1/f_SWDCK max T/4 – – T_SWDI_hold SWDIO input hold afte r SWDCK high T = 1/f_SWDCK max T/4 – – T_SWDO_valid SWDCK high to SWDI O output T = 1/f_S WDCK max – – T/2 T_SWDO_hold SWDIO output hold after SWDCK high T = 1/f_SWDCK max 1 ––n s Table 11-78. TPIU Interface AC Specifications[94] Parameter Description Conditions Min Typ Max Units TRACEPORT (TRACECLK) frequency – – 33 [96] MHz SWV bit rate – – 33 [96] Mbit Notes 94. Based on device characterization (Not production tested). 95. f_SWDCK must also be no more than 1/3 CPU clock frequency. 96. TRACEPORT signal frequency and bit rate are limited by GPIO output frequency, see Table 11-9 on page 77.

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11.9 Clocking

Specifications are valid for –40 °C ≤ TA ≤ 105 °C and TJ ≤ 120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Unless otherwise specified, all charts and graphs show typical values

11.9.1 Internal Main Oscillator

Figure 11-81. IMO Current vs. Frequency Table 11-79. IMO DC Specifications[97] Parameter Description Conditions Min Typ Max Units Icc_imo Supply current

74.7 MHz – – 730 µA

62.6 MHz – – 600 µA

48 MHz – – 500 µA

24 MHz – USB mode With oscillator locking to USB bus – – 500 µA

24 MHz – non-USB mode – – 300 µA

12 MHz – – 200 µA

6 MHz – – 180 µA

3 MHz – – 150 µA

t, μ 100 200 300 0 1 02 03 04 05 06 07 08 0 Cu e Frequency, MHz Note 97. Based on device characterization (Not production tested). Table 11-80. IMO AC Specifications Parameter Description Conditions Min Typ Max Units FIMO [98] IMO frequency stability (with factory trim)

74.7 MHz –7 – 7 %

62.6 MHz –7 – 7 %

48 MHz –5 – 5 %

24 MHz – non-USB mode –4 – 4 %

24 MHz – USB mode With oscillator locking to USB bus –0.25 – 0.25 %

12 MHz –3 – 3 %

6 MHz –2 – 2 %

3 MHz 0 °C to 70 °C –1 – 1 %

3-MHz frequency stability after typical PCB assembly post-reflow Typical (non-optimized) board layout and 250 °C solder reflow. Device may be calibrated after assembly to improve performance. –± 2 % – %

Document Number: 001-84932 Rev. *N Page 124 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-82. IMO Frequency Variation vs. Temperature Figure 11- 83. IMO Frequency Variation vs. VCC Tstart_imo Startup time[99] From enable (during normal system operation) – – 13 µs Jp-p Jitter (peak to peak)[99] F = 24 MHz –0 . 9 –n s F = 3 MHz –1 . 6 –n s Jperiod Jitter (long term)[100] F = 24 MHz –0 . 9 –n s F = 3 MHz –1 2 –n s Table 11-80. IMO AC Specifications (continued) Parameter Description Conditions Min Typ Max Units 0.25 0.5

62.6 MHz

3 MHz

-0.5 -0.25 - 4 0 - 2 00 2 04 06 08 0 1 0 0 % Variation Temperature, ° C Notes 98. FIMO is measured after packaging, and thus accounts for substrate and die attach stresses. 99. Based on device characterization (Not production tested). 100.Based on device characterization (Not production tested). USBIO pins tied to ground (VSSD).

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11.9.2 Internal Low-Speed Oscillator

Figure 11-84. ILO Frequency Variation vs. Temperature Figure 11- 85. ILO Frequency Variation vs. VDD Table 11-81. ILO DC Specifications Parameter Description Conditions Min Typ Max Units ICC Operating current[101] FOUT = 1 kHz – – 1.7 µA FOUT = 33 kHz – – 2.6 µA FOUT = 100 kHz – – 2.6 µA Leakage current[101] Power down mode – – 15 nA Table 11-82. ILO AC Specifications[102] Parameter Description Conditions Min Typ Max Units Tstart_ilo Startup time, all frequencies Turbo mode – – 2 ms FILO ILO frequencies 100 kHz 45 100 200 kHz 1 kHz 0.5 1 2 kHz % Variation 100 kHz -50 -25 - 4 0 - 2 00 2 04 06 08 0 1 0 0 Temperature, ° C 1 kHz iation -20 -10 % Vari VDDD, V 100 kHz 1 kHz Notes 101.This value is calculated, not measured. 102.Based on device characterization (Not production tested).

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11.9.3 MHz External Crystal Oscillator

For more information on crystal o r ceramic resona tor selection for the MHzECO, refer to application note AN54439: PSoC 3 and PSoC 5 External Oscillators. 11.9.4 kHz External Crystal Oscillator

11.9.5 External Clock Reference

11.9.6 Phase-Locked Loop

Table 11-83. MHzECO DC Specifications Parameter Description Conditions Min Typ Max Units ICC Operating current[103] 13.56 MHz crystal – 3.8 – mA Table 11-84. MHzECO AC Specifications Parameter Description Conditions Min Typ Max Units F Crystal frequency range 4 – 25 MHz Table 11-85. kHzECO DC Specifications[103] Parameter Description Conditions Min Typ Max Units ICC Operating current Low power mode; CL = 6 pF – 0.25 1.0 µA DL Drive level – – 1 µW Table 11-86. kHzECO AC Specifications[103] Parameter Description Conditions Min Typ Max Units F Frequency – 32.768 – kHz TON Startup time High power mode – 1 – s Table 11-87. External Clock Reference AC Specifications[103] Parameter Description Conditions Min Typ Max Units External frequency range 0 – 33 MHz Input duty cycle range Measured at V DDIO/2 30 50 70 % Input edge rate V IL to VIH 0.5 – – V/ns Table 11-88. PLL DC Specifications Parameter Description Conditions Min Typ Max Units IDD PLL operating current In = 3 M Hz, Out = 80 MHz – 650 – µA In = 3 MHz, Out = 67 MHz – 400 – µA In = 3 MHz, Out = 24 MHz – 200 – µA Table 11-89. PLL AC Specifications Parameter Description Conditions Min Typ Max Units Fpllin PLL input frequency [104] 1–4 8 M H z PLL intermediate frequency[105] Output of prescaler 1 – 3 MHz Fpllout PLL output frequency [104] 24 – 80 MHz Lock time at startup – – 250 µs Jperiod-rms Jitter (rms)[103] –– 2 5 0 p s Notes 103.Based on device characterization (Not production tested). 104.This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL. 105.PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.

Document Number: 001-84932 Rev. *N Page 127 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 12. Ordering Information In addition to the features listed in Table 12-1, every CY8C58LP device includes: up to 256 KB flash, 64 KB SRAM, 2 KB EEPROM, a precision on-chip voltage reference, precision oscillators, f lash, ECC, DMA, a fixed function I 2C, JTAG/SWD programming and debug, external memory interface, boost, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C58LP deriv atives incorporate device and flash security in user-selectable security levels; see the TRM for details. Notes 106.Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 40 for more information on how analog blocks can be used. 107.UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 40 for more information on how UDBs can be used. 108.The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See “I/O System and Routing” section on page 33 for details on the functionality of each of these types of I/O. 109.The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID. Table 12-1. CY8C58LP Family with Arm Cortex-M3 CPU Part Number MCU Core Analog Digital I/O[108] Package JTAG ID[109] CPU SPEED (MHZ) FLASH (KB) SRAM (KB) EEPROM (KB) LCD SEGMENT DRIVE ADCS DAC COMPARATORS SC/CT ANALOG BLOCKS[106] OPAMPS DFB CAPSENSE UDBS[107] 16-BIT TIMER/PWM FS USB CAN 2.0B TOTAL I/O GPIO SIO USBIO CY8C5868AXI-LP031 67 256 64 2 ✔ 1x20-bit Del-Sig 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 – – 70 62 8 0 100-TQFP 0x2E11F069 CY8C5868AXI-LP032 67 256 64 2 ✔ 1x20-bit Del-Sig 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ – 72 62 8 2 100-TQFP 0x2E120069 CY8C5868AXI-LP035 67 256 64 2 ✔ 1x20-bit Del-Sig 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ ✔ 72 62 8 2 100-TQFP 0x2E123069 CY8C5868LTI-LP036 67 256 64 2 ✔ 1x20-bit Del-Sig 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 – – 46 38 8 0 68-QFN 0x2E124069 CY8C5868LTI-LP038 67 256 64 2 ✔ 1x20-bit Del-Sig 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ – 48 38 8 2 68-QFN 0x2E126069 CY8C5868LTI-LP039 67 256 64 2 ✔ 1x20-bit Del-Sig 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ ✔ 48 38 8 2 68-QFN 0x2E127069 CY8C5867AXI-LP023 67 128 32 2 ✔ 1x20-bit Del-Sig 1x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 – – 70 62 8 0 100-TQFP 0x2E117069 CY8C5867AXI-LP024 67 128 32 2 ✔ 1x20-bit Del-Sig 1x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ – 72 62 8 2 100-TQFP 0x2E118069 CY8C5867LTI-LP025 67 128 32 2 ✔ 1x20-bit Del-Sig 1x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 – – 46 38 8 0 68-QFN 0x2E119069 CY8C5867LTI-LP028 67 128 32 2 ✔ 1x20-bit Del-Sig 1x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ – 48 38 8 2 68-QFN 0x2E11C069 CY8C5866AXI-LP020 67 64 16 2 ✔ 1x20-bit Del-Sig 1x12-bit SAR 4 4 4 4 ✔ ✔ 20 4 ✔ ✔ 72 62 8 2 100-TQFP 0x2E114069 CY8C5866AXI-LP021 67 64 16 2 ✔ 1x20-bit Del-Sig 1x12-bit SAR 4 4 4 4 ✔ ✔ 20 4 ✔ – 72 62 8 2 100-TQFP 0x2E115069 CY8C5866LTI-LP022 67 64 16 2 ✔ 1x20-bit Del-Sig 1x12-bit SAR 4 4 4 4 ✔ ✔ 20 4 ✔ – 48 38 8 2 68-QFN 0x2E116069 CY8C5888AXI-LP096 80 256 64 2 ✔ 1x20-bit Del-Sig 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ ✔ 72 62 8 2 100-TQFP 0x2E160069 CY8C5888AXQ-LP096 80 256 64 2 ✔ 1x20-bit Del-Sig 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ ✔ 72 62 8 2 100-TQFP 0x2E160069 CY8C5888LTI-LP097 80 256 64 2 ✔ 1x20-bit Del-Sig 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ ✔ 48 38 8 2 68-QFN 0x2E161069 CY8C5888LTQ-LP097 80 256 64 2 ✔ 1x20-bit Del-Sig 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ ✔ 48 38 8 2 68-QFN 0x2E161069 CY8C5888FNI-LP210 80 256 64 2 ✔ 1x20-bit Del-Sig 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ ✔ 72 62 8 2 99-WLCSP 0x2E1D2069 CY8C5888FNI-LP214 80 256 64 2 ✔ 1x20-bit Del-Sig 2x12-bit SAR 4 4 4 4 ✔ ✔ 24 4 ✔ – 72 62 8 2 99-WLCSP 0x2E1D6069

Document Number: 001-84932 Rev. *N Page 128 of 139 PSoC® 5LP: CY8C58LP Family Datasheet

12.1 Part Numbering Conventions

PSoC 5LP devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9, A, B, …, Z) unless stated otherwise. CY8Cabcdefg-LPxxx  a: Architecture  3: PSoC 3  5: PSoC 5  b: Family group within architecture  2: CY8C52LP family  4: CY8C54LP family  6: CY8C56LP family  8: CY8C58LP family  c: Speed grade  6: 67 MHz  8: 80 MHz  d: Flash capacity  5: 32 KB  6: 64 KB  7: 128 KB  8: 256 KB  ef: Package code  Two character alphanumeric  AX: TQFP  LT: QFN  PV: SSOP  FN: CSP  g: Temperature Range  C: Commercial  I: Industrial  Q: Extended  A: Automotive  xxx: Peripheral set  Three character numeric  No meaning is associated with these three characters Tape and reel versions of these devices are available and are marked with a “T” at the end of the part number. All devices in the PSoC 5LP CY8C58LP family comply to RoHS-6 sp ecifications, demonstrating t he commitment by Cypress to lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages. A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of life” requirements. Architecture Cypress Prefix Family Group within Architecture Speed Grade Flash Capacity Package Code Temperature Range Peripheral Set 5: PSoC 5 8: 80 MHz 8: 256 KB AX: TQFP, PV: SSOP I: Industrial Examples CY8C 5 8 X A88I x LPx-x 8: CY8C58LP Family /PV

Document Number: 001-84932 Rev. *N Page 129 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 13. Packaging Table 13-1. Package Characteristics Parameter Description Conditions Min Typ Max Units TA Operating ambient temperature –40 25 105 °C TJ Operating junction temperature –40 – 120 °C TA Operating ambient temperature For CSP parts –40 25 85 °C TJ Operating junction temperature For CSP parts –40 – 100 °C TJc Package θJC (99-ball CSP) – 0.1 – °C/Watt Table 13-2. Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature 68-pin QFN 260 °C 30 seconds 100-pin TQFP 260 °C 30 seconds 99-ball WLCSP 255 °C 30 seconds Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 68-pin QFN MSL 3 100-pin TQFP MSL 3 99-ball WLCSP MSL1

Document Number: 001-84932 Rev. *N Page 131 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 13-3. WLCSP Package (5.192 × 5.940 × 0.6 mm) Package Outline 001-88034 *B

Document Number: 001-84932 Rev. *N Page 132 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 14. Acronyms Table 14-1. Acronyms Used in this Document Acronym Description abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced micro controller bus archi- tecture) high-performance bus, an Arm data transfer bus ALU arithmetic logic unit AMUXBUS analog mu ltiplexer bus API application programming interface APSR application program status register Arm ® advanced RISC machine, a CPU architecture ATM automatic thump mode BW bandwidth CAN Controller Area Network, a communications protocol CMRR common-mode rejection ratio CPU central processing unit CRC cyclic redundancy check, an error-checking protocol DAC digital-to-analog converter, see also IDAC, VDAC DFB digital filter block DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. DMA direct memory access, see also TD DNL differential nonlinearity, see also INL DNU do not use DR port write data registers DSI digital system interconnect DWT data watchpoint and trace ECC error correcting code ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory EMI electromagnetic interference EMIF external memory interface EOC end of conversion EOF end of frame EPSR execution program status register ESD electrostatic discharge ETM embedded trace macrocell FIR finite impulse re sponse, see also IIR FPB flash patch and breakpoint FS full-speed GPIO general-purpose input/output, applies to a PSoC pin HVI high-voltage interrupt, see also LVI, LVD IC integrated circuit IDAC current DAC, see also DAC, VDAC IDE integrated development environment I 2C, or IIC Inter-Integrated Circuit, a communications protocol IIR infinite impulse r esponse, see also FIR ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO INL integral nonlinearity, see also DNL I/O input/output, see also GPIO, DIO, SIO, USBIO IPOR initial power-on reset IPSR interrupt program status register IRQ interrupt request ITM instrumentation trace macrocell LCD liquid crystal display LIN Local Interconnect Network, a communications protocol. LR link register LUT lookup table LVD low-voltage detect, see also LVI LVI low-voltage interrupt, see also HVI LVTTL low-voltage transistor-transistor logic MAC multiply-accumulate MCU microcontroller unit MISO master-in slave-out NC no connect NMI nonmaskable interrupt NRZ non-return-to-zero NVIC nested vectored interrupt controller NVL nonvolatile latch, see also WOL opamp operational amplifier PAL programmable array logic, see also PLD PC program counter PCB printed circuit board PGA programmable gain amplifier Table 14-1. Acronyms Used in this Document (continued) Acronym Description

Document Number: 001-84932 Rev. *N Page 133 of 139 PSoC® 5LP: CY8C58LP Family Datasheet PHUB peripheral hub PHY physical layer PICU port interrupt control unit PLA programmable logic array PLD programmable logic device, see also PAL PLL phase-locked loop PMDD package material declaration datasheet POR power-on reset PRES precise low-voltage reset PRS pseudo random sequence PS port read data register PSoC ® Programmable System-on-Chip™ PSRR power supply rejection ratio PWM pulse-width modulator RAM random-access memory RISC reduced-instruct ion-set computing RMS root-mean-square RTC real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC/CT switched capacitor/continuous time SCL I 2C serial clock SDA I 2C serial data S/H sample and hold SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced features. See GPIO. SOC start of conversion SOF start of frame SPI Serial Peripheral Interface, a communications protocol SR slew rate SRAM static random access memory SRES software reset SWD serial wire debug, a test protocol SWV single-wire viewer TD transaction descriptor, see also DMA THD total harmonic distortion Table 14-1. Acronyms Used in this Document (continued) Acronym Description TIA transimpedance amplifier TRM technical reference manual TTL transistor-transistor logic TX transmit UART Universal Asynchronous Transmitter Receiver, a communications protocol UDB universal digital block USB Universal Serial Bus USBIO USB input/output, PSoC pins used to connect to a USB port VDAC voltage DAC, s ee also DAC, IDAC WDT watchdog timer WOL write once latch, see also NVL WRES watchdog timer reset XRES external reset pin XTAL crystal Table 14-1. Acronyms Used in this Document (continued) Acronym Description

Document Number: 001-84932 Rev. *N Page 134 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 15. Document Conventions

15.1 Units of Measure

Table 15-1. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohours kHz kilohertz kΩ kilohms ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz MΩ megaohms Msps megasamples per second µA microamperes µF microfarads µH microhenrys µs microseconds µV microvolts µW microwatts mA milliamperes ms milliseconds mV millivolts nA nanoamperes ns nanoseconds nV nanovolts Ω ohms pF picofarads ppm parts per million ps picoseconds s seconds sps samples per second sqrtHz square root of hertz Vv o l t s

Document Number: 001-84932 Rev. *N Page 135 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Document History Page Description Title: PSoC® 5LP: CY8C58LP Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-84932 Revision ECN Submission Date Description of Change ** 3825653 12/07/2012 Datasheet for new CY8C58LP family *A 3897878 02/07/2013 Updated char acterization footnotes in Electrical Specifications. Updated conditions for SAR ADC INL and DNL specifications in Table 11-28 Changed number of opamps in Ordering Information Removed Preliminary status Removed references to CAN. Updated INL VIDAC spec. *B 3902085 02/12/2013 Changed Hibernat e wakeup time from 125 µs to 200 µs in Table 6-3 and Table 11-3. *C 3917994 01/03/2013 Added Controller Area Network (CAN) content. *D 4114902 09/30/2013 Added informati on about 1 KB cache in Features. Added warning on reset devices in the EEPROM section. Added DBGEN field in Table 5-3. Deleted statement about repeat start from the I2C section. Removed TSTG spec from Table 11-1 and added a note clarifying the maximum storage temperature range. Updated chip Idd, regulator, opamp, delta-sigma ADC, SAR ADC, IDAC, and VDAC graphs. Added min and max values for the Regulator Output Capacitor parameter. Updated CIN specs in GPIO DC Specifications and SIO DC Specifications. Updated rise and fall time specs in Fast Strong mode in Table 11-9, and deleted related graphs. Added IIB parameter in Opamp DC Specifications Updated Vos spec conditions and changed TCVos max value from 0.55 to 1 in Table 11-20. Updated Voltage Reference Specifications and IMO AC Specifications. Updated FIMO spec (3 MHz). Updated 100-TQFP package diagram. Added Appendix for CSP package (preliminary). *E 4225729 12/20/2013 Added SIO Com parator Specifications. Changed T HIBERNATE wakeup spec from 200 to 150 µs. Updated CSP package details and ordering information. Added 80 MHz parts in Table 12-1. *F 4386988 05/22/2014 Updated General Description and Features. Added More Information and PSoC Creator sections. Updated JTAG IDs in Ordering Information. Updated 100-TQFP package diagram. *G 4587100 12/08/2014 Added link to AN72845 in Note 3. Updated interrupt priority numbers in Section 4.4. Updated Section 5.4 to clarify the factory default values of EEPROM. Corrected ECCEN settings in Table 5-3. Added a note below Figure 6-4. Updated Figure 6-11. Changed ‘Control Store RAM’ to ‘Dynamic Configuration RAM’ in Figure 7-4 and changed Section 7.2.2.2 heading to ‘Dynamic Configuration RAM’. Updated Section 7.8.

Document Number: 001-84932 Rev. *N Page 137 of 139 PSoC® 5LP: CY8C58LP Family Datasheet *H (cont.) 4698847 03/24/2015 Updated Electrical Specifications: Updated Memory: Updated Flash: Updated Table 11-62: Updated details in “Conditions” column corresponding to “Flash data retention time” parameter. Added Note 80 and referred the same note in last condition corresponding to “Flash data retention time” parameter. Updated EEPROM: Updated Table 11-64: Updated details in “Conditions” column corresponding to “EEPROM data retention time” parameter. Added Note 80 and referred the same note in last condition corresponding to “EEPROM data retention time” parameter. Updated Nonvolatile Latches (NVL): Updated Table 11-66: Updated details in “Conditions” column corresponding to “NVL data retention time” parameter. Added Note 81 and referred the same note in last condition corresponding to “NVL data retention time” parameter. Updated Clocking: Updated Internal Main Oscillator: Updated Table 11-80: Replaced 85 °C with 105 °C. Updated Figure 11-83. Updated Ordering Information: Updated Table 12-1: Updated part numbers. Updated Part Numbering Conventions: Added “Q: Extended” as sub bullet under “g: Temperature Range”. Updated Packaging: Updated Table 13-1: Changed maximum value of T A parameter from 85 °C to 105 °C. Changed maximum value of TJ parameter from 100 °C to 120 °C. Updated : Updated : spec 001-88034 – Changed revision from ** to *A. *I 4839323 07/15/2015 Added reference to code examples in More Information. Updated typ value of T WRITE from 2 to 10 in EEPROM AC specs table. Changed “Device supply for USB operation" to "Device supply (VDDD) for USB operation" in USB DC Specifications. Clarified power supply sequencing and margin for VDDA and VDDD. Updated Serial Wire Debug Interface with limitations of debugging on Port 15. Updated Delta-sigma ADC DC Specifications Document History Page (continued) Description Title: PSoC® 5LP: CY8C58LP Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-84932 Revision ECN Submission Date Description of Change

Document Number: 001-84932 Rev. *N Page 138 of 139 PSoC® 5LP: CY8C58LP Family Datasheet *J 5030641 11/30/2015 Added Table 2-1. Removed the configurable XRES information. Updated Section 5.6 Updated Section 6.3.1.1. Updated values for DSI Fmax, Fgpioin max, and Fsioin max. Corrected the web link for the PSoC 5 Device Programming Specifications in Section 9. Updated CSP Package Bootloader section. Added MHzECO DC Specifications. Updated 99-WLCSP and 100-pin TQFP package drawings. Added a footnote reference for the “CY8C5287AXI-LP095” part in Table 12-1 clarifying that it has 256 KB flash. Added the CY8C5667AXQ-LP040 part in Table 12-1. *K 5478402 10/25/2016 Updated More Information. Add Links to CAD Libraries in Section 2. Corrected typos in External Electrical Connections. *L 5703770 04/20/2017 Updat ed the Cypress logo and copyright information. *M 6385319 11/15/2018 Added a footnot e on DNU pins for the WLCSP pinout table. Updated the links in Sales, Solutions, and Legal Information. *N 6739970 11/27/2019 Updated the paragraph in section Inputs and Outputs. Completing Sunset review. Document History Page (continued) Description Title: PSoC® 5LP: CY8C58LP Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-84932 Revision ECN Submission Date Description of Change

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