AN6494NSA PANASONIC | Alldatasheet

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Technical content

The AN6494NSA is an orthogonal modulator IC for digital cellular telephones. It incorporates a phase shifter and an APC circuit for indirect modulation in the 1.5GHz band. It efficiently prevents power from leaking to adjacent channels. When pro- vided with an LC filter, it can efficiently suppress IF-band local harmonic spurious. n Features

  • Operating supply voltage range : 2.7V to 4.0V
  • 1.5GHz indirect modulation
  • LO1’s eighth-order harmonic suppression : –65dBc or better
  • Output power level : –13dBm
  • Variable range : APC = typ. 38dB (at fout=1.5GHz)
  • Phase shifter frequency : 178MHz
  • Package : SSOP016-P-0225A with 0.65mm pitch AN6494NSA Digital Communication Orthogonal Modulator IC 5.00–0.20 0.65 Unit : mm SOP package with 16 pins (SSOP016-P-0225A) 16 9 1.20–0.2 6.40–0.30 4.40–0.20 0.22+0.10 –0.05 (0.225) SEATING PLANE (1.0) 0 —10˚ 0.50–0.20 0.15 + 0.10– 0.05 0.10–0.10 SEATING PLANE n Block Diagram 81234567 916 15 14 13 12 11 10 M LPF NC V CC Q Q I I PO V APC L01 L02

Pin N o. D escription V C C (m od) Q input Q input I input I input LC 1 LO 1 G N D Pin N o. D escription LO 2R LO 2 A PC /B S LC 2 N C G N D R Foutput V C C (U P–M IX ) Param eter Sym bol R ating U nit n A bsolute M axim um R atings (Ta=25˚C ) Supply voltage Supply current Pow er dissipation O perating am bient tem perature Storage tem perature V C C IC C PD Topr Tstg 4.2 252 (Ta=80˚C ) –30 to + 80 –55 to + 125 V m A m W Param eter Sym bol R ange n R ecom m ended O perating R ange O perating supply voltage range V C C 2.7V to 4.0V Param eter Sym bol C ondition m in typ m ax U nit n Electrical C haracteristics (Ta=25–2˚C ) O utput level (1) O utput level (2) C urrent consum ption Sleep current M inim um output level PO 1 PO 2 IC C ISL Pm in LO 1=178M H z, –20dB m LO 2=1607M H z, –25dB m V A PC =2.5V LO 1=178M H z, –20dB m LO 2=1631M H z, –25dB m V A PC =2.5V LO 1=178M H z, –20dB m LO 2=1619M H z, –25dB m V A PC =2.5V LO 1=178M H z, –20dB m LO 2=1619M H z, –25dB m V A PC =0V LO 1=178M H z, –20dB m LO 2=1619M H z, –25dB m V A PC =1.0V –16 –16 –13 –13 –52 –10 –10 –45 dB m dB m m A µA dB m N ote) V C C =3.7V IQ signal : 0.5V P–P (single phase), π/4 Q PSK m odulated PO 1 output frequency : 1428.0025M H z PO 2 output frequency : 1453.0025M H z Pm in output frequency : 1441.0025M H z

Param eter Sym bol C ondition m in typ m ax U nit n Electrical C haracteristics (D esign V alues for R eference) (Ta=25–2˚C ) C arrier leak suppression (fLO 2–fLO 1) *1 Im age leak suppression *1 A djacent spurious suppression *1 B ase-band distortion suppression *1 3rd interm odulation distortion suppression *2 (Po = –10dB m ) A djacent channel pow er leak suppression (50kH z separation) *3 A djacent channel pow er leak suppression (100 kH z separation) *3 A PC variation range *1 A PC output level control sensitivity *1 In-band output level deviation *1 D irect conversion m odulation current consum ption *1 U p-m ixer current consum ption * C L IL D U B D IM 3 B L1 B L2 LA PC SA PC ΔP IM D IU M LO 1=178M H z, –20dB m LO 2=1619M H z, –25dB m V A PC =2.5V , IQ : V D C offset adjust LO 1=178M H z, –20dB m LO 2=1619M H z, –25dB m V A PC =2.5V , IQ : V A C level adjust LO 1=178M H z, –20dB m LO 2=1619M H z, –25dB m V A PC =2.5V LO 1=178M H z, –20dB m LO 2=1619M H z, –25dB m V A PC =2.5V LO 1=178M H z, –20dB m LO 2=1619M H z, –25dB m V A PC =2.5V LO 1=178M H z, –20dB m LO 2=1619M H z, –25dB m V A PC =2.5V LO 1=178M H z, –20dB m LO 2=1619M H z, –25dB m V A PC =2.5V LO 1=178M H z, –20dB m LO 2=1619M H z, –25dB m V A PC =1.0 — 2.5V LO 1=178M H z, –20dB m LO 2=1619M H z, –25dB m V A PC =1.0 — 2.5V LO 1=178M H z, –20dB m Lo2=1607M H z— 1631M H z, –25dB m V A PC =2.5V LO 1=178M H z, –20dB m LO 2=1619M H z, –25dB m V A PC =2.5V LO 1=178M H z, –20dB m LO 2=1619M H z, –25dB m V A PC =2.5V –1.5 –35 –40 –70 –40 –35 –30 –35 –65 –60 –65 +1.5 dB c dB c dB c dB c dB c dB c dB c dB dB /V dB m A m A N ote) V C C = 3.7V IQ signal : 0.5V P–P (single phase), 1.85V D C *1 : π/4 Q PSK m odulation *2 : 3π/4 Q PSK m odulation *3 : PN 9-stage m odulation A PC output level sensitivity w as m easured w ith V A PC =1.0V and V A PC =1.6V . The follow ing are design values for reference only (not guaranteed). n U sage N ote Surge breakdow n levels The follow ing are design values for reference only (not guaranteed). C ondition : C =200pF, and R =0Ω Pin N o. Positive breakdow n level (V ) 170 N egative breakdow n level (V )

D C bias (V ) 1.7— (V C C – 0.9) Sym bol Equivalent circuit This is the supply voltage pin for the direct conversion m odulator. The IC incorporates a band-gap regulator to provide a regulated bias independent of V C C or tem perature change. V C C Pin N o. A n external LC connected to this pin rem oves spurious from the transm ission band by raising up the Lo1 input fre- quency band. The output is an em itter follow er. Inverted-I signal input. A pply 1.5— (V C C – 0.9) V for single-phase input m ode. I signal input. The relationship betw een input D C bias and am plitude is as follow s : I/O D escription I I I I I A m plitude V P–P 0.5 (single phase) Input im pedance is 100kΩ or m ore. 2 3 4 52kΩ 6 12 External n Pin D escriptions D C bias (V ) 1.7— (V C C – 0.9) Inverted-Q signal input. A pply 1.5— (V C C – 0.9)V for single-phase input m ode. Q signal input. The relationship betw een input D C bias and am plitude is as follow s : A m plitude V P–P 0.5 (single phase) Input im pedance is 100kΩ or m ore.

4 Q I

5 Q I

6 LC 1

2kΩ

V A PC (V ) 0 — 0.5 1.0 — V C C Sym bol Equivalent circuit This is the local input to the orthogonal m odulator. T he input im pedance is 10kΩ . Lo1 Pin N o. A n external LC connected to this pin rem oves spurious from the transm ission band by raising up the Lo1 input fre- quency band. The output is an em itter follow er. This is a local input to the U P m ixer. A n external balance coil should be used to provide balanced input. This is a local input to the U P m ixer. A n external balance coil should be used to provide balanced input. This is the ground for the orthogonal m odulator. The ground foil pattern for this pin m ust be w ide enough to provide a low im pedance. G N D8 10kΩ 2pF 2pF 2pF 340Ω 340Ω 5pF 2pF 7kΩ 5pF 10 9 5pF 1kΩ 1kΩ 10kΩ 10kΩ 3kΩ R egulator 6 12 External (A PC control) I/O D escription I Lo2 R EF I Lo2 I A PC /B S I LC 2 This is the battery save control for all circuits. It also controls R F output pow - er. Status O FF O N (A PC control) The input im pedance is 5kΩ or m ore. n Pin D escriptions (cont.)

Sym bol Equivalent circuit This is the ground for the U P m ixer and the output am plifier. The ground foil pattern for this pin m ust be w ide enough to provide a low im pedance for high fre- quencies. N C Pin N o. This is the pow er supply for the U P m ixer and the output am plifier circuit. It incorporates a regulating circuit to provide a regulated bias independent of V C C or tem perature change. This is the R F output from the output am plifier circuit (em itter follow er). G N D14 I/O D escription R F output O V C C I 200Ω 200Ω n Pin D escriptions (cont.) (T= 80˚C ) (T= 27˚C ) (T= –30˚C ) 0 1 2 3 A PC C ontrol V oltage (V ) –80 –70 –60 –50 C ircuit O FF –80 –70 –60 –50 –40 –30 –20 –10 A PC C ontrol V oltage C haracteristics V C C =3.0V LO 1=178M H Z, –20dB m LO 2=1619M H Z, –25dB m IQ signal : 0.5V p-p (single phase) O utput Level (dB m ) /Im age Leak Suppression (dB c) A djacent C hannel Leak Pow er Suppression (50kH z Separation) (dB c) A djacent C hannel Leak Pow er Suppression (100kH z Separation) (dB c) n C haracteristics C urve N earby Spurious Suppression (dB c) PO IL B L1 B L2 D U