AN5829

AN5829S PANASONIC | Alldatasheet

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Technical content

Sound multiplex decoder IC for the U.S. televisions n Overview The AN5829S is a multiplex sound demodulation IC dedicated to the U.S. television and incorporates a bi- directional I 2C interface (adjustment, mode SW), an AGC circuit and external stereo input switches (2 systems). n Features

• Stereo demodulation, SAP demodulation, dbx noise re- duction, AGC, external stereo input SW and I2C bus interface are integrated in a single chip
• Bi-directional I2C bus makes it possible to monitor MPX input level, separation adjustment (3 places), mode changeover and receiving status.
• Eliminated external parts (multi-sound block: 21 pieces fi 14 pieces
• Lower power dissipation (V CC = 5 V, ITOT = 18 mA) n Applications
• Televisions and VCRs for the North American market SOP024-P-0375A Unit: mm 0.3 7.2–0.3 9.4–0.3 0.15 0.925 2.0–0.2 15.3–0.3

RMS det. Spectral RMS det. Wide band expand Spectral expand dbx De-emph. (L-R)/SAP switch Offset cancel 75 ms De-emph. L+R filter Pilot cancel L-R filter SAP out filter Pilot det. L+R demod St. PLL L-R demod SAP demod Noise det. Noise filter SAP filter Input VCA SAP det. Stereo filter fH , 2fH Trap filter DAC Out SW AGC Matrix Offset cancel

Pin No. Description

1 AGC timing

2 External input 1 L-ch

3 External input 1 R-ch

4 75 ms filter offset cancel 5 dbx offset cancel

6 Wideband timing

8 Wideband level sensor input

9 Spectral filter

10 Spectral timing

11 Spectral level sensor input

12 SAP noise level detection

Parameter Symbol Rating Unit Supply voltage V CC 6.0 V Supply current I CC 25 mA Power dissipation *2 PD 150 mW Operating ambient temperature *1 T opr -20 to +75 °C Storage temperature *1 Tstg -55 to +125 °C n Absolute Maximum Ratings Note) The use of this IC, which builds in dbx-TV noise reduction, requires a license agreement with THAT Corporation. *1: Except fot the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C. *2: Ta = 75°C n Recommended Operating Range Pin No. Description

13 SAP carrier detection

14 Composite input

15 Pilot signal detection

16 Stereo PLL filter

17 GND

18 SCL

19 SDA

20 PE for ZAP

21 L-ch output

22 R-ch output

23 External input 2 R-ch. 24 External input 2 L-ch. Parameter Symbol Range Unit Supply voltage V CC 4.5 to 5.5 V

Parameter Symbol Conditions Min Typ Max Unit Total circuit current I CC No signal 11 18 25 mA Mono output level V 0(MON) f = 1 kHz, (mono) 100%mod 430 480 530 mV[rms] Mono frequency characteristics-1V 1(MON) f = 300 Hz, (mono) 30%mod - 0.5 0 0.5 dB Mono frequency characteristics-2V 2(MON) f = 8 kHz, (mono) 30%mod -1.2 - 0.1 0.7 dB Mono distortion ratio THD (MON) f = 1 kHz, (mono) 100%mod ¾¾ 0.7 % Mono noise level V N(MON) Input short-circuit, BPF (A curve)¾¾ - 60 dBV (L), (R) output voltage differenceV LR(MON) f = 1 kHz, (mono) 100%mod - 0.5 0 0.5 dB Stereo output level V 0(ST) f = 1 kHz, (L(R)-only) 100%mod 380 480 580 mV[rms] Stereo frequency characteristics-1V 1(ST) f = 300 Hz, (L(R)-only) 30%mod - 0.7 0 0.7 dB Stereo frequency characteristics-2V 2(ST) f = 3 kHz, (L(R)-only) 30%mod -10 1 d B Stereo frequency characteristics-3V 3(ST) f = 8 kHz, (L(R)-only) 30%mod -2.5 - 0.5 1.5 dB Stereo distortion ratio THD (ST) f = 1 kHz, (L(R)-only) 100%mod ¾¾ 1% Stereo noise level V N(ST) f = 15.73 kHz, (fH ), 15 mV[rms] ¾¾ - 60 dBV fH , 2 fH Trap+BPF Stereo discrimination level VTH(ST) f = 15.73 kHz (fH )4 8 1 3 mV[rms] Stereo discrimination hysteresis VHY(ST) f = 15.73 kHz (fH ) 0.5 ¾ 5d B SAP output level V 0(SAP) f = 1 kHz, (SAP) 100%mod 370 500 680 mV[rms] SAP frequency characteristics-1 V1(SAP) f = 300 Hz, (SAP) 30%mod -10 1 d B SAP frequency characteristics-2 V2(SAP) f = 3 kHz, (SAP) 30%mod -2.5 - 0.5 1 dB SAP distortion ratio THD (SAP) f = 1 kHz, (SAP) 100% ¾¾ 1.5 % SAP noise level V N(SAP) f = 78.7 kHz, (5fH ),V= 45 mV[rms], BPF ¾¾ - 70 dBV SAP discrimination level V TH(SAP) f = 78.7 kHz, (5fH )1 1 ¾ 26 mV[rms] SAP discrimination hysteresis VHY(SAP) f = 78.7 kHz, (5fH ) 0.5 ¾ 5d B SAP fi Stereo crosstalk C T1 (SAP)1 kHz, 100%mod ¾¾ - 50 dB (Stereo) pilot-signal Stereo fi SAP crosstalk C T2 (Stereo) 1 kHz, 100%mod ¾¾ - 50 dB (SAP) carrier-signal SAP fi Mono crosstalk C T3 (SAP) 1 kHz, 100%mod ¾¾ - 50 dB Mono fi SAP crosstalk C T4 (Mono) 1 kHz, 100%mod ¾¾ - 56 dB (SAP) carrier-signal AUX 1, AUX 2 to INT C T5 f = 1 kHz, VIN = 500 mV[rms] ¾¾ 50 dB crosstalk INT, AUX 2 to AUX 1 C T6 INT: (mono) 1 kHz, 100%mod ¾¾ 50 dB crosstalk EXT: f = 1 kHz, 500 mV[rms] INT, AUX 1 to AUX 2 C T7 INT: (mono) 1 kHz, 100%mod ¾¾ 50 dB crosstalk EXT: f = 1 kHz, 500 mV[rms] n Electrical Characteristics at VCC = 5 V, NR: On,Ta = 25°C Input level (at 100% modulation) L+R: 75 mV[rms] (pre-emphasis off) L-R: 150 mV[rms] (dbx noise reduction off) Pilot: 15 mV[rms] SAP: 45 mV[rms] (dbx noise reduction off)

Parameter Symbol Conditions Min Typ Max Unit Stereo separation (100%)-1 Sep100-1 f = 300 Hz, (L(R)-only) 100% mod 20 35 ¾ dB Stereo separation (100%)-2 Sep100-2 f = 1 kHz, (L(R)-only) 100 % mod 17 28 ¾ dB Stereo separation (100%)-3 Sep100-3 f = 3 kHz, (L(R)-only) 100% mod 20 35 ¾ dB Stereo separation (100%)-4 Sep100-4 f = 8 kHz, (L(R)-only) 100% mod 10 18 ¾ dB Stereo separation (30%)-1 Sep 30-1 f = 300 Hz, (L(R)-only) 30% mod 22 35 ¾ dB Stereo separation (30%)-2 Sep 30-2 f = 1 kHz, (L(R)-only) 30% mod 20 35 ¾ dB Stereo separation (30%)-3 Sep 30-3 f = 3 kHz, (L(R)-only) 30% mod 22 35 ¾ dB Stereo separation (30%)-4 Sep 30-4 f = 8 kHz, (L(R)-only) 30% mod 14 22 ¾ dB Stereo separation (10%)-1 Sep 10-1 f = 300 Hz, (L(R)-only) 10% mod 20 35 ¾ dB Stereo separation (10%)-2 Sep 10-2 f = 1 kHz, (L(R)-only) 10% mod 20 35 ¾ dB Stereo separation (10%)-3 Sep 10-3 f = 3 kHz, (L(R)-only) 10% mod 20 30 ¾ dB Stereo separation (10%)-4 Sep 10-4 f = 8 kHz, (L(R)-only) 10% mod 14 22 ¾ dB I2 C interface Bus free before start t BUF ¾ 4.0 ¾¾ m s Start condition set-up time tSU.STA ¾ 4.0 ¾¾ m s Start condition hold time t HD.STA ¾ 4.0 ¾¾ m s Low period SCL, SDA t LO ¾ 4.0 ¾¾ m s High period SCL t HI ¾ 4.0 ¾¾ m s Rise time SCL, SDA t r ¾ ¾ ¾ 1.0 ms Fall time SCL, SDA t f ¾ ¾ ¾ 0.35 ms Data set-up time (write) t SU.DAT ¾ 0.25 ¾¾ m s Data hold time (write) t HD.DAT ¾ 0.3 ¾¾ m s Acknowledge set-up time t SU.ACK ¾ ¾ ¾ 3.5 ms Acknowledge hold time t HD.ACK ¾ 0 ¾¾ m s Stop condition set-up time tSU.STO ¾ 4.0 ¾¾ m s Parameter Symbol Conditions Min Typ Max Unit AGC gain 1*1 V AGC1 f = 1 kHz, VIN(EXT) = 50 mV[rms] 67 100 140 mV[rms] AGC gain 2 *1 V AGC2 f = 1 kHz, VIN(EXT) = 500 mV[rms] 180 270 390 mV[rms] I2 C interface Sink current at ACK I ACK Maximum pin 2 sink current at ACK 1 2 20 mA SCL, SDA signal input high levelV IHI ¾ 3.5 ¾ 5.0 V SCL, SDA signal input low levelV ILO ¾ 0 ¾ 0.9 V Input available maximum frequencyfImax ¾ ¾ ¾ 100 kbit/s n Electrical Characteristics at VCC = 5 V, NR: On,Ta = 25°C (continued) Note) *1: 00H register: D7 = 0, D6 = 1

• Design reference data Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.

Pin No. Equivalent circuit Description DC voltage (V) 1 AGC: 0.5 to 2.0 AGC level sensor pin 2 AUXIL: 2.2 External input1 L-ch input pin 3 AUXIR: 2.2 External input 1 R-ch input pin n Terminal Equivalent Circuits n Electrical Characteristics at VCC = 5 V, NR: On,Ta = 25°C (continued) SDA SCL Start condition Slave address tSU.DAT tHD.DAT tLO tSU.STOtBUF tSU.STA tHDSTA tr tf tHI tLO ACK ACK ACK Data byte Stop conditionSub address GND 51 kW 500 W 425 W V CC GND 20.7 kW 13.8 kW 2.2 V V CC GND 20.7 kW 13.8 kW 2.2 V V CC

Pin No. Equivalent circuit Description DC voltage (V) 4 OFCAN1: 2.2 75 ms filter output Offset cancel pin 5 OFCAN2: 2.2 dbx output Offset cancel pin 6 WBTIME: 2.2 Wide expander effective value detec- tion recovery time set-up pin 7 ¾ V CC : VCC pin V CC 8 WBDET: 2.2 RMS detection circuit input pin of wide band expander n Terminal Equivalent Circuits (continued) GND 80 kW V CC 80 kW 524 W 2.2 V GND 80 kW V CC 80 kW 524 W 2.2 V 29 W 29 W 7.5 mA 15 mA GND V CC GND 14.4 kW 2.2 V V CC

Pin No. Equivalent circuit Description DC voltage (V) 9 SPEFIL: 2.2 Variable de-emphasis level adjusting pin 10 SPETIME: 0.2 RMS detection recovery time pin of variable de-emphasis 11 SPEDET: 2.2 RMS detection circuit input pin of variable de-emphasis

12 NOISEDET: V CC - 2 VBE

Noise detecting pin of SAP malfunc- tion-prevention-circuit(Mute SAP de- modulation at detecting noise.) n Terminal Equivalent Circuits (continued) GND 230 W 18 kW 18 kW 2.2 V V CC 230 W 29 W 29 W 7.5 mA 15 mA GND V CC GND 3.2 kW 2.2 V V CC GND V CC 141 kW

Pin No. Equivalent circuit Description DC voltage (V)

13 SAPDET: V CC - 2 VBE

SAP signal carrier level detection pin 14 MPXIN: 2.2 Composite signal input pin 15 PILOTDET: 2.2VCC - 2 VBE Stereo pilot signal detection pin

16 PLL: V CC - 2 VBE

Stereo PLL low pass filter connection pin 17 ¾ GND: GND pin 0 n Terminal Equivalent Circuits (continued) GND V CC 163 kW GND 524 W 54.4 kW 2.2 V V CC GND V CC 136 kW GND V CC 58 kW

Pin No. Equivalent circuit Description DC voltage (V)

18 SCL: ¾

19 SDA: 2.2 I2C bus data input pin

20 PE: ¾

Current application input pin for ZAP at final test 21 L-OUT: 2.2 L-ch. line out output pin n Terminal Equivalent Circuits (continued) GND V CC 51 kW 1.7 kW GND V CC 51 kW 1.7 kW GND GND 850 W 520 W 430 W 2.2 V V CC

Pin No. Equivalent circuit Description DC voltage (V) 22 R OUT: 2.2 R-ch. line out output pin 23 AUX2R: 2.2 External input 2 L-ch. input pin 24 AUX2L: 2.2 External input 2 R-ch. input pin n Terminal Equivalent Circuits (continued) GND 850 W 520 W 430 W 2.2 V V CC GND 20.7 kW 13.8 kW 2.2 V V CC GND 20.7 kW 13.8 kW 2.2 V V CC

1. AGC set-up method By turning on AGC, the AGC performs 0 dB at a small signal input, Boost at a medium signal and gain reduction at a big signal. It can also control the I/O characteristics of AGC by I2C as shown below: AGC characteristics 2. Guarantee of I2C operating temperature I2C bus control operation at an operating ambient temperature is theoretially guranteed based on IC design by means of the inspection using about 50% faster clock speed at the normal temperature (Ta = 25°C). Namely it is a theoretical value based on IC design, therefore it is not guranteed at the shipping inspection because the inspection under a high and low temperature is not conducted. 3. Electrostatic breakdown Pay attention to the following levels: Pin 6: 200 pF, 130 V Pin 10: 200 pF, 150 V Pin 22: 200 pF, 190 V 1 mV1 mV 10 mV 10 mV 100 mV 100 mV 1 V 10 V 1 V Input level (rms) Output level (rms) "00" "11" "01" "10" AGC = On AGC = Off Data of sub address 00H D7 D6

B 0010 0000 0000 1000 SDA SCL Start condition Slave address Acknowledge bit Acknowledge bit Acknowledge bit Data Stop condition Sub address n Technical Information [1] I2C bus 1. Receiving mode Transmission message As transfer messages, SCL and SDA are transfered synchronouslly and serially. SCL is a constant clock frequency and SDA is address data for controlling a receiving side and is sent in parallel by synchronizing with SCL. Data are in principle sent by 8-bit 3-octet (byte) and there exists an acknowledge bit per octet. The frame structure is mentioned below: 1) Start condition When SDA becomes from high to low at SCL = high, the receiver gets ready to receive. 2) Stop condition When SDA becomes from low to high at SCL = high, the receiver stops receiving. 3) Slave address Specified for each device. If any addresses of other devices are sent, receiving will be stopped. 4) Sub-address Specified for each function. 5) Data Data for controlling 6) Acknowledge bit This is the bit that informs the master of data reception every octet. The master sends the high signal and the receiver sends back the low signal as shown with the dotted line in the above figure, thus the master acknowledges reception on the receiver side. If the low signal is not sent back, the reception will be stopped. Except for the start and stop conditions, SDA does not change at SCL = high.

[1] I2C bus (continued) 1. Receiving mode (continued) <I2C of this IC> 1) Enhances adjustment-free mechanism of the TV set thanks to DAC control 3 and 9 switches 2) Auto-increment function

• Sub address 0 *: Auto-increment mode (Data sequential transfer leads to the sequential change of sub address, so that the data is inputted.)
• Sub address 8 *: Data renewal mode (With sequential data transfer, data are inputted in the same sub address.) 3) I2C bus protocol
• Slave address
• Format (normal)
• Auto-increment mode/data renewal mode 4) As the initial state of DAC is not guaranteed, never fail to input the following data in a power on mode. "06" register: "04" "00" register: adjustment data "01" register: adjustment data "02" register: "00" "05" register: adjustment data 2. Transmission mode (read mode) I 2C bus protocol
• Slave address: 10110111 (B7H)
• Format S Slave address AW Sub address A Data 1 A Data 2 A A PData n S Slave address A Sub address A Data byte A P Start condition Acknowledge bit Write Mode: 0 Stop condition W S Slave address A Data byte A P Read Mode: 1 R

n Technical Information (continued) [1] I2C bus (continued)

• Sub address byte and data byte format Write mode (slave add.: 10110110) Read mode (slave add.: 10110111) D7 D6 D5 D4 Data byteUpper MSB Lower LSB D3 D2 D1 D0 Sub address "00" AUXselect 0: AUX1 1: AUX2 "01" "02" "05" "06" *** AUX SW 0: Off 1: On Adj.: 1 fi On L:VGA out R:VCO f H Mute: 1 fi On L: Mute R: Mute FMONO: 1 fi On L: L+R R: L+R AGC 1 fi On St/SAP 0 fi SAP (L+R)/SAP 0 fi SAP AGC adj. Input level adjustment High frequency separation adjustment Low frequency separation adjustment * = Don't care D7 D6 D5 D4 Data byte D3 D2 D1 D0 1 fi DET SAP det. 1 fi DET * = Don't care Upper MSB Lower LSB

n Technical Information (continued) [2] Noise detecting operation in SAP receiving mode MPX in Input VCA Stereo filter SAP filter Noise filter 5fH BPF 150 kHz BPF SAP det. Noise det. SAP det. SW1 a b Noise det. dbx Decoder 75 ms De-emph. dbx Decoder I2C Decoder L-R filter SAP out filter SW2 L out R out a b a b c c Matrix DC voltage comparater Pin 14 input "02" registerPin 12, pin 13 SW1 SW2 I 2C SAP det.Pin 21, pin 22 DC voltage Noise: Small "00" V 12 > V13 b c 3.5 V to 5 V SAP Noise: Large "00" V 12 < V13 a a 0 V to 0.9 V L +R

n Application Circuit Example V CC 5 V AUX2 L PE SCL SDA AUX2 R AUX1 L AUX1 R MPX in R out L out 4.7 mF 4.7 mF 4.7 mF 2.2 mF 0.1 mF 0.047 mF 180 kW 4.7 mF 0.1 mF 0.1 mF 4.7 mF 4.7 mF 4.7 mF 4.7 mF 4.7 mF 0.33 mF 0.1 mF 0.022 mF 10 mF(Ta) 3.3 mF(Ta) ZAP I2C Decoder Wide band filter Spectral filter Wide band RMS det. Spectral RMS det. Wide band expand Spectral expand dbx De-emph. (L-R)/SAP switch Offset cancel 75 ms De-emph. L+R filter Pilot cancel L-R filter SAP out filter Pilot det. L+R demod St. PLL L-R demod SAP demod Noise det. Noise filter SAP filter Input VCA SAP det. Stereo filter fH , 2fH Trap filter DAC Out SW AGC Matrix Offset cancel