AN5491 | DigiCamel IC Datasheet

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AN5491K PANASONIC | Alldatasheet

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Synchronous signal and deflection distortion correction processing IC supporting I2C bus for HD, wide television n Overview The AN5491K is a deflection processor IC for syn- chronous signal processing and screen distortion correc- tion. It synchronizes with the input signal of High-vision, wide television, NTSC, PAL and VGA by the external binary input signal of them so that a multimedia television can be realized easily. n Features

Supports the multiple-point horizontal frequency (15.7 kHz to 62.7 kHz)
Horizontal duty is controllable by external voltage.
Built-in full functions for correction (Horizontal and vertical: 16 items)
Over-current detection, shut-down and hold-down n Applications
High-vision televisions, Wide screen televisions and Projection televisions SDIP042-P-0600A Unit: mm 0.5±0.1 0.9±0.25 1.778 13.7±0.3 15.3±0.25 3° to 15° 0.96±0.25 4.76±0.25 3.3±0.25 0.3 +0.1 –0.05 36.8±0.3

42 H-AFC11H-OSC

Shut downH-duty adj. Comparator ref.H-out Comparator in Comparator out BLK out V-SAW upper V-SAW lower V-SAW in I 2L VCC SDA SCL DEF V CC VP in VS2 V-OSC Ramp Trapezoid Lock det. H-GND I 2L GND VGA

1
2
4
8
32 Corner level EW out Phase out DEF GND V-out 41 2 40 3 39 4 38 5 37 6 935 26 10 33 12 32 13 30 15 29 16 28 17 23 20 22 21 EHT-DC EHT-AC AGC H VCO H AFC2 H-POS Gain-SW Counter BF H duty H out V out V OSC V-AGC timingV-latch pulse Data latchSync. DEF DAC I2C decode VP slice HP slice H AFC1 V-BLK gen. Shut down det. X-ray det. V/I converter Phase out V-SAW correction EHT correction Ramp /AGC Lock det. EW out Trapezoid crrection Upper Latch-SW H-parabola V-LIN BOW V-SLower V-amp. Phase crrection Counter input Corner correction fH switch input Counter Counter PG Counter decode 2 2 2 V-POS POLParallel V- EHT H- EHT Trape H-WID EHT-AC

n Absolute Maximum Ratings Pin No. Description Pin No. Description

1 H-AFC1 22 V-AGC

2 H-pulse input 23 EHT-DC input

3H - V CC (6.2 V) 24 EHT-AC input

4 Shut down SW 25 · 8

5 Comparator ref. (6.5 V) 26 · 4

6 Comparator 27 VGA

7 Comparator output 28 V-output

8 BLK output 29 DEF GND

9 V-SAW slice voltage (High) 30 Phase output

10 V-SAW slice voltage (Low) 31 · 2

11 V-SAW input 32 EW output

12 I 2L VCC (5 V) 33 Corner slice voltage

13 I 2C SDA input 34 I 2L GND

14 I 2C SCL input 35 · 1

15 DEF V CC (9 V) 36 H-GND

16 V-pulse input 37 Lock det.

17 V-pulse output 38 H-output

18 V-OSC 39 H-duty

19 · 32 40 H-AFC2

20 V-ramp 41 FBP input

21 Trapezoid correction voltage 42 H-OSC

Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C. *2: The power dissipation shown is for the independent IC without a heat sink in free air at Ta = 70°C. Parameter Symbol Rating Unit Supply voltage V CC V CC1 5.6 V V CC2 10 Supply current I CC ICC1 24 mA ICC2 29 I3 14 Power dissipation *2 PD 600 mW Operating ambient temperature *1 T opr -20 to +70 °C Storage temperature *1 Tstg -55 to +150 °C

n Recommended Operating Range Parameter Symbol Range Unit Supply voltage V CC1 4.5 to 5.0 to 5.5 V V CC2 8.1 to 9.0 to 9.9 n Electrical Characteristics at Ta = 25°C Parameter Symbol Conditions Min Typ Max Unit DC characteristics Circuit current ICC1 I12 V CC1 = 5 V, VCC2 = 9 V 13.6 17.0 20.4 mA Circuit current ICC2 I15 V CC1 = 5 V, VCC2 = 9 V 16.8 21.0 25.2 mA Circuit current ICC3 I3 V CC1 = 5 V, VCC2 = 9 V, 6.0 7.5 9.0 mA V CC3 = 6.5 V Synchronizing signal processing Horizontal free-running oscillation fHO8 Pin 2: Without input, Pin 25: High61.5 62.7 63.9 kHz frequency 1 [Divide-by-8] Pins 19, 26, 31, 35: Low Horizontal free-running oscillation fHO16 Pin 2: Without input 30.8 31.4 32.0 kHz frequency 2 [Divide-by-16] Pins 19, 25, 26, 31, 35: Low Horizontal free-running oscillation fHO32 Pin 2: Without input 15.4 15.7 16.0 kHz frequency 3 [Divide-by-32] Pin 19: High Horizontal output pulse duty cycle 1tHO1 Pin 2: Without input, Pin 39: 2 V 11.7 14.0 16.6 ms [Divide-by-32] Pin 19: High Horizontal output pulse duty cycle 2tHO2 Pin 2: Without input, Pin 39: 5 V 23.9 28.5 33.7 ms [Divide-by-32] Pin 19: High Horizontal high-level output voltage VFHH DC voltage for pin 38 high-level 2.8 3.5 4.2 V Horizontal low-level output voltage VFHL DC voltage for pin 38 low-level 0 ¾ 0.3 V Horizontal output start voltage V FHS Minimum voltage of pin 3 to bec-¾ 4.2 5.0 V ome f > 10 kHz when horizontal oscillation output is 1 V[p-p] or more in divide-by-32 mode. Screen center variable range 1 t DH16 Pin 25: Low, 2.16 2.70 3.24 ms [Divide-by-16] Pins 19, 26, 31, 35: High Change amount of phase difference between H P and H-out of Data 08: [00] to [1F] Screen center variable range 2 t DH32 Pin 19: Low, 3.8 4.8 5.8 ms [Divide-by-32] Change amount of phase difference between HP and H out of Data 08: [00] to [1F] Horizontal input pulse threshold voltageV T2 Slice level of pin 2 0.9 1.5 2.1 V Over-voltage protective operation V4 Pin 4 voltage at I4 = 50 mA 0.60 0.75 0.90 V voltage

n Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit Deflection correction processing V P pulse for OSD low-level V LOSD V CC1 = 5 V, VCC2 = 9 V 0 ¾ 0.4 V V P pulse for OSD high-level V HOSD V CC1 = 5 V, VCC2 = 9 V 2.2 2.75 3.3 V EHT-AC input pin voltage V 24 Pin 24: Open 2.00 2.45 2.90 V Vertical input signal threshold voltage VTFV Pin 16: Input 0.9 1.5 2.1 V Vertical free-running oscillation fVO Pin 16: Without input 35 44 53 Hz frequency external R = 10 kW , C = 3.3 mF Typical vertical output amplitude VV V amplitude DAC: Typ. 0.88 1.10 1.32 V[p-p] Typical EW output amplitude V EW EW output amplitude for typical ver- 0.8 1.0 1.2V[p-p] tical output amplitude = 1.25 V[p-p] Phase out amplitude V PHASE Side pin parallel, DAC: Typ. - 0.1 0 0.1 V[p-p] Ramp waveform amplitude V RAMP fV = 50 Hz to 120 Hz 2.15 2.45 2.75 V[p-p] AGC input and output current I AGC 1.6 2.0 2.4 mA Service SW: ON time V 28SW 3.1 3.5 3.9 V Vertical output DC BLK pulse high-level V HBLK 4.5 5.0 5.5 V BLK pulse low-level V LBLK 0 ¾ 0.4 V Vertical output amplitude DVAMPmax V amplitude ratio between +40 +50 +60 % variable ratio (max.) typ. ﬁ max. Vertical output amplitude DVAMPmin V amplitude ratio between -40 -50 -60 % variable ratio (min.) typ. ﬁ max. Vertical output trapezoidal waveformDVTRAPmin Trapezoidal waveform correction:- 0.28- 0.38- 0.48 V correction variable amount (min.) Typ. ﬁ min. Vertical output trapezoidal waveformDVTRAPmin Trapezoidal waveform correction:+0.28 +0.38 +0.48 V correction variable amount (max.) Typ. ﬁ max. External trapezoidal waveform V 21 2.4 3.0 3.6 V center voltage Vertical output center DC level V 28 2.8 3.5 4.2 V EW output (min.) to parabolic V EWmin Parabolic amplitude: Min. - 0.1 0 0.1 V[p-p] amplitude change amplitude change to horizontal amplitude change to horizontal amplitude change to EHT-DC change Horizontal EHT: Max. EHT-AC gain: Min.

n Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit Deflection correction processing (continued) to EHT-DC change Horizontal EHT: Max. EHT-AC gain: Min. to EHT-AC change Horizontal EHT: Max. EHT-AC gain: Max. to EHT-AC change Horizontal EHT: Max. EHT-AC gain: Max. EW output parabolic DC level V 32 Typ. 2.2 2.7 3.4 V Parallelogram correction fluctuation 1DV UPH1 Parallelogram correction: +0.16 +0.26 +0.36 V (upper side) Typ. ﬁ min. Parallelogram correction fluctuation 2DV UPH2 Parallelogram correction: - 0.16 - 0.26 - 0.36 V (upper side) Typ. ﬁ max. Parallelogram correction fluctuation 3DV BPH1 Parallelogram correction: - 0.25 - 0.35 - 0.45 V (lower side) Typ. ﬁ min. Parallelogram correction fluctuation 4DV BPH2 Parallelogram correction: +0.16 +0.26 +0.36 V (lower side) Typ. ﬁ max. Bow shape correction fluctuation 1DV USD1 Bow shape correction: - 0.24 - 0.34 - 0.44 V (upper side) Typ. ﬁ min. Bow shape correction fluctuation 2DV USD2 Bow shape correction: +0.12 +0.22 +0.32 V (upper side) Typ. ﬁ max. Bow shape correction fluctuation 3DV BSD1 Bow shape correction: - 0.17 - 0.27 - 0.37 V (lower side) Typ. ﬁ min. Bow shape correction fluctuation 4DV BSD2 Bow shape correction: +0.12 +0.22 +0.32 V (lower side) Typ. ﬁ max. I2C interface SCL, SDA input threshold voltage V TH V CC1 = 5 V 1.5 ¾ 3.0 dB Sink capacity at ACK V ACK I = 3 mA in case of pull-up resistor¾¾ 0.4 V 1.6 W Maximum clock frequency f SCL 100 ¾¾ kHz

Design reference data Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter Symbol Conditions Min Typ Max Unit DC characteristics AGC pulse width tAGC ¾ 95 ¾m s Ramp discharge current I RAMP1 3.6 ¾¾ mA Ramp charge current 1 I RAMP2 f = 120 Hz, Pin 4: 5.7 V ¾ 138 ¾m A Ramp charge current 2 I RAMP3 f = 30 Hz, Pin 4: 7.5 V ¾ 32.9 ¾m A

n Electrical Characteristics at Ta = 25°C (continued)

Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter Symbol Conditions Min Typ Max Unit DC characteristics (continued) BLK output amplitude V BLK 456V Vertical output drive current I 28 -2 ¾¾ mA Vertical output amplitude fluctuationV V Difference of VCCmax - VCCmin ¾ 0.1 ¾ V with supply voltage DV CC Vertical output DC fluctuation V 28 Difference of VCCmax - VCCmin ¾ 1.0 ¾ V with supply voltage DV CC EW output amplitude fluctuation V EW Difference of VCCmax - VCCmin ¾ 0.1 ¾ V with supply voltage DV CC EW output DC fluctuation V 32 Difference of VCCmax - VCCmin ¾ 1.0 ¾ V with supply voltage DV CC Synchronizing signal processing Horizontal free-running oscillation fHO15 Pin 2: Without input, Pin 19: Low32.9 33.5 34.1 kHz frequency [Divide-by-15] Pins 25, 26, 31, 35: High Horizontal output pull-in range f HP8 Pin 2: Without input, Pin 25: High–2 000–2 600 ¾ Hz [Divide-by-8] Pins 19, 26, 31, 35: Low Comparator detection operation voltageV 6 Pin 6: Minimum voltage to become5.7 6.3 6.9 V high, Pin 5: 6.2 V Lock detection output voltage V 37 V 37 in horizontal AFC lock mode 5.7 6.3 6.9 V Lock detection charge and discharge ILOCK DC measurement in divide-by-32¾– 0.8 ¾ mA current FBP (AFC2) slice level V TFBP Minimum voltage of pin 41 at 1.5 1.9 2.3 V which AFC operates. Horizontal AFC mm DC measurement in divide-by-32¾ 37 ¾m A/ms Horizontal VCO bb Slant of b curve near f = 15.7 kHz ¾ 1.9 ¾ Hz/mV FBP allowable range 1 t FBP8 Time from H-out rise to FBP 3 ¾ 9 ms [Divide-by-8] center FBP allowable range 2 t FBP16 Time from H-out rise to FBP 4 ¾ 13 ms [Divide-by-16] center FBP allowable range 3 t FBP32 Time from H-out rise to FBP 6 ¾ 20 ms [Divide-by-32] center AFC1 reference current 1 I AFC1 Data 0C = "11" (D1, D0) ¾ 0.82 ¾ mA AFC1 reference current 2 I AFC2 Data 0C = "01" (D1, D0) ¾ 1.1 ¾ mA AFC1 reference current 3 I AFC3 Data 0C = "10" (D1, D0) ¾ 1.5 ¾ mA AFC1 reference current 4 I AFC4 Data 0C = "00" (D1, D0) ¾ 2.0 ¾ mA Horizontal output pull-in range 1 fHP16 Pin 2: Without input –1 000–1 300 ¾ Hz [Divide-by-16] Pins 19, 25, 26, 31, 35: Low Horizontal output pull-in range 2 fHP32 Pin 2: Without input –500 –650 ¾ Hz [Divide-by-32] Pin 19: High

n Electrical Characteristics at Ta = 25°C (continued)

Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter Symbol Conditions Min Typ Max Unit Deflection correction processing Vertical output S-shape variableDV SC1 Vertical S-shape: ¾- 28 ¾% ratio 1 Ratio of min. ﬁ max. Vertical output S-shape variableDV SC2 Vertical S-shape: Ratio of min.ﬁ¾ 1.5 ¾% ratio 2 max. (Change of V-out 40% to 60% point) Vertical output (upper side) DV ULIN1 Vertical linearity (upper side):¾+ 12 ¾% linearity variable ratio 1 Typ.ﬁ max. Vertical output (upper side) DV ULIN2 Vertical linearity (upper side):¾- 10 ¾% linearity variable ratio 2 Typ. ﬁ min. Vertical output (lower side) DV BLIN1 Vertical linearity (lower side):¾+ 9 ¾% linearity variable ratio 1 Typ.ﬁ max. Vertical output (lower side) DV BLIN2 Vertical linearity (lower side):¾- 11 ¾% linearity variable ratio 2 Typ. ﬁ min. Vertical output DV EDC1 EHT-DC = 5.0 V ﬁ 3.8 V ¾- 30 ¾% EHT-DC change 1 Vertical EHT: Max., EHT gain: Max. Vertical output DV EDC2 EHT-DC = 5.0 V ﬁ 6.2 V ¾+ 25 ¾% EHT-DC change 2 Vertical EHT: Max., EHT gain: Max. Vertical output DV EAC1 EHT-AC = 2.35 V ﬁ 1.35 V ¾- 12 ¾% EHT-AC change 1 EHT: Max., EHT gain: Max. Vertical output DV EAC2 EHT-AC = 2.35 V ﬁ 3.35 V ¾+ 12 ¾% EHT-AC change 2 EHT: Max., EHT gain: Max. EW output (min.) DV TRAPmin Trapezoidal SW: On, ¾- 40 ¾% to trapezoidal waveform change Trapezoidal: Typ. ﬁ min. EW output (max.) DV TRAPmax Trapezoidal SW: On, ¾+ 40 ¾% to trapezoidal waveform change Trapezoidal: Typ. ﬁ max. EW output (min.) to upper cornerDV UCmin Upper corner: Typ. ﬁ min. ¾- 45 ¾% trapezoidal waveform change Corner slice voltage: 1 V EW output (max.) to upper cornerDV UCmax Upper corner: Typ. ﬁ max. ¾+ 45 ¾% trapezoidal waveform change Corner slice voltage: 1 V EW output (min.) to lower cornerDV BCmin Lower corner: Typ. ﬁ min. ¾- 4 5 ¾% trapezoidal waveform change Corner slice voltage: 1 V EW output (max.) to lower cornerDV BCmax Lower corner: Typ. ﬁ max. ¾+ 45 ¾% trapezoidal waveform change Corner slice voltage: 1 V External trapezoidal waveform correctionDV ETR1 External trapezoidal correction:¾- 40 ¾% fluctuation 1 (Parabolic amplitude) 3 V ﬁ 2 V External trapezoidal waveform correctionDV ETR2 External trapezoidal correction:¾+ 40 ¾% fluctuation 2 (Parabolic amplitude) 3 V ﬁ 4 V

n Electrical Characteristics at Ta = 25°C (continued)

Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter Symbol Conditions Min Typ Max Unit I2C interface 3, 4, 5, 6-bit DAC DNLE L1 1LSB = 0.1 1.0 1.9 LSB/step {Data(max.) - Data(00)}/7,15,31,63 7-bit DAC DNLE (Except for 40) L2 1LSB = {Data(max.) - Data(00)}/127 0.1 1.0 1.9 LSB/step 7-bit DAC DNLE (40 only) L3 1LSB = {Data(max.) - Data(00)}/127 -1.0 1.0 2.0 LSB/step n Terminal Equivalent Circuits Pin No. Equivalent circuit Description Voltage

1 AFC1:

Horizontal frequency detection pin

Pin for adjusting the frequency of horiz- ontal input pulse and the internal refere- DC nce pulse. approx. 4.3 V
Connect a lag lead filter.

2 H-pulse in: AC

Horizontal synchronizing signal input pin

Polarity is as shown in the right figure (Negative).
Slice level is 1.5 V.
Input polarity is one polarity only (not corresponding to both polarities). 3V CC :D C Horizontal system power supply (6.5 V) pin 6.5 V
Connect an external zener

4 Shut down: DC

Control pin for shut-down Normal: GND

Horizontal output stops (GND) if a voltage 1 V BE and over (more than approx. 0.75 V) is applied to the pin. 5.3 V 6.5 V 3.15 V 4.3 V 27 kW 9 V 3 V 1.5 V 100 kW 1 kW 12 V 330 W

6.5 V28 kW 28 kW

1.5 V

n Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage 5 Comparator ref.: DC Reference voltage input pin for comparator

Attach zener diode externally (approx. 6.2 V) (Usable as reference voltage for hold-down)

6 Comparator: DC

Input pin for comparator detection

(Usable as pin for hold-down detection)

7 Comparator out: DC

Comparator detection output pin Normally:

Connect pull-up resistors outside the IC. High (usable as hold-down control pin) Note) Use under 400 mA or less.

8 BLK out: DC

Blanking pulse output pin At BLK: High

Normally: Low At BLK: High (5 V)

9 Upper side slice: DC

Upper side slice voltage input pin for BLK pulse generation 6.5 V 1 kW 6.5 V 1 kW1 kW 9 V 25 kW 20 kW 48.3 kW 20 kW 9 V 99.8 kW 9 V 20 kW

145 W145 W

n Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage

10 Lower side slice: DC

Lower side slice voltage input pin for BLK Pulse generation

11 V-SAW in: AC

V-SAW input pin for BLK pulse generation 12 ¾ V CC :D C Power supply (5 V) pin for DAC/I2L5 V

Connect a pass capacitor (0.01 mF) between pin 12 and GND (pin 19).

13 SDA:

14 SCL:

15 ¾ V CC :D C Pin for deflection system power supply (9 V) 9 V

Connect a pass capacitor between the pin and GND. 9 V 20 kW 145 W Lower side BLK 20 kW 145 W 25 mA 9 V 1 kW 20 mA 5 V GND 5 V 1 kW 20 mA 5 V GND 5 V

n Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage

16 V-pulse in: AC

Vertical sync. signal input pin (Pulse)

Polarity is as shown in the right figure (Negative)
Slice level is 1.5 V.
Input polarity is only one polarity (Not correspond to both polarities)

17 V-pulse out: AC

Vertical sync. signal output pin (Pulse)

If vertical sync. signal input is present: Outputs the pulse synchronized with input V. Not present: Outputs free-running V pulse. (Usable for microcomputer OSD control)

18 V-OSC: AC

Connect CR.
Free-running oscillation when there is no input. 19 · 32: DC Horizontal free-running oscillation frequency control pin
To be used by high/low control.
Input is controlled by open collector output.20 V-ramp pin: AC
The pin for generating reference V sawtooth waveform for IC inside.
Connect an 0.22 mF mylar capacitor. 9 V 1.5 V 30 kW 290 W 290 W 25 mA V rate 1.5 V 0 V 9 V 55 kW 1 kW 5 V 50 mA 9 V 36 kW 5.8 V

3.1 VV rate

2.5 V 0 V 6.5V 150 kW 30 kW 30 kW 30 kW 1kW 2.5V 2.5 V

0 VV rate

n Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage

21 External trapezoidal waveform: DC

The pin for controlling trapezoidal wavefo- 2 V to 4 V rm compensation from outside.

Used by linking to V-position shift (at AC co- upling). typ. 3.0 V

22 V-AGC: DC

AGC pin to make a vertical output amplit- ude constant.
Connect 3.3 mF tantalum capacitor.

23 EHT-DC: DC

Pin for extremely high-tension compensation (EHT)

DC-coupled to pin. Operating range: 3.8 V to 6.2 V

24 EHT-AC AC

Pin for extremely high-tension compensation

AC-coupled to pin.

2.35 V in an

Operating range: 1.35 V to 3.35 V 25 · 8: DC Horizontal free-running oscillation frequency control pin

To be used by high/low control.
Input is controlled by open collector output. 145 W 25 mA 9 V 145 W 500 W 500 W 9 V 9 V 3.8 V 5.45 V 20 kW 145 W 25 mA 9 V 145 W 25 mA 20 kW 20 kW 6.5 V 150 kW 20 kW 20 kW

n Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage 26 · 4: DC Horizontal free-running oscillation frequency control pin

To be used by high/low control.
Input is controlled by open collector output.

27 V-FB: DC

Forced progressive mode pin

To be used by high/low control.
At high: Multi-point mode At low: Progressive mode

28 V-out: AC

V sawtooth waveform output pin

Typ. 1.25 V[p-p] 29 ¾ GND: DC GND pin for deflection-system circuit (9 V) GND

30 Phase out: AC

Pin for side pin (Bow shape) correction, para- llelogram correction and control pulse output. DC

Connect to H-AFC2 pin via 1 mF (non- approx. 3.7 V polarity) capacitor. Max. 300 mV[p-p] 6.5 V 150 kW 20 kW 20 kW 6.5 V 60 kW 9 V 300 W 100 W 290 W
5
5 0 V 9 V 9 V 290 W 290 W

n Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage 31 · 2: DC Horizontal free-running oscillation frequency control pin

To be used by high/low control.
Input is controlled by open collector output.

32 EW out: AC

Parabolic waveform output pin

33 Corner slice: DC

The voltage to set a slice point of upper and lower corner correction.

The correction gain can be controlled inde- Externally set pendently by I 2C bus for upper and lower, at 0 VDC to respectively. 1.25 VDC

34 GND: GND pin for 5 V system (I 2C/I2L) DC

35 · 1: DC Horizontal free-running oscillation frequency control pin

To be used by high/low control. 36 ¾ GND: GND pin for 6.5 V system DC (Horizontal system) GND 37 Lock det.: DC Horizontal lock detection pin
Connect 0.022 mF and 1 MW between the At lock mode: pin and GND. 6 V At unlocked mode: GND 6.5 V 150 kW 20 kW 20 kW 9 V 500 W 300 W 40 kW 1.5 V 10 kW 9 V 9 V 50 mA 50 mA 6.5 V 10 kW 150 kW 6.5 V 820 mA 880 mA 200 W

n Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description Voltage

38 H-out: AC

The length of high-period can be adjusted by a separate pin.

39 H-duty: DC

Pin for controlling the length of high-period 1 V to 5 V of horizontal output pulse.

Apply DC voltage from the outside.

40 AFC2: DC

Horizontal phase detection pin 1.5 V to 4.5 V

Pin for controlling phase difference bet- ween horizontal output pulse and FBP.
Phase out waveform is also connected to this pin via capacitor.
Connect 0.015 mF between this pin and GND.

41 FBP input pin: AC

Slices at 1.9 V (in the IC) and then uses as AFC2 control pulse.
Do not input any signal under GND insi- de the IC.

42 H-OSC: AC

Reference oscillation pin (500 kHz)

Connect CERALOCK (CSB500F48), and temperature guaranteed (N750) 220 pF capacitor in series between this pin and GND. 6.5 V 3.2 mA 40 kW 15 kW H rate 2.9 V GND 6.5 V 10 kW 124 kW 124 kW 6.5 V 3.9 V 1.9 V 6.5 V 2.7 kW 100 kW 50 mA 1.9 V GND 1.9 V 6.5 V 300 W 270 W 270 W

3.0 V10 kW100 mA

0.5 V[p-p]

2.25 V

n Application Circuit Example Shut downH-duty adj. Comparator ref.H-out Comparator in Comparator out BLK out V-SAW upper V-SAW lower V-SAW in I 2L VCC SDA SCL DEF V CC VP in VS2 V-OSC Ramp Trapezoid Lock det. H-GND I 2L GND VGA

1
2
4
8
32 Corner level EW out Phase out DEF GND V-out 41 2 40 3 39 4 38 5 37 6 36 7 935 26 10 33 12 32 13 30 15 29 16 28 17 23 20 22 21 EHT DC EHT AC AGC

1 M W

6.5V 6.5 V 5 VV 10 kW 620 W 330 W 10 kW 3.3 mF 0.22 mF 0.033 mF 0.22 mF 3.3 mF 1 mF 220 pF 22 mF*1 *1: Horizontal oscillator TAFCSB500F48 [Murata Manufacturing Co. Ltd.] 4.7 kW 4.7 kW 9 V 9 V 9 V 6.5 V 6.5 V 12 V

Product Information

AN5491 specifications and overview.

Summary

Synchronous signal and deflection distortion correction processing IC supporting I2C bus for HD, wide television

Description

Synchronous signal and deflection distortion correction processing IC supporting I2C bus for HD, wide television

Source title AN5491 Datasheet(PDF) - Panasonic Semiconductor

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