AN5165K

AN5165K PANASONIC | Alldatasheet

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Technical content

A Single Chip IC for NTSC Color-TV n Overview The AN5165K is an IC in which all of the NTSC system color television signal processing circuits are in- tegrated on a single chip. The rationalization of set pro- duction line can be realized by this IC incorporating I bus interface. n Features

• Built-in video IF circuit, sound IF circuit, video signal processing circuit, color signal processing circuit, de- flection correction circuit and sync. signal processing circuit
• Built-in I 2C bus interface n Applications
• TVs 26 27 47.7±0.3 13.7±0.3 (0.7) 3.85±0.3 (3.3) 1.778 0.5±0.1 1.0±0.25 Unit: mm SDIP052-P-0600A

Ext.Audio SIF In IF AGC Video Out AFT Out Int.V DET Out APC VCO1 VCO2 IF 9 V BLDET V Sync. Y In V Clamp H Sync. V/C/J/5 V C In VCJ GND FBP In 6.3 V AFC1 HOSC X-ray H Out CW Out V Out1 1

26 Decoupling

Ext.Video Audio Out APC RF AGC Out GND (IF) IF 5 V 9 V BLK In (SCP) SCL SDA ACL/NECK GND (RGB) Lock DET B G R V/C/J 9 V B In G In R In Y S&Y M APC Chroma VCO X-ray Gain Control HVCO Ver. Out Ver. CountDown to Video RGB VBLK CCP (Hosc4) Trig1 Trig2 A Trig P.EQP H Center 2fH 32fH H.EQP HBLK Killer Off SW 7-bit 5-bit BPF SW 7-bit 3-bit On/Off SW7-bit ABL SW DC 8-bit g On/Off SW 6-bit 4-bit DC 7-bit 9-bit 5-bit 8-bit Cut Off Cut Off B SW Cut Off R SW 7-bit Drive RGB Limit3-bit Hor. CountDown ACC DET Sharpness CV Clamp ACC1 APC Tint C Filter Y S&Y M Hor. Sync. Sep. Ver. Sync. Sep. HBLK AFC1 Lock DET AFC2 CW Out Killer L.P.F. Y .N.R B.P.F.2 B.P.F.1 B.G.P DL Trap VCO PT L.P.F. APC VCO CTRL VA SW IF AGC IF DET RF AGC VIF Amp. V AMP NI SIF AFT VSW Cut off DriveVCO Y Contrast Y Clamp Bright Black Expamsion g ACC2 Contrast Color DEM SW DAC SW DAC DACSW DAC SW DAC SW V SW DAC DAC DAC DAC SW DACDAC DAC SW DAC SW DAC SW S.SW to Video RAMP PLL DEMP VOL ASW to Chroma H Out2 H Out1 Hosc2 H Pluse Hosc1 n Block Diagram

Pin No. Description

28 SIF Input/White Expand-Level

29 IF AGC Filter

30 Video Output

31 AFT Output

32 Internal Video Input

33 VIF Detect Output

34 VIF APC Filter

35 VIF VCO (1)

36 VIF VCO (2)

37 V CC1-2 9 V

38 Black Detect

39 Y/Ver. Sync. Input 40 Ver. Sync. Clamp 41 Hor. Sync. Input

42 V CC2-2 5 V (Chroma/jungle/DAC)

43 Chroma Input/Black Expansion Start

44 GND (Video/Chroma/Jungle)

45 FBP Input

46 V CC3 6.2 V

47 AFC1 Filter

48 Hor. VCO (32 f H )

49 X-ray Protection Input

50 Hor. Pulse Output

51 CW Output/Spot KILLER Off Input/

52 Ver. Pulse Output Pin No. Description 1 Chroma VCO (3.58 MHz)

2 Chroma APC Filter

3Y S & YM Input

4 External R Input

5 External G Input

6 External B Input

7V CC1-1 9 V (VCJ)

8 R Output

9 G Output

10 B Output

11 Hor. Lock Detect

12 GND (RGB/I 2C/ DAC)

13 ACL/NECK Protect

14 SDA

15 SCL

16 BLK Pulse Input/H SYNC2 Output

17 White Detect

18 V CC2-1 5 V (VIF/SIF)

19 VIF Input (1)

20 VIF Input (2)

21 GND (VIF/SIF)

22 RF AGC Output

23 SIF APC Filter

24 Audio Output

25 External Video Input

26 DC Decoupling Filter

27 External Audio Input

Parameter Symbol Rating Unit Supply voltage V CC V CC1 (7·37) 10.5 V V CC2 (18·42) 6.0 V CC3 (46) 6.5 Supply current I CC I7+37 117 mA I18+42 68 I46 6.3 n Absolute Maximum Ratings

Parameter Symbol Conditions Min Typ Max Unit Power supply Supply current 1 I 7+I37 Current at V7 = 9 V, current at 68 85 100.5 mA V 37 = 9 V Supply current 2 I 18+I42 Current at V18 = 5 V, current at 38 48 57 mA V 42 = 5 V Supply current 3 I 46 Current, when V46 = 6.2 V 2 5 6 mA Supply current 4 I 46 Current at V46 = 6.2 V. However 5 7 9 mA all other power supplies are off state VIF circuit (Typical input fP = 45.75 MHz, VIN = 90 dBm) Data 0D = 88 Video detection output (max.) V POmax Data 0D = F8 2.15 2.6 3.3 V[p-p] Video detection output (min.) V POmin Data 0D = 08 1.1 1.6 2.0 V[p-p] Video detection output f characteristicsfPC Frequency of output -3 dB for 1 MHz 5.5 8 12 MHz Synchronous peak value voltage V SP Voltage in VPO measurement 1.6 2.0 2.4 V APC pull-in range (Hu) f PPHU High band side pull-in range 1.0 1.5 ¾ MHz (Difference from fP = 45.75 MHz) APC pull-in range (Lu) f PPLU Low band side pull-in range ¾- 1.5 -1.0 MHz (Difference from fP = 45.75 MHz) RF AGC delay point adjustment DV RFDP Input to become delay point 75 ¾ 95 dBm range (V 22 = approx. 6.5 V), when Data 0C = 00 to 7F RF AGC maximum sink current I RFmax Maximum current IC can sink when 1.5 3.0 ¾ mA pin 22 is low Parameter Symbol Rating Unit Power dissipation *2 PD 1 481 mW Operating ambient temperature *1 T opr -20 to +70 °C Storage temperature *1 Tstg -55 to +150 °C n Absolute Maximum Ratings (continued) Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25°C. *2: The power dissipation shown is the value for Ta = 70°C n Recommended Operating Range Parameter Symbol Range Unit Supply voltage V CC1 8.1 to 9.9 V V CC2 4.5 to 5.5 V CC3 6.05 to 6.35 n Electrical Characteristics at Ta = 25°C

Parameter Symbol Conditions Min Typ Max Unit VIF Circuit (continued) (Typical input fP = 45.75 MHz, VIN = 90 dBm) RF AGC minimum sink current I RFmin Leak current of IC, when pin 22 is-50 0 50 mA high AFT discrimination sensitivity mAFT Df = –25 kHz 40 57 75 mV/kHz AFT center voltage V AFT V 31 without VIN 4.0 4.5 5.0 V AFT maximum output voltage V AFTmax V 31 at f = fP-500 kHz 7.8 8.1 8.7 V AFT minimum output voltage V AFTmin V 31 at f = fP+500 kHz 0.3 0.8 1.0 V SIF circuit (Typical input fS = 4.5 MHz, fM = 400 Hz, VIN = 90 dBm) Audio detection output V SO Df = –25 kHz, 0A = 10 250 350 450 mV[rms] Audio detection output (max.) V SOmax Data 0A = 1F 300 390 480 mV[rms] Audio detection output (min.) V SOmin Data 0A = 00 150 256 350 mV[rms] SIF pull-in range f SP 3.3 ¾ 5.7 MHz AV SW circuit Video SW voltage gain G VSW f = 1 MHz, VIN = 1 V[p-p] 6.2 7.2 8.2 dB Video SW frequency characteristics fVSW Frequency of output -3 dB from 1 MHz 10 ¾¾ MHz Audio SW voltage gain G ASW Data 0 F-D5 = 1 (external) -3 -11d B f = 400 Hz, VIN = 1 V[p-p] Video signal processing circuit (In the following test conditions, the measurements are made withinput: 2.0 V[p-p] (VWB = 1.43 V[0-p]stair-step) at GOUT .) Contrast variable range Y Cmax/min 03 = 7F 19 22 26 dB 03 = 00 Video frequency characteristics fYC Data 0F-D7 = 0 (Trap Off) 6.0 8.0 10.0 MHz Data 04 = 00 (Sharpness) Frequency to become -3 dB from f = 0.5 MHz Sharpness variable range Y Smax/min 04 = 3F f = 3.8 MHz 7 10.5 14 dB 04 = 00 Data 0F - D7 = 0 Pedestal level (typical) V PED Data 02 = 80 (typ.) (Brightness) 2.4 3.0 3.6 V Pedestal variable width DV PED Difference between Data 02 = 00 2.2 2.6 3.0 V and FF Brightness control sensitivity DV BRT Average amount of change per 1 step, 9.5 12.5 15.5 mV/Step when Data 02 = 60 and A0 Blanking level V YBL DC voltage of blanking pulse 0.9 1.4 1.9 V n Electrical Characteristics at Ta = 25°C (continued)

n Electrical Characteristics at Ta = 25°C (continued) Parameter Symbol Conditions Min Typ Max Unit Video signal processing circuit (continued) (In the following test conditions, the measurements are made with input: 2.0 V[p-p] (VWB = 1.43 V[0-p] stair-step) at GOUT .) Video input clamp current I YCLP DC measurement: Sink current inside IC51 0 1 5 mA ACL start point V ACL V 13 voltage at which output amplitude 3.5 4.0 4.5 V becomes 90% when ACL pin (V13) is being decreased from 5 V. Color signal processing circuit (In the following test conditions, burst = 300 mV[p-p], reference is BOUT ) Color difference output (typ.) V CO Input: Color bar 2.8 3.5 4.2 V[p-p] Data 00 = 40 (typ.), 03 = 40 (typ.) Color difference output (max.) VCOmax Data 00 = 7 F one side amplitude 2.3 3.4 ¾ V[0-p] Data 03 = 40 Color difference output (min.) VCOmin Data 00 = 00, Data 03 = 40 0 ¾ 100 mV[p-p] Contrast variable range C Cmax/min 03 = FF Data 00 = 40 15 20 25 dB 03 = 00 ACC characteristics 1 ACC1 Burst 300 mV[p-p] fi 600 mV[p-p] 0.8 1.0 1.2 Time Input: Color bar ACC characteristics 2 ACC2 Burst 300 mV[p-p]fi 60 mV[p-p] 0.7 1.0 1.2 Time Input: Color bar Tint center Dq C Difference (Tint) between Data 01 = 40 -13 0 13 STEP and that of tint adjusted at center Tint variable range 1 Dq 1 Data 01 = 7F 30 45 60 deg Tint variable range 2 Dq 2 Data 01 = 00 -60 -45 -30 deg Demodulation output ratio (R) R/B Input: Rainbow 0.81 0.95 1.09 Time Demodulation output ratio (G) G/B Input: Rainbow 0.3 0.36 0.42 Time Demodulation output angle (R) — R Input: Rainbow 92 104 116 deg Demodulation output angle (G) — G Input: Rainbow 223 235 237 deg APC pull-in range (H) f CPH 450 900 ¾ Hz APC pull-in range (L) f CPL ¾- 900 -450 Hz RGB processing circuit Pedestal difference voltage DV IPL Difference voltage of RGB out pedestal- 0.3 ¾ 0.3 V Brightness voltage tracking DTBL Ratio of R, G, B out fluctuation level 0.9 1.0 1.1 Time for Data 02 (Bright) 02 = 40 to C0 Video voltage gain relative ratioDG YC Output ratio of R, B out to GOUT 0.8 1.0 1.2 Time Video voltage gain tracking DTCONT Gain ratio of R, G, B out for Data 0.9 1.0 1.1 Time/ 03 (Contrast) 03 = 20 to 60 Time Drive adjustment range G DV AC change amount of R, B out between 5.9 7.1 8.3 dB drive adjustment max. and min.

Parameter Symbol Conditions Min Typ Max Unit RGB processing circuit (continued) Cutoff adjustment range V CUTOFF DC change amount of R, G, B out 1.8 2.4 3.0 V between drive adjustment max. and min. Y S threshold voltage V YS Minimum DC voltage at which YS 2.7 3.1 3.6 V turns on Y M threshold voltage V YM Minimum DC voltage at which YM 0.7 1.0 1.3 V turns on Y M operating voltage gain DG YM Y M on/off gain difference -12 -9 -6d B External RGB pedestal voltage V EPL Y S is on 2.1 2.7 3.3 V External RGB pedestal differenceDV EPL Y S is on, R-G, G-B -250 ¾ 250 mV voltage Internal/external pedestal differenceDV PL/IE Internal-external -100 200 500 mV voltage External RGB output voltage V ERGB Input 3 V[p-p], contrast 03 =7 F 1.2 1.7 2.2 V[0-p] External RGB output differenceDV ERGB Input 3 V[p-p], contrast 03 = 7F - 0.6 0 0.6 V voltage External RGB contrast variable range ECmax/min 03 = 7F 5 8 11 dB 03 = 00 External RGB frequency characteristicsfRGBC Input 0.2 V[p-p], DC = 1 V 8 12 ¾ MHz Synchronizing signal processing circuit Horizontal free-running oscillation fHO Without sync. signal input 15.4 15.75 16 kHz frequency Horizontal pull-in range f HP Difference from fH = 15.75 kHz –500 –650 ¾ Hz Vertical free-running oscillation fVO-N Without sync. signal input 58 60 62 Hz frequency Vertical output pulse width tVO 5.5 6.5 7.5 1/f H Picture center variable range DTHC Change amount of phase difference 5.9 7.3 9.1 ms between HSYNC and HOUT Data from 0E: 00 to 1F I2C interface SCL, SDA signal input high level VIHI 3.1 ¾ 5.0 V SCL, SDA signal input low level VILO 0 ¾ 0.9 V Allowable maximum input frequency fImax 100 ¾¾ kbit/s n Electrical Characteristics at Ta = 25°C (continued)

• Design reference data Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter Symbol Conditions Min Typ Max Unit VIF Circuit (Typical input fP = 45.75 MHz, VIN = 90 dBm) Input sensitivity V PS Input level to become VPO = -3 dB ¾ 52 60 dB m

Parameter Symbol Conditions Min Typ Max Unit VIF circuit (continued) (Typical input fP = 45.75 MHz, VIN = 90 dBm) Maximum allowable input V Pmax Input level to become VPO = +1 dB 104 110 ¾ dB m SN ratio SN P 50 53 ¾ dB Differential gain DG P 035% Differential phase DP P 0 3 5 deg Black noise detection level DV BN Difference from sync. peak value-55 -45 -35 IRE Black noise clamp level DV BNC Difference from sync. peak value 35 45 55 IRE RF AGC operation sensitivity G RF Input level difference to become 0.5 1.5 3.0 dB V 22 = 1 Vfi 7 V VCO switch on drift DfPD Frequency drift from 5 seconds ¾ 70 ¾ kHz after SW On to 5 mins. after Intermodulation IM V FC -V FP = -2 dB, VFS-V FP = -12 dB 46 52 ¾ dB RF AGC adjustment sensitivity S RF Average amount of change of output 1.0 1.7 2.5 V/Step voltage V22 for Data 1Step AFT offset adjustment sensitivity SAFT Average amount of change of output0.15 0.2 0.25 V/Step voltage V31 for Data 1Step Video detection output fluctuationDV P/V V CC = –10% ¾– 10 –15 % with VCC Video detection output-temperatureDV P/T Ta = -20°C to +70°C ¾– 5 –10 % characteristics Input resistance (pin 19, 20) R I19,20 f = 45.75 MHz ¾ 1.2 ¾ kW Input capacitance (pin 19, 20) CI19,20 f = 45.75 MHz ¾ 4.0 ¾ pF Sound IF output level V SIF fS = 45.75 MHz-4.50 MHz, 94 100 106 dBm P/S = 20 dB RF AGC delay point DV DP/T Ta = -20°C to +70°C0 3 5 d B -temperature characteristics VCO free-running frequency DfP/T Ta = -20°C to +70°C ¾ 300 ¾ kHz -temperature characteristics AFT center frequency DfAFT/T Ta = -20°C to +70°C ¾ 300 ¾ kHz -temperature characteristics Input frequency at which AFT output voltage becomes 4.5 V VCO free-run adjustment V AFTADJ AFT center voltage adjustment ¾ 4.5 ¾ V VCO free-running frequency 1 DfP1 Dispersion without VIN. -300 0 300 kHz V 29 (IF AGC) = 0 V (Difference from 45.75 MHz is measured) n Electrical Characteristics at Ta = 25°C (continued)

• Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.

Parameter Symbol Conditions Min Typ Max Unit VIF circuit (continued) (Typical input fP = 45.75 MHz, VIN = 90 dBm) VCO free-running frequency 2 DfP2 Dispersion without VIN. -300 0 300 kHz V 29 (IF AGC) = 0 V (Difference from 58.75 MHz is measured) APC pull-in range (Hj) f PPHJ High band side pull-in range 1.0 1.5 ¾ MHz (Difference from fP = 58.75 MHz) APC pull-in range (Lj) f PPLJ Low band side pull-in range ¾- 1.5 -1.0 MHz (Difference from fP = 58.75 MHz) Detection output resistance R O33 DC measurement 70 120 170 W SIF circuit (Typical input fS = 4.5 MHz, fM = 400 Hz, VIN = 90 dBm) Input limiting level V LIM Input level to become VSOP = -3 dB ¾ 44 50 dB m AM rejection ratio AMR AM = 30% 60 70 ¾ dB Total harmonic distortion THD Df = –50 kHz 0 0.3 0.5 % SN ratio SN A 50 55 ¾ dB Audio detection output linearityDV SOP Ratio of Df = –50 kHz to 5 6 7 dB Df = –25 kHz Audio output fluctuation with VCC DV S/V V CC = –10% ¾– 3 –6% Audio output-temperature DV S/T Ta = -20°C to +70°C ¾– 5 –10 % characteristics Audio output-frequency f SOP1 APC pin C = 100 pF 100 ¾¾ kHz characteristics 1 Audio output-frequency f SOP2 APC pin C = 5600 pF ¾ 2.2 ¾ kHz characteristics 2 AV SW circuit Video SW crosstalk CT VSW f = 1 MHz, VIN = 1 V[p-p], ¾- 60 -50 dB Insidefi Outside, Outsidefi Inside Video SW external input terminal V25 DC measurement 1.3 1.6 1.9 V voltage Video SW internal input terminal V 32 DC measurement 1.3 1.6 1.9 V voltage Video SW internal output DC voltage V30I DC measurement Data 04-D6 = 0 3.4 4.2 5.0 V Video SW external output DC voltage V30E DC measurement Data 0F-D5 = 1 3.4 4.2 5.0 V Video SW input resistance R I25, 32 DC measurement ¾ 524 ¾W Video SW output resistance R O30 DC measurement 20 50 100 W n Electrical Characteristics at Ta = 25°C (continued)

• Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.

Parameter Symbol Conditions Min Typ Max Unit AV SW circuit (continued) Audio SW crosstalk CT AIE fS = 4.5 MHz, fM = 400 Hz, ¾- 73 -67 dB (Internalfi External) No external input Audio SW crosstalk CT AEI fS = 4.5 MHz, fM = 0 Hz, External ¾- 73 -67 dB (Externalfi Internal) f = 400 Hz, VIN = 600 mV[rms] Audio SW input terminal voltage V27 DC measurement 3.7 4.2 4.7 V Audio SW internal output DC voltage V24I DC measurement 3.7 4.2 4.7 V Audio SW external output DC voltage V24E DC measurement 3.7 4.2 4.7 V Audio SW internal/external DC DV 24 DC measurement -300 0 300 mV difference voltage Audio SW input resistance R I27 DC measurement 61 72 83 k W Audio SW output resistance R O24 DC measurement 200 400 600 W Video signal processing circuit (In the following test conditions, the measurements are made with input 2.0 V[p-p] (VWB = 1.43 V[0-p]) GOUT ) Y signal delay time 1 T DL1 Phase difference from Y-input 620 690 760 ns (For both trap on/off) Y signal delay time 2 T DL2 Phase difference from Y-input ¾ 200 ¾ ns (Trap through) Black level extension 1 V BL1 Input: Total black, difference between-100 0 100 mV pin 38 of 9 V and open (With RC filter) Black level extension 2 V BL2 Input: Total black, pin 38 GND and 700 900 1 300 mV black slice potential V43 = 2.5 V Black level extension 3 V BL3 Voltage difference between pin 38 400 600 800 mV open and 9V. Black slice potential V 43 = 2.5 V Contrast variation with sharpness DVCS Y OUT output level difference between-300 0 300 mV sharpness max. and min. Contrast variation with sharpness DVBS Pedestal level DC difference between-250 0 250 mV sharpness max. and min. Input dynamic range V Imax Contrast 03 = 40 2.8 ¾¾ V[p-p] Y signal SN ratio SN Y Contrast 03 = 7F 51 56 ¾ dB Black level extension start point VBLS Start point when V43 = 4.5 V 50 57 64 IRE Trap on/off through-gain difference DGTRAP Trap on/off/through -10 1d B Trap frequency error Df TRAP Trap center frequency at chroma-70 0 70 kHz input 3.58 MHz Trap attenuation amount Att TRAP 3.58 MHz component attenuation 26 30 ¾ dB amount at chroma input 3.58 MHz n Electrical Characteristics at Ta = 25°C (continued)

• Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.

Parameter Symbol Conditions Min Typ Max Unit Video Signal Processing Circuit (continued) (In the following test conditions, the measurements are made with input 2.0 V[p-p] (VWB = 1.43 V[0-p]) GOUT ) Trap automatic adjustment range fTRAP VCO frequency of DfTRAP £ 70 kHz 3 ¾ 4 MHz Video output fluctuation with VCC DV Y/V V CC1 = 9 V (allowance: –10%) 0 100 250 mV/V Video output-temperature characteristicsDV Y/T Ta = -20°C to +70°C0 5 1 0 % YNR operation I SN YNR S/N, when YNR: min.fi max. and ¾- 4 ¾ dB sharpness max. YNR operation II SN YNR Sharpness max., YNR: max. ¾- 1.5 ¾ dB (IFAGC) S/N at IF AGC 2 Vfi 4 V Pedestal level fluctuation White gradation correction 1 g1 White detection pin V17 = 4.5 V 120 125 130 % Difference of amplitude between G OUT gamma on/off White gradation correction 2 g2 White detection pin V17 = 2.0 V 70 75 80 % Difference of amplitude between G OUT gamma on/off Neck protector threshold voltage VNP 0.3 0.5 1.0 V DC restoration ratio T DC APL 10% to 90% 90 100 110 % TDC = DAC -D DC · 100DAC Color signal processing circuit (Burst 300 mV[p-p], reference is BOUT ) Demodulation output residual carrier VCAR fSC level of pin 8, 9, 10 0 ¾ 50 mV[p-p] VCO free running frequency f CN Difference from f = 3.579545 MHz -300 0 300 Hz fCO fluctuation with VCC DV C/V V CC1 = 9 V (allowance: –10%) -300 0 300 Hz Static phase error Dq N Tint shift at ¾ 13 deg/100 Hz DfC = -300 to +300 Hz change Demodulation output bandwidth f CC Band to become -3 dB 400 600 800 kHz Demodulation output fluctuationDV C/V V CC1 = 9 V (allowance: –10%) ¾– 4 ¾ % with VCC Demodulation output DV C/T Ta = -20°C to +70°C ¾– 10 –20 % -temperature characteristics Brightness variation with color VBC Pedestal level DC difference between-250 0 250 mV color max. and min. Brightness variation differenceDV BC R, G, B Out variation voltage 0 ¾ 20 mV voltage with color difference n Electrical Characteristics at Ta = 25°C (continued)

• Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.

Parameter Symbol Conditions Min Typ Max Unit Color signal processing circuit (continued) (Burst 300 mV[p-p], reference is BOUT ) Color killer allowance 1 V KILL1 0 dB = 300 mV[p-p], 00-D7 = 0 -53 -46 -39 dB Color killer allowance 2 V KILL2 0 dB = 300 mV[p-p], 00-D7 = 1 -50 -43 -36 dB characteristics -3 dB from 3.58 MHz RGB processing circuit (C-Y)/Y R C/Y Color bar input, BOUT 0.9 1.2 1.5 V[0-p]/ Contrast typ. color Data 00 = 60 V[p-p] (C-Y), Y delay difference DTC/Y Color bar input, BOUT -100 0 100 ns Phase of greenfi magenta Y S changeover speed f YS fYS , when external input is 3 V, 7 11 ¾ MHz output level -3 dB External RGB input dynamic range VDEXT Contrast max. Data 03 = 7F 6.5 7.0 ¾ V[0-p] Internal/external crosstalk CT RGB Leakage when f = 1 MHz, 1 V[p-p],¾- 60 -50 dB Y S = 5 V Spot killer operation V SPK V 9 at which spot killer turns on by 7.3 7.7 8.0 V decreasing V9 from 9 V Brightness variation with contrast VBAC Pedestal level DC difference between-250 0 250 mV contrast max. and min. Brightness variation difference DVBAC R, G, B Out variation voltage 0 ¾ 20 mV voltage with contrast difference Color /B&W DC difference voltage DVCBW Pedestal level voltage difference-60 0 60 mV between with and without burst signal Pedestal level fluctuation with VCC DV PL/V V CC1 = 9 V (allowance: –10%) 0 200 400 mV/V Pedestal level-temperature characteristicsDV PL/T Ta = -20°C to +70°C ¾- 0.6 ¾ mV/ °C Pedestal level difference voltage DVPD/V V CC1 = 9 V (allowance: –10%) ¾ 0 ¾ mV/V fluctuation with VCC R -G, B-G External RGB output blanking voltage VBLK Burst input only 0.8 1.3 1.8 V RGB limiter control range 1 V BEAM1 Input 2 V[p-p], contrast max. 6.4 6.7 7.0 V RGB limiter 0E = 70 RGB limiter control range 2 V BEAM2 Input 2 V[p-p], contrast max. 5.6 6.0 6.4 V RGB limiter 0E = F0 n Electrical Characteristics at Ta = 25°C (continued)

• Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.

Parameter Symbol Conditions Min Typ Max Unit Synchronizing signal processing circuit Horizontal output start voltage VfHS Minimum V 46, when H osc. output is 3.9 4.4 4.9 V

1 V[p-p] or more and fO becomes >10 kHz

Lock detection output voltage 1 VLD1 V 11, when horizontal AFC is locked 3.8 4.3 4.8 V Lock detection output voltage 2 VLD2 V 11, when horizontal AFC is unlocked.00 . 1 0 . 5V Lock detection charge and discharge ILD DC measurement –0.5 –0.7 –1.1 mA current EBP (BLK) slice level V FBP Minimum voltage of pin 45, when 0.3 0.66 1.0 V blanking is applied to RGB output EBP (AFC2) slice level V FBPH Minimum voltage of pin 45, when 1.45 1.85 2.25 V AFC2 operates Horizontal AFC mm H DC measurement 26 33 40 mA/ms Horizontal VCO bb H b curve gradient near f = 15.75 kHz 1.4 1.8 2.2 Hz/mV Burst gate pulse position P BGP Delay from HSYNC rise 0.2 0.4 0.6 ms Burst gate pulse width W BGPN 2.5 3.0 3.5 ms V blanking pulse width W VN Pulse width, when fH = 15.75 kHz 1.04 1.14 1.24 ms EBP allowable range T FBP Time from HOUT rise to FBP center 12 ¾ 19 ms Overvoltage protective operation VXRAY Dispersion from the minimum voltage-60 ¾ 60 mV voltage at which H osc. comes to be out of synchronization Black-out operation voltage V BLOUT Difference voltage from hold-down 10 110 160 mV to black out H SYNC2 output level V SCP H SYNC2 output DC level 8.0 8.2 8.4 V H SYNC2 output width W SCP H SYNC2 output pulse width ¾ 2 ¾m s H SYNC2 output position P SCP The period of time from HSYNC ¾ 3 ¾m s center to HSYNC2 rise Horizontal output pulse duty cycle tHO Upward going pulse duty cycle 32 38 44 % Horizontal output voltage (high) V50H High level DC voltage 2.8 3.1 3.4 V Horizontal output voltage (low) V50L Low level DC voltage 0 ¾ 0.3 V Vertical output voltage (high) V 52H High level DC voltage 3.9 4.2 4.5 V Vertical output voltage (low) V 52L Low level DC voltage 0 ¾ 0.3 V Synchronizing signal clamp voltage (Ver.)V 39 V 39 clamp voltage 3.2 3.6 4.0 V Synchronizing signal clamp voltage (Hor.)V 41 V 41 clamp voltage 3.2 3.6 4.0 V External blanking input threshold levelV 16I 0.4 0.75 1.1 V Vertical pull-in range f VP-N fH = 15.75 kHz 56 ¾ 64 Hz n Electrical Characteristics at Ta = 25°C (continued)

• Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.

Parameter Symbol Conditions Min Typ Max Unit I2C interface Sink current when ACK I ACK Maximum value of sink current 1.8 2.5 5.0 mA for pin 14 at ACK Bus free before start t BUF 4.0 ¾¾ m s Start condition set-up time t SU, STA 4.0 ¾¾ m s Start condition hold time t HD, STA 4.0 ¾¾ m s Low period SCL,SDA t LOW 4.0 ¾¾ m s High period SCL t HIGH 4.0 ¾¾ m s Rise time SCL,SDA t R ¾¾ 1.0 ms Fall time SCL,SDA t F ¾¾ 0.35 ms Data set-up time(write) t SU, DAT 0.25 ¾¾ m s Data hold time(write) t HD, DAT 0 ¾¾ m s Acknowledge set-up time t SU, ACK ¾¾ 3.5 ms Acknowledge hold time t HD, ACK 0 ¾¾ m s Stop condition set-up time t SU, STO 4.0 ¾¾ m s DAC 3, 4, 5, 6, 7-bit DAC DNLE L 3, 4, 5, 6, 71LSB = {Data (max.)-Data (00)} 0.1 1.0 1.9 LSB /7, 15, 31, 63, 127 Step 8-bit DAC DNLE L 8 1LSB = {Data (FF)-Data (00)}/255 0.1 1.0 1.9 LSB Step Cut-Off DAC overlap D STEP Overlap of 8-bit 2-stage changeover 27 32 37 Step of R, B cut-off (Same for AFT)

• Standard conditions when testing 1. Input signal 1) VIF : f P = 45.75 MHz, VIN = 90 dBm, at video modulation: Modulation signal is 10-staircase Modulation m = 87.5% , pin 19 input level 84 dBm when VIN = 90 dBm 2) SIF : f S = 4.5 MHz, VIN = 90 dBm, modulation signal fM = 400 Hz, deviation: NTSC –25 kHz 3) Video : 10-staircase 2 V[p-p] (VBW = 1.43 V[0-p]) 4) Chroma : Color bar signal: Burst level 300 mV[p-p] Rainbow signal : Burst level 300 mV[p-p] 5) Sync. signal: Video signal 1.5 V[p-p] to 2.5 V[p-p] for both horizontal and vertical sync. signal input n Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.

n Terminal Equivalent Circuits Pin No. Equivalent circuit Description I/O 1 Chroma oscillation pin (3.58 MHz) AC

• Pin for chroma oscillation of 3.58 MHz. f = fC
• The pattern between pin and oscillator approx. should be made as short as possible. 0.3 V[p-p]

2 APC filter pin DC

• Filter pin for APC detection circuit approx. (Operates for BGP period) 5.6 V
• Detection sensitivity becomes high when external Rfi Large (Tends to be easily pulled in and afffected by noise.) 3Y S/YM input pin AC
• Fast blanking pulse input pin for OSD (Pulse)
• Y M On (Half-tone) at 1.0 V[0-p] or higher
• Y S ON(OSD input) at 3.0 V[0-p] or higher
• Recommended use range: 0 V to 6 V Y S Y M 25 mA 6.3 V 1 000 mA 3 300 pF 50 mA1.0 mF R 3.3 kW 200 W 270 W 84 kW 270 W 25 mA 25 mA 16 kW 5 V 25 mA

270 W 1 kW

1 V3 V

9 V (VCC1-1 )

1.5 kW

3.58 MHz

Temperature characteristic product should be used for C8 (-750 ppm/°C) 500 mA IN1 200 mA200 mA IN2 b curve fC V 2 n Electrical Characteristics at Ta = 25°C (continued)

• Standard conditions when testing (continued) 2. I2C BUS condition Sub Address Data (H) Sub Address Data (H)

00 Color 40 08 Drive R 40

01 Tint 40 09 Drive B 40

02 Bright 80 0A Audio Adj, YNR 10

03 Contrast 40 0B AFT 10

04 Sharpness 00 0C RFAGC 40

05 Cut-off R 80 0D Video Adj 08

06 Cut-off G 40 0E H center, RGB limiter 10

07 Cut-off B 80

n Terminal Equivalent Circuits (continued) H Out pin 50 H SYNC In pin 41 Pin No. Equivalent circuit Description I/O

4 External R input pin AC

5 External G input pin (Pulse)

6 External B input pin

• External input pin for OSD
• Output linearly changes according to input level
• Recommended use range: 0 V to 6 V 7 ¾ V CC1-1 (typ.9 V) DC
• Video circuit 9 V
• Chroma circuit
• RGB circuit
• Sync. circuit
• DAC circuit

8 R Out pin AC

9 G Out pin

10 B Out pin

• BLK level approx. 1.5 V
• Black (Pedestal) level approx. 3.0 V
• Recommended use range: -2.4 mA to +4.8 mA 11 Horizontal sync. detection pin DC
• Phase of horizontal synchronizing signal when and horizontal output pulse are detected synchronized and outputted 4.5 V
• Pin 11 becomes low at out of when synchronization asynchronous
• Color control becomes min. and chroma 0.1 V output disappears and VOUT goes into free- running state in a asynchronous condition
• Pay attention to impedance when pin 11 voltage is used for microcomputer (ZO ‡ 680 kW required)
• H SYNC period, when pin 50 at high: I1 ON at low: I2 ON 12 ¾ GND DC
• RGB circuit
• DAC. I2C circuit
• VIF (VCO) circuit 5.0 V 50 mA 8 mA 800 mA 800 mA 10 kW 12 kW to Chroma Circuit 2.8 V 3.7 V 12 kW 270 W 5 V (VCC2-2 ) 0.082 mF ZO ‡680 kW ZO11 50 W

5.0 V from m-COM 200 W 50 kW 50 kW to RGB Output Circuit pin4, 5, 6

n Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description I/O

13 ACL/ABL pin DC

• RGB output is blacked out when DC voltageapprox. 3.5 V of pin 13 is decreased from the outside. However, it is not blacked out when service switch has been turned on. (Service switch priority) When 01-D7 = 1, ABL functions, and brightness decreases by lowering DC voltage of pin 13
• When pin 13 is grounded, ACC gain becomes min. and it is possible to measure chroma free-running frequency. Measuring point is pin 51.
• Recommended use range: 0 V to VCC1

14 I 2C BUS Data input pin AC

• Input low level: 0.9 V or less (Pulse)
• Input high level: 3.1 V or more
• ACK sink capability: 1.8 mA
• Recommended use range: 0 V to V CC2

15 I 2C clock input pin AC

• Input low level: 0.9 V or less (Pulse)
• Input high level: 3.1 V or more
• Recommended use range: 0 V to V CC2

16 External blanking input pin AC

• RGB out blanking is applied when a voltage(Pulse) of 0.8 V or more is applied
• H SCP pulse output pin Horizontally synchronized 2 ms pulse is outputted.
• Recommended use range: - 0.8 mA to 0.2 mA, 0 V to 5.0 V 2.7 kW 100 W Data 14 1 kW 30 kW to Logic CircuitACK 51 kW 10 kW 30 kW 5 V (VCC2-2 )5 V 3.25 V 2 kW 20 mA 50 mA from m-com 2.7 kW 100 W Clock 1 kW 30 kW to Logic CircuitACK 51 kW 10 kW 30 kW 5 V (VCC2-2 )5 V 3.25 V 2 kW 20 mA 50 mA from m-com 10 kW H Sync.2 100 kW40 kW 5.6 kW 3.9 kW 270 W2.7 kW 10 kW 9 V (VCC1-1 ) 50 mA50 mA 0.7 V 8.2 V 5 V 0 V 9 V (VCC1-1 ) 60 kW60 kW 2.7 V 5.9 V 2.7 V 6.9 kW 7.1 kW Neck ABL 7.1 kW 140kW 6.9 kW 6.9 kW 5 kW When neck protect time high 5.0 V 5.0 V

n Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description I/O

17 White Peak Detect Filter input pin DC

• White gradation correction response characteristic is determined. When there is screen sag, make Cfi larger When screen response is slow, make C fi smaller 18 ¾ V CC2-1 (typ.5 V) DC
• VIF, SIF circuit 5 V

19 VIF input pin 1 AC

20 VIF input pin 2 f = fP

• VIF amp. input with balanced input DC level
• Input max.120 dBm approx. 2.7 V Input resistance: 1.2 kW (45.75 MHz) Input capacitance: 4.0 pF (45.75 MHz) 21 ¾ GND DC
• For VIF and SIF circuit

22 RF AGC output pin DC

• Collector open output
• Recommended use range: 0 V to VCC1 (9 V) Maximum sink current min.: 1.5 mA

23 SIF APC filter pin DC

• Filter pin for APC circuit of SIF. approx. 2.5 V
• Deemphasis characteristic is changeable by the capacitor between pin and GND 9 V 9 V (VCC1-1 ) 20 mA 270 W 6 kW Y OUT

375 W 50 kW

4.7 mF 40 mA 5 V (VCC2-1 ) 27 kW 1.2 kW 3.5 V SAW 1.2 kW 150 mA 0.022 mF 0.68 mH 150 mA 5 V (VCC2-1 ) IF AGC Bias RF AGC Control Bias 100 mA 1 kW1 kW 270 W 40 kW 6 kW3 kW 33 kW to Tuner 10 kW 9 V (VCC1-2 ) 12.2 kW 7.5 kW 57 kW 270 W1.5 V 875 W 100 pF4 pF

n Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description I/O

24 Audio output pin AC

• DC fluctuates by internal/external changeover 0 kHz to 20 kHz
• Recommended use range: - 0.8 mA to DC + 0.8 mA approx. 3.9 V

25 External video input pin AC

• Input pin for external video signal and DC 1 V[p-p] cut input (Composite)
• Typical: 1 V[p-p] (max. 1.5 V[p-p]) O is 100 W or less DC approx. 1.6 V

26 Decoupling pin DC

• S-curve in IC is wideband, but DC feedback is applied so that DC voltage of output signal becomes constant.
• DC level (typ. 4.5 V), fSfi high: V26fi low
• If C (4.7 mF) is too small, sound distortion tends to become larger at low frequency.

27 External audio input pin AC

• Input pin for external audio signal. DC cut0 kHz to 20 kHz input.
• Adjust typical input level to internal sound level.
• Input max. 7 V[p-p]

28 SIF signal input pin AC

• Input max. 110 dBm f = fS Blooming DC adjusting pin
• White gradation correction curve and bias DC to determine absolute clip point are provided.approx. 2.3 V (2.0 V to 4.5 V)
• Recommended use range: 0 V to VCC1 (9 V) 800 mA150 mA 9 V (VCC1-2 ) 270 W 9 V (VCC1-1 ) (VCC1-2 ) Int. Video to Video SW 50 mA 50 mA 1.6 V 7 mA 4.7 mF 500 W ZO <100 W 9 V (VCC1-2 ) 1.7 kW 100 mA 20 kW 10 kW 3 kW3 kW 270 W 270 W typ. 4.5 V 13 mA 4.7 mF C 9 V (VCC1-2 ) 50 mA 10 mF 150 mA 5.4 V to Audio SW 270 W

270 W65 kW

(VCC1-2 ) 100 mA to SIF Limitter Amp. 25 mA 270 W 128 kW 3 kW3 kW 1.5 kW Blooming DC 80 pF 0.01 mF

n Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description I/O

29 IF AGC filter pin DC

• Pin for IF AGC filter. The current obtainedapprox. 2 V from peak AGC circuit is smoothed by external capacitor.
• Since response becomes faster when C goes smaller, hum characteristic will be improved. However, sag tends to appear easily.

30 Video output pin AC

• INT.Video or EXT.Video selected by AV 2 V[p-p] SW is outputted.
• Recommended use range -3.2 mA to +0.4 mA DC level approx. 4.2 V

31 AFT output pin DC

• Offset of center voltage is adjusted by bus
• When AFT defeat SW is turned on (0B = 00), V 31 becomes a value determined by external resistance-divider.
• m of AFT is variable by impedance of externally attached resistor.

32 Internal video input pin AC

• Input pin for signal detected by VIF circuit 1 V[p-p] (Internal video signal). (Composite)
• DC cut input Typical input: 1 V[p-p] (max. 1.5 V[p-p]) ZO @ 280 W DC level approx. 1.6 V

33 VIF detection output pin AC

• Adjusted to center value by I2C bus approx. (Using upper 4-bit of 0 A) 2.1 V[p-p] DC voltage becomes approx. 1 V at external video mode (04-D6 = 1) Recommended use range: -1.6 mA to + 0.8 mA 500 W 400 mA 50 W 9 V (VCC1-2 ) 100 mA 9 V (VCC1-2 ) 1.1 kW 1.1 kW 40 kW1.1 kW 1.1 kW max. 350 mF to Tuner 33 kW 33 kW 9 V 270 W 0.01 mF 9 V (VCC1-1 ) (VCC1-2 ) Int. Video to Video SW 50 mA 50 mA 1.6 V 7 mA 4.7 mF 500 W ZO 50 W 9 V (VCC1-2 ) 150 mA 800 mA

270 W270 W

0.47 mF 5 V (VCC2-1 ) to IF Amp. 30 mA

n Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description I/O

34 APC filter pin DC

• Filter pin for VIF APC circuit. approx. 2.5 V
• Lock detection circuit for VCO is built in the IC inside to changeover the time constant for APC filter.

35 VIF oscillation pin AC

36 • Oscillation coil is changed according to approx. VIF frequency. 0.3 V[p-p]

• Allowable value of dispersion for coil DC level resonance point is within 1%. approx. 3.9 V 37 ¾ V CC1-2 (typ.9 V) DC IF circuit 9 V

38 Black level detection pin DC

• Black level detection pin for black extensionapprox. 5.1 V circuit
• The most black Y-level except for blanking circuit is held. Black detection sensitivity drops when ZO is made smaller, so that black detection becomes impossible unless a large black area. 39 Vertical sync. separation input pin AC Video input pin 2.0 V[p-p]
• Video signal input pin (Also composite video input)
• Typical input: 2.0 V[p-p]
• Sync. Top is clamped at 3.5 V
• Video signal should be inputted at low impedance. (under 100 W ) 5 V (VCC2-1 ) 3.25 V 75 mA 50 mA SW 1 0 0.47 mF 25 mA

270 W500 W

(VCC2-1 ) 1 200 mA 1.5 kW1.5 kW 1 200 mA 300 mA 300 mA 2.5V 35 36 2.5 kW 2.5 kW 2.5 kW 100 mA 50 mA 4.7 mF10 kW 18 pF 6.6 kW 270 W ZO 6.6 kW 9 V (VCC1-1 ) 16 kW 8 mA 3.5 V 16 kW 10 mA60 pF470 pF 50 mA 2.2 mF 2.4 kW 220 kW Video 5 V 1 kW 0.015 mF

n Terminal Equivalent Circuits (continued) Pin No. Equivalent circuit Description I/O

40 Vertical synchronizing signal clamp pin AC

• Peak clamp pin for separating vertical sync. f = fV signal.
• Integral amount of vertical sync signal itself has been determined by internal time constant. However, trigger application timing is determined by the selection of external constant C1. 41 ¾ Horizontal sync separation input pin AC
• Internal circuit of pin 39 and 41 are the same. 2 V[p-p]
• When Rfi large, slice level becomes deeper (Weak to Sync compression). When R fi small, slice level becomes shallower (Weak to fluctuation such as Ver. Sag).
• Sync. Top is clamped at 3.5 V. 42 ¾ V CC2-2 (typ.5 V) DC For chroma, jungle circuit 5 V

43 Chroma signal input pin AC +DC

Black extension start point adjusting pin Burst typ.

• Pin 43 is chroma signal input pin, and black300 mV[p-p] extension start point is adjusted by externally applied DC voltage. DC typ. DC level: high « low 4.5 V Start point: Shallow « Deep Black extension effect: Small « Large
• Recommended use range: 0 V to VCC1 (9 V) 44 ¾ GND DC
• For video, chroma, jungle circuit 0 V

45 FBP input pin AC

• FBP input pin for horizontal blanking and FBP AFC circuit
• Threshold level HBLK: 0.7 V AFC: 1.9 V
• A voltage input of 0 V or less is inhibited.
• Recommended use range: 0 V to VCC2 (5 V) 46 ¾ Horizontal stabilized power supply pin. DC 6.2 V 5 V (VCC2-2 ) C1 220 2.2 mF 4 mA 30 kW 3 kW 50 kW270 W 200 W 10 kW 10 kW 4.3 V to Ver. Count Down

5 V (VCC2-2 )

1.9 V 0.7 V 2.7 kW 2.7 kW 270 W 100 kW

Pin No. Equivalent circuit Description I/O

47 Horizontal AFC1 filter pin DC

• The capacitor connected to pin 47 is charged typ. 4.3 V and discharged after comparing the phase of horizontal synchronizing signal and pulse inside the IC.
• R1, R2, C1 and C2 are lag lead filter for AFC1.

48 Horizontal oscillation pin AC

• Oscillation takes place at 32 · fH @ 503 kHz f = 32 fH by ceramic oscillator. (approx.
• Horizontal and vertical pulse are generated500 kHz) by count-down circuit inside the IC.

49 Overvoltage protection input pin DC

• If increasing input pin voltage from 0 V Normally at VREF (pin 46) = 6.2 V; 0 V (1) Horizontal oscillation come to be out of synchronization: approx. 6.15 V (2) Blacked out: (1)+70 mV
• Recommended use range: 0 V to VCC1 (9 V)

50 Horizontal pulse output pin AC

• Duty cycle approx. 37% Pulse
• Recommended use range: -6.4 mA to +0.1 mA 200 mA 1 mF 1 000 mA Hor. Sync. Hor. OSC0.033 mF 27 kW 27 kW 1.8 kW R1AFC1 Detecter 1.5 V 4.3 V 6.2 V (VCC3 ) Horizontal b curve fH V 53 200 mA 100 mA be used (-750 ppm/°C) 220 pF: Temperature characteristic product should 80 mA 6.2 V (VCC3 ) 10 kW 10 kW 22 kW 300 W 100 mA V CC3 48.3 kW 20 kW 1 kW 1 kW 9 V (VCC1-1 ) 50 W 10 kW 6.2 V (VCC3 ) 40 kW Hor. Out 3.5 V 0 V 19 kW 4.3 V 3.5 V n Terminal Equivalent Circuits (continued)

Pin No. Equivalent circuit Description I/O 51 CW output pin / input pin for spot killer off. AC (Output amplitude 860 mV[p-p]) Approx. The pin also shares in Hold-down detection.830 mV[p-p]

• At normal: 6.1 V (DC)
• At hold-down: 1.2 V (DC)
• Apply 9 V(VCC1 ) DC to turn off spot killer. f = 3.58 MHz Recommended use range: - 0.4 mA to + 0.1 mA

0 V to VCC1

52 Vertical pulse output pin AC

• Negative polarity, pulse width 6.25 H Pulse
• Recommended use range: - 0.8 mA to + 0.1 mA

(VCC2-2 ) 4.2 V 4.2 V n Terminal Equivalent Circuits (continued)