AN5163K PANASONIC | Alldatasheet
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NTSC Color-TV Signal Processor IC Overview I5U— ES tat: am The AN5163K is a single-chip IC which incorporates alll q b | | B= functions needed for NTSC color-TV signal processing. q ig — And sets production line will be rationalized by built-in q P| |= - °C bus interface. q b | |B] i Features q bs |= + Built-in VIF, SIF, video signal processing, chroma sig- q BS |= | nal processing, and synchronization signal processing q P =} circuits q P| |B=28 + Built-in an °C bus interface circuit d E | E= 23
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iM L_Jea 53503 3001s (as24) ~ Pin Descriptions 52-Pin SDIP Package (SDIPOS2-P-0600A) PinNof Pinname ino Pin name 2 [Pessalclanp ‘| >8 [NC 3 [ACL Service switch | 29 | SIF InRF AGC delay © [Ring Veg @) ISTP 6 [Bint | 32 J AF Toco 7 [Simp] 33 [in vio ipa 3 [ck De ink Sub Cor | 34 [VIF seston oa 9 [Routt 35 J APC (VIF) 10 [Goupar 26 v0 at 11 [Bupa veo) 12 | Vee (1) video/chroma system | 38 | Vocs (1) video/jungle system 1B [Chom VO 39 [Xi 14 [Lok ston 0 ex. pea mp is[SDA_ «41. [GND (1) video/chroma/jungle system 16 [sch «42. [ Chroma In/Black Level Start ve | ViFinpu (1) | + [inp 19 [viFinpu@) | 45 | Wesel am 21 [Ex Auioinpat 47 [Hora 22 |RFAGC oupa | «® [Ho osc 23 [Awio capa a8 [Xray poston 25 |stF dawson | 51 ] old Down Rt 26 [AFToupu | 52 Tver output Panasonic 90 @@® 6932452 0014174 333
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———— eee Wl Absolute Maximum Ratings Parameter Symbol Unit | Sopply voltage ct Y WVecwnm | 60 Supply curent Tee | te [6 ma [uw [ow Power dissipation ™*?) [ett Operating ambient temperature "= c | Storage temperature N=) c | Note 1) Ta=25'C except operating ambient temperature and storage temperature. Note 2) Allowable power dissipation of the package at Ta=70T. I Recommended Operating Range (Ta=25°C) Parameter Range rating supply voltage range Operating supply current range [| ils 10mA to 25mA i Reference Pp—Ta 2eof—]—T 7 TT pt IC wit et ink en z i] — or Pec daismw (25%) = sof — XE ZET ee P TN TT yy = oof +N} Ty 2° PE T TN TT F 120) | 1 XK TT] $ ee 5 sof | | | \\ [I é poy NE aof—| | tT NI poy IN oT tN 02s 50751028150 Ambient temperature Ta (C) Panasonic
@ Electrical Characteristics (Ta=25+2C) Parameter [Symbol [Condition min [yp | max | Unit Supply cure (1) [te | GinentwhenVn=9V_——| «6 T1] 12] ma Supply curent (2) ma Supply curent (3) [ta | Cumentwhen vo=ov[_a8 | 49 | 60 | ma Supply eurent (4) | tw | Current when Vn=sv_ [a6 | 33 | 40 | ma Stabilized supply eument mA Ouiput resistor (Pini) | Rue [DCmeasuremen | 20 | dso] a Input esitor Pine, @) ia Ouiput resistor (Pind) | Rn | DCmeasurement | 20 | [iso] Input esistor Pind) [Rar [| DCmeasuemen | ss] os] 75] en VIF Circuit (The test condition for below is fp=45.7SMHz Vin=90dBy ) eS =8 (typ) Tv APC pulhin range () [fo | Pulhin ange offow band side | — | —13| —06 | Miz Video SW voltage gain [Gow | FIM Vin=Ver | 30 | 46 60] ap SIF Circuit (The test condition for below is fs=4.5MHz Vin=90dBy: ) 4f=+25kHz_ fm=400Hz Audio detection output (standard) Von | DATAOC=8 (typ.) 350 | 450 | 550 | mVrms [vom [Bese [a0] oo] 50 Audio detection output (min.) a3 Audio detection output (max.) | Vous | DATAOC=0,raiotoryp. [9 | —s| —2| @B Audio output DC voltage (Ext.) | Vaex [DATA OD—1=1(extema) [35 [ a0[ 45] v Audio SW voltage gain 4B COs 6932852 0034177 O42 ao
M@ Electrical Characteristics (cont.) (Ta=25+2°C) Parameter Symbol_[ Condition] min [typ [max [Unit | Video Signal Processing Circuit (The test condition for below is established to be input 0.7Vpe stair step wave Gout) , Video output (max.) DATA 03=7F (max.) [33] 43] 53 | ver Video output (min.) DATA 03=00 (min.) | o3[ os[ o7[ Wer 7 5 DATA 04=00 DATA 02=81 (typ.) | 30 Pedestal level (standard) Voet ATA 028 24| 30] Vv Pedestal variable range Diference beeen DATA 02=00 and FF y — we fa] ABL sey [ram [ oo i we DC restoration rate APL10% 10 90% [95 [00 | 0s | % Senice SW vestolvenuge | Vow [0s | os | 09 v Color Signal Processing Circuit (The test condition for below is burst 150mVp.r, where B out as reference) Color difference output (max.) DATA 00=7F, amplitude on one side Vo-r Color difference output (min.) DATA 00=00 | — | 0]. 100 |mvr» ‘ACC characteristics (1) Burst 150--300mVp-» | o9 | 10] 12 | times ACC characteristics (2) Burst 150—-30mVp—p fo7| 10] 1.1 | times Fai on [ae | Data ai=Fe esa) a Ti ibe rge [a _[Daraot=o0 | ee | as a0] a Demoddaionoujuraio @) | RB] are | 6 | 1s | ies Demodulation output ratio (G) [opto | 034 | at | times Demodnaion pat eng (R) | er [SY | | | ae Denodnain oupatangie(G)| 2o_| | a | 2 | 208 | oe Color killer tolerance OdB=150mVr-r,BPFOFF | —49 | —39| -33| 4B APC palkinge [oie [0 | eo | — |e APC pull-in range (L) [fon J t000 | = 450 [He RGB Processing Circuit ; ; DATA 02 (bright) : Brightness voltage tracking MT difference between 02=41 to C1 Lt times: Panasonic
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—$—$S ee @ Electrical Characteristics (cont.) (Ta=25+2) Parameter |_Symbot [Condition [min Typ [max [Unit Video voltage gain relative ratio | 40rc [RBowoupuraioncor | os] 10] 12| times Drive adjustment range | Gy [0 To [so Cut-off adjustment range [| Weewom [tg [a2 ast tes voluge [Ws | Miniminivetawain SwON] 07] 10 [13] —v External RGB pedestal voltage [ven [Os Ta 30 fv Extemal RGB pedestaldifferencevottage| Ven [| 250] 0] 250] mv Intemalfexternal pedestal difference voltage] Vnuae | Internal-extemal | —250| 0 | 250 | mv Enema RGB ouput dileecevoinge | awe || ~ae | of toe v Exeral RGB coms varie range | ECaumn | | 15 | ie [2 | a auetkoumavoines@) | vow | Rem eroeo | os] o| ves] v pe Synchronizing Signal Processing Circuit me Horizontal free-run oscillation frequeney| fo [15.45 | 15.75 | 1605 | az =| Horizontal out pulse duty [wo [oe as Pas Horizontal pall-in range a Vertical free-run oscillation frequency | fv | iS] |e Vertical output pulse width [v0 | fu=15.75KHe fv=60He | os7 | 06s | 071 | ms Vera pln age [te [isms ts] — | oe |e Vertical blanking pulse width | se | MeasueatkoBo [os [ta] 13| ms Horizontal ourput voltage (H) [vw fa Fa [30] ov Horizontal output voltage (L) [ove fo os fv Vertical ouput voltage (H) [ven [Oso [a [ae [ov Vertical ouput voltage (L) {va [oP os Tv Picture center variable range [ate | 30 [7 Tas | as PC Interface Sink current at ACK time [te [oT 0 | 2s = Tima SCL,SDA signal input HighLevel | Von | | | — | — Tv SCL,SDA signal input LowLevel | Viow | | — | — [ot Input maximum frequency en VIF Circuit (The test condition for below is f»=45.75MHz) Input sensitivity [vs [Vous=sap = To [Taw Maximum input | Vm [Vous tiup | (103) | Guo) [| — a, SN ratio | sine | Vin=900Bu (50) | 58) | — {a Differential gsin % Differential phase | pre | vin=vodbe | Ls) | eg Black noise clamp level | ave [| | (028) | (0s) | (os) |v Tntermodulation pom Joa | Input eines PHB_B) [Rin | Peas [uo | as ae [an Tnput capacitance (Pind, @) Cis | £=45.75MHz G32) pF Sh 992852 0004379 15 Panasonic
W@ Electrical Characteristics (cont.) (Ta=25+2) , Parameter Symbol [Condition [min [typ] max [Unit | AFT defeat SW operation voltage Maximum voltage at v Video SW crosstalk [ctv [rei | [00 | SIF Circuit Tnput limiting level [Ven | Vos=—3p | — |) 9) | a | AM rejection ratio AM=30% _Vin=904B, Gs) | — | ow Total harmonics distortion ratio [THD | vin=90B, S| =~) | (3)| 5) % Audio SW crosstalk | ctw | vin=o0ape | =| (985) 4B Video Signal Processing Circuit (The test condition below is to be measured at G out) Delay line ON/OFF gain difference Ratio of PEON (0.9) times , . a= Y signal delay time ‘Lane (Pao) | (390) (530) | ns , [ver _| Input: fullback, difference between |; _ Black level correction (1) Vous black correction SW SV and OPEN (—100) (0) | (100) | mv , Tnpot: ful black, difference between . Block Ive comeson (2) black conection SW 3V and 9V my ; Toputapprox. 20TRE, voltage difference Black level correction (3) Vous lack correction SW open and gv} (200) | (300) | (S00) | mv Black evel enon ar pot (oy | RE Black level correction start point (2) Va=45V TRE Black level correction start point (3) (20) [ (25) | RE Vie uit Vos van (00) Tov Pedestal level Voc variation Veci=8.1 to 9.9V (300) | mv/v Color Signal Processing Circuit (The test condition below is burst 150mVp., where reference Bout) Denodulain uputcesidaleaniy [Va [sd |_| 0) [mVnn Demodulation output Voc variation Voci=8.1V 10 9.9V (100) |nvs-2v . Tint deviation when Static phase error fe=~300 to 300Hz change (5) |acrtome cogs, Color level fluctuation portion when a Sub color control characteristics AVae | DATAOA-S=1 V8=4V (1.2) | (1.5) | (1.9) | times RGB Processing Circuit CYP ratio (0.95) (1.85) [times Panasonic
a @ Electrical Characteristics (cont.) (Ta=25+2°C) Parameter | Symbol [Condition [min Typ [max [tn Ditaca in a Pedestal level temperature variation Ta=—20 to +70 [| — |(-18) | — [mvc Ys siching ed ae Synchronizing Signal Processing Circuit Horizontal output starting voltage ot opera eran Oe (45) | (30)| ov Lock detection output voltage In horizontal AFC lock (6.0) v Lock detection charging anddiscaringecaren} tay | (206) [(208) [TY [ma FBP slice level [vw [oo | 0a) | 00 [9 |v Horizontal? curve [ge fs) | |) rer Horizontal AFC a OC = Tolerance of minimum voltage ICs for = Overvoltage protective operation voltage] Vx-ray | (V6V51/2) at which horizontal | (—30) (0) | (+30) mV ly & synchronization comes off = Black-out operation voltage Pieaence voltage from (0.18) v NC Interface Basin tee a es CD San conn spine [sn | ef Ps St conden oldie [tesm [0 Car dS spe [toe [ef — Ps High period SCL a Fall ine SL, SDA a Data set-up time (write) [towne [Of os) Ts Akvis ap es DAG 4bit DAC DNLE ILSB= IDATA (OF) (01) | Go) oe = — , LSB Toit DAC DNLE mse BRUNO (ou) STEP = = B B THEDACDNLE con | ao] | ster Note) The characteristics value in parentheses is not a guaranteed value, but reference one on design. —_— SO So6992852 0014181 573 Es Panasonic
1 Operational descriptions
- DAC CONTROL and SUB ADDRESS SLAVE ADDRESS ; 8A Conte Rema a TCS mre [7 || at _fat=or00 0001 puoness [8 [| st __fsi=r0000001 conreast [7 | sat — snanpness [7 [| | | — corom@®) [7M [sat =e curorr(@) | 7erF@) [0 =i _—*is me) curom(e) [rere [oat —*foo= 7m) a CCT HoccENTER | # fai «oT BLueBAcksw [1 | @>-0 | __1__[DATAO=BBACKON auposw [1 | =i | 0 [DATAO=mvr DELAYLINESW [1 | _D=4_-|_0‘[DATAO=DIL.ON curomswr [i | 00-5 | __0__|DATAG~omF-sETORF coromswo [1 | @=6 | 0 __[DATAo=omF—sETOFF SubColorsW [| sts] ~——OA-5_———| 0 _[DATA1Black correction off, sub-color ON Note) (1) Values at power ON are not guaranteed, and initial setting should be required. (2) For 7+ 1, the 7-bit DAC is changed over in two steps. For 7+1+ (1), the 7-bit DAC is changed over in four steps. SS 932852 0004182 4OT Panasonic
—-!] * FC bus protocol PC~BUS Formats (1) Slave address = 10001010 (2) Slave address format : [s [stave avon [ox [Sus Abpe [a [bata wv [a |] t t i Start Write Acknowledge bit Stop condition condition (3) Subaddress byte and data byte format : ie functions Data ___byte "| Dr D6 Ds St SO? oT color SSSS«~=SC SSCA ~~S«AOS~~AOS~~«AOS-AOD AOI -AOO oi ftin Cd (CASSIS. «SOAS CAD =A ALON 02 | brightness |= A27~—A26 «ADS —A2A—-ADS._-ADD~ADI ADO 03 0 A386 A353 A332 ABCA 04 0 Ade AS A443 AAD AGT AO.
06 A676 AGS AGS AGS AG2 _—_AGL__—_AGO ICs for
09 A97A96A9S_—-AD4 ADB. ADD ADT. —«ASO OA 0 0 0 0 _AA3_AA2_—AAI_AAO 0B oo 0 0 _AB3_AB2_ ABI ABO oc oo 00 ACAD SC AO Panasonic