CY8C61X5 INFINEON | Alldatasheet

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PSoC 6 MCU: CY8C61x5 Datasheet PSoC 61 MCU Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 002-30703 Rev. *F Revised October 26, 2022 General Description PSoC® 6 MCU is a high-performance, ultra-low-power and secured MCU p latform, purpose-built for IoT applications. Based on the PSoC 6 MCU platform, this product line is a combination of a dual CPU microcontroller with low-power flash technology, digital programmable logic, high-performance analog-to-digital conversion and standard communication and timing peripherals.

Features

Note: In PSoC 61 the Cortex M0+ is reserved for system functions, and is not available for applications. 32-bit Dual CPU Subsystem ■ 150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU) ■ 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU ■ User-selectable core logic operation at either 1.1 V or 0.9 V ■ Active CPU current slope with 1.1-V core operation ❐ Cortex-M4: 40 µA/MHz ❐ Cortex-M0+: 20 µA/MHz ■ Active CPU current slope with 0.9-V core operation ❐ Cortex-M4: 22 µA/MHz ❐ Cortex-M0+: 15 µA/MHz ■ Three DMA controllers Memory Subsystem ■ 512-KB application flash, 32-KB auxiliary flash (AUXflash), and 32-KB supervisory flash (SFlash); read-while-write (RWW) support. Two 8-KB flash caches, one for each CPU. ■ 256-KB SRAM with programmable power control and retention granularity ■ One-time-programmable (OTP) 1-Kb eFuse array Low-Power 1.7-V to 3.6-V Operation ■ Six power modes for fine-grained power management ■ Deep Sleep mode current of 7 µA with 64-KB SRAM retention ■ On-chip DC-DC buck converter, <1 µA quiescent current ■ Backup domain with 64 bytes of memory and real-time clock Flexible Clocking Options ■ 8-MHz internal main oscillator (IMO) with ±2% accuracy ■ Ultra-low-power 32-kHz internal low-speed oscillator (ILO) ■ On-chip crystal oscillators (16 to 35 MHz, and 32 kHz) ■ Phase-locked loop (PLL) for multiplying clock frequencies ■ Frequency-locked loop (FLL) for multiplying IMO frequency ■ Integer and fractional peripheral clock dividers Quad-SPI (QSPI)/Serial Memory Interface (SMIF) ■ Execute-In-Place (XIP) from external quad SPI flash ■ On-the-fly encryption and decryption ■ 4-KB cache for greater XIP performance with lower power ■ Supports single, dual, and quad interfaces with throughput up to 320 Mbps Segment LCD Drive ■ Supports up to 63 segments and up to 8 commons. ■ Operates in system Deep Sleep mode Serial Communication ■ Seven run-time configurable serial communication blocks (SCBs) ❐ Six SCBs: configurable as SPI, I2C, or UART ❐ One Deep Sleep SCB: configurable as SPI or I2C ■ USB Full-Speed device interface ■ One SD Host Controller/eMMC/SD controller ■ One CAN FD block Timing and Pulse-Width Modulation ■ Twelve timer/counter/pulse-width modulators (TCPWMs) ■ Center-aligned, edge, and pseudo-random modes ■ Comparator-based triggering of kill signals Programmable Analog ■ 12-bit 2-Msps SAR ADC with differential and single-ended modes and 16-channel sequencer with result averaging ■ Two low-power comparators available in system Deep Sleep and Hibernate modes ■ Built-in temperature sensor connected to ADC Up to 64 Programmable GPIOs ■ Two Smart I/O™ ports (8 I/Os) enable Boolean operations on GPIO pins; available during system Deep Sleep ■ Programmable drive modes, strengths, and slew rates ■ Two overvoltage-tolerant (OVT) pins Capacitive Sensing ■ Cypress CapSense® sigma-delta (CSD) provides best-in-class signal-to-noise ratio (SNR), liquid tolerance, and proximity sensing ■ Enables dynamic usage of both self and mutual sensing ■ Automatic hardware tuning (SmartSense™)

Document Number: 002-30703 Rev. *F Page 2 of 73 PSoC 6 MCU: CY8C61x5 Datasheet Security Built into Platform Architecture ■ Authentication during boot using hardware hashing ■ All debug and test ingress paths can be disabled ■ Up to eight protection contexts Cryptography Accelerator ■ Hardware acceleration for symmetric and asymmetric cryptographic methods and hash functions ■ True random number generation (TRNG) function Packages ■ 100 TQFP, 68 QFN, 49 WLCSP Device Identification and Revisions ■ Product line ID (12-bit): 0x105 ■ Major/Minor die revision ID: 1/2 ■ Firmware revisions: ROM Boot: 7.1, Flash Boot: 3.1.0.378 (see Boot Code section) This product line has a JTAG ID which is available through the SWJ interface. It is a 32-bit ID, where: ■ The most significant digit is the device revision, based on the Major Die Revision ■ The next four digits correspond to the part number, for example "E4B0" as a hexadecimal number ■ The three least significant digits are the manufacturer ID, in this case "069" as a hexadecimal number The Silicon ID system call can be used by firmware to get Silicon ID and ROM Boot data. For more information, see the technical reference manual (TRM). The Flash Boot version can be read directly from designated addresses 0x1600 2004 and 0x1600 2018. For more information, see the technical reference manual (TRM).

Document Number: 002-30703 Rev. *F Page 4 of 73 PSoC 6 MCU: CY8C61x5 Datasheet Development Ecosystem PSoC 6 MCU Resources Cypress provides a wealth of data at www.cypress.com to help you select the right PSoC device and quickly and effectively integrate it into your design. The following is an abbreviated list of resources for PSoC 6 MCU: ■ Overview: PSoC Portfolio, PSoC Roadmap ■ Product Selectors: PSoC 6 MCU ■ Application Notes cover a broad range of topics, from basic to advanced level, and include the following: ❐ AN221774: Getting Started with PSoC 6 MCU ❐ AN218241: PSoC 6 MCU Hardware Design Guide ❐ AN213924: PSoC 6 MCU Device Firmware Update Guide ❐ AN215656: PSoC 6 MCU Dual-CPU System Design ❐ AN219528: PSoC 6 MCU Power Reduction Techniques ❐ AN85951: PSoC 4, PSoC 6 MCU CapSense Design Guide ■ Code Examples demonstrate product features and usage, and are also available on Cypress GitHub repositories. ■ Technical Reference Manuals (TRMs) provide detailed descriptions of PSoC 6 MCU architecture and registers. ■ PSoC 6 MCU Programming Specification provides the infor- mation necessary to program PSoC 6 MCU nonvolatile memory ■ Development Tools ❐ ModusToolbox® software enables cross platform code de- velopment with a robust suite of tools and software libraries ❐ There is no kit available for the PSoC 61 product line. How- ever, the CY8CPROTO-062S3-4343W PSoC 6 Wi-Fi-BT Prototyping Kit is available: a low-cost hardware platform that enables design and debug of the PSoC 62 CY8C62x5 prod- uct line. ❐ PSoC 6 CAD libraries provide footprint and schematic sup- port for common tools. BSDL files and IBIS models are also available. ■ Training Videos are available on a wide range of topics including the PSoC 6 MCU 101 series ■ Cypress Developer Community enables connection with fellow PSoC developers around the world, 24 hours a day, 7 days a week, and hosts a dedicated PSoC 6 MCU Community ModusToolbox™ IDE and the PSoC 6 SDK ModusToolbox Software is Cypress' comprehensive collection of multi-platform tools and software libraries that enable an immersive development experience for creating converged MCU and wireless systems. It is: ■ Comprehensive - it has the resources you need ■ Flexible - you can use the resources in your own workflow ■ Atomic - you can get just the resources you want Cypress provides a large collection of code repositories on GitHub. This includes: ■ Board Support Packages (BSPs) aligned with Cypress kits ■ Low-level resources, including a hardware abstraction layer (HAL) and peripheral driver library (PDL) ■ Middleware enabling industry-leading features such as CapSense, Bluetooth Low Energy, and mesh networks ■ An extensive set of thoroughly tested code example applications Note: The HAL provides a high-level, simplified interface to configure and use the hardware blocks on Cypress MCUs. It is a generic interface that can be used across multiple product families. For example, it wraps the PSoC 6 PDL with a simplified API, but the PDL exposes all low-level peripheral functionality. You can leverage the HAL's simpler and more generic interface for most of an application, even if one portion requires finer-grained control. ModusToolbox Software is IDE-neutral and easily adaptable to your workflow and preferred development environment. It includes a project creator, peripheral and library configurators, a librar y manager, as well as the optional Eclipse IDE for ModusToolbox . For information on using Cypress tools, refer to the documentation delivered with ModusToolbox software, and AN228571: Getting Started with PSoC 6 MCU on ModusToolbox.

Figure 1. ModusToolbox Software Tools

where the particular block is still functional (for example, the SRAM is functional down to system Deep Sleep mode). Figure 2. Block Diagram

512 KB + 32 KB + 32 KB

8 KB cache for each CPU

Document Number: 002-30703 Rev. *F Page 7 of 73 PSoC 6 MCU: CY8C61x5 Datasheet There are three debug access ports, one each for CM4 and CM0+, and a system port. PSoC 6 MCU devices include extensive support for programming, t esting, debugging, and tracing both hardware and firmware. All device interfaces can be permanently disabled for applications concerned about a reprogrammed device or starting and interrupting flash programming sequences. All programming, debug, and test interfaces can be disabled. Complete debug-on-chip functionality enables full device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are requir ed to fully support debug. The Eclipse IDE for ModusToolbox provides fully integrated programming and debug support for these devices. The SWJ (SWD and JTAG) interface is fully compatible with industry-standard third party probes. With the ability to disable debug features, with very robust flash protection, and by allowing customer-proprietary function ality to be implemented in on-chip programmable blocks, PSoC 6 provides multiple levels of device security.

hardware configuration files, s tartup code, and linker files. regarding the use of associated registers. plications have functions to access them from within PDL. override the hardware defaults. response time, high code density, and high throughput. The Cortex-M0+ (CM0+) has single-cycle multiply, and an MPU. see the Register and Architecu TRM. . and device-level security, safety, and protection features. in the Armv6-M Architecture Reference Manual). Sleep power modes as defined by Arm. peripherals as well as the registers in both CPUs. Table 1. Active Current Slope at V

debugging and tracing of both CPUs. eight internal (software only) interrupts. technical reference manual (TRM). locking scheme which can be used to manage shared resources. reference manual (TRM) for detail. bus master level. Other bus masters use additional MPUs. privilege level, secured/non-secured, and protection context. see the technical reference manual for details. Table 2. Distribution of IPC Channels and Other Resources clock dividers, DMA channels, etc.

1 CM0+ interrupt mux

Document Number: 002-30703 Rev. *F Page 10 of 73 PSoC 6 MCU: CY8C61x5 Datasheet Memory PSoC 6 contains flash, SRAM, ROM, and eFuse memory blocks. ■ Flash There is up to 512 KB of application flash, organized in 256-KB sectors. There are also two 32-KB flash sectors: ❐ AUXflash, typically used for EEPROM emulation ❐ Supervisory flash (SFlash). Data stored in Sflash includes device trim values, Flash Boot code, and encryption keys. After the device transitions into the “Secure” lifecycle stage, SFlash can no longer be changed. The flash uses 128-bit-wide accesses to reduce power. Write operations can be performed at the row level. A row is 512 bytes. Read operations are supported in both Low Power and Ultra-Low Power modes, however write operations may not be performed in Ultra-Low Power mode. The flash controller has two caches, one for each CPU. Each cache is 8 KB, with 4-way set associativity. ■ SRAM Up to 256 KB of SRAM is provided. Power control and reten- tion granularity is implemented in 32-KB blocks allowing the user to control the amount of memory retained in Deep Sleep. Memory is not retained in Hibernate mode. ■ ROM The 64-KB ROM, also referred to as the supervisory ROM (SROM), provides code (ROM Boot) for several system func- tions. The ROM contains device initialization, flash write, se- curity, eFuse programming, and other system-level routines. ROM code is executed only by the CM0+ CPU, in protection context 0. A system function can be initiated by either CPU, or through the DAP. This causes an NMI in CM0+, which causes CM0+ to execute the system function. ■ eFuse A one-time-programmable (OTP) eFuse array consists of 1024 bits, of which 648 are reserved for system use such as die ID, device ID, initial trim settings, device life cycle, an d security settings. The remaining bits are available for storing security key information, hash values, unique IDs or similar custom content. Each fuse is individually programmed; once programmed (or “blown”), its state cannot be changed. Blowing a fuse transi- tions it from the default state of 0 to 1. To program an eFuse, V DDIO0 must be at 2.5 V ±5%, at 14 mA. Because blowing an eFuse is an irreversible process, pro- gramming is recommended only in mass production under controlled factory conditions. For more information, see PSoC 6 MCU Programming Specifications. Boot Code Two blocks of code, ROM Boot and Flash Boot , are pre-programmed into the device and work together to provide device startup and configuratio n, basic security features, life-cycle stage management and other system functions. ■ ROM Boot On a device reset, the boot code in ROM is the first code to execute. This code performs the following: ❐ Integrity checks of flash boot code ❐ Device trim setting (calibration) ❐ Setting the device protection units ❐ Setting device access restrictions for “Secure” lifecycle states ROM cannot be changed and acts as the root of trust in a secured system. ■ Flash Boot Flash boot is firmware stored in SFlash that ensures that only a validated application may run on the device. It also ensures that the firmware image has not been modified, such as by a malicious third party. Flash boot: ❐ Is validated by ROM Boot ❐ Runs after ROM Boot and before the user application ❐ Enables system calls ❐ Configures the Debug Access Port ❐ Launches the user application

into the Arm-defined regions shown in Table 8. Note that code can be executed from the Code and External RAM regions. Table 3. Address Map for CM4 and CM0+ vector table, which starts at address 0. 0x2000 0000 – 0x3FFF FFFF SRAM Data region. This region is not su pported in PSoC 6. in this region is not supported in PSoC 6. section). Code can be executed from this region. Provides access to peripheral registers within the CPU core. 0xE010 0A000 – 0xFFFF FFFF Device De vice-specific system registers. Table 4. Internal Memory Address Map for CM4 and CM0+

Document Number: 002-30703 Rev. *F Page 12 of 73 PSoC 6 MCU: CY8C61x5 Datasheet System Resources Power System The power system provides assurance that voltage levels are as required for each respective mode and will either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (brown-out detect (BOD)) when the power supply drops below specified levels. The design guarantees safe chip operation between power supply voltage dropping below specified levels (for example, below 1.7 V) and the reset occurring. There are no voltage sequencing requirements. The V DDD supply (1.7 to 3.6 V) powers an on-chip buck regulator or a low-dropout regulator (LDO), selectable by the user. In addition, both the buck and the LDO offer a selectable (0.9 or 1.1 V) core operating voltage (VCCD). The selection lets users choose between two system power modes: ■ System Low Power (LP) operates VCCD at 1.1 V and offers high performance, with no restrictions on device configuration. ■ System Ultra Low Power (ULP) operates VCCD at 0.9 V for exceptional low power, but imposes limitations on clock speeds. In addition, a backup domain adds an “always on” functionality using a separate power domain supplied by a backup supply BACKUP) such as a battery or supercapacitor. It includes a real-time clock (RTC) with alarm feature, supported by a 32.768-kHz watch crystal oscillator (WCO), and power-management IC (PMIC) control. Refer to Power Supply Considerations for more details. Power Modes PSoC 6 MCU can operate in four system and three CPU power modes. These modes are intended to minimize the average power consumption in an application. For more details on power modes and other power-saving configuration options, see the application note, AN219528: PSoC 6 MCU Low-Power Modes and Power Reduction Techniques a n d t h e Architecture TRM, Power Modes chapter . Power modes supported by PSoC 6 MCUs, in order of decreasing power consumption, are: ■ System Low Power (LP) – All peripherals and CPU power modes are available at maximum speed ■ System Ultra Low Power (ULP) – All peripherals and CPU power modes are available, but with limited speed ■ CPU Active – CPU is executing code in system LP or ULP mode ■ CPU Sleep – CPU code execution is halted in system LP or ULP mode ■ CPU Deep Sleep – CPU code execution is halted and system Deep Sleep is requested in system LP or ULP mode ■ System Deep Sleep – Only low-frequency peripherals are available after both CPUs enter CPU Deep Sleep mode ■ System Hibernate – Device and I/O states are frozen and the device resets on wakeup CPU Active, Sleep, and Deep Sleep are standard Arm-defined power modes supported by the Arm CPU instruction set architecture (ISA). System LP, ULP, Deep Sleep and Hibernate modes are additional low-power modes supported by PSoC 6 MCU. Clock System Figure 15 shows that the clock system of this product line consists of the following: ■ Internal main oscillator (IMO) ■ Internal low-speed oscillator (ILO) ■ Watch crystal oscillator (WCO) ■ External MHz crystal oscillator (ECO) ■ External clock input ■ One phase locked-loop (PLL) ■ One frequency-locked loop (FLL) Clocks may be buffered and brought out to a pin on a Smart I/O port. The default clocking when the application starts is CLK_HF[0] being driven by the IMO and the FLL. CLK_HF[0], clk_fast, clk_peri, and clk_slow are all either 50 MHz (LP mode) or 25 MHz (ULP mode). All other clocks, including all peripheral clocks, are off. Internal Main Oscillator (IMO) The IMO is the primary source of internal clocking. It is trimmed at the factory to achieve the specified accuracy. The IMO frequency is 8 MHz and tolerance is ± 2%. The IMO can operate in system D eep Sleep mode to drive the LCD block for better contrast (and higher power) than is possible with the 32-kHz mode. Internal Low-Speed Oscillator (ILO) The ILO is a very low power oscillator, nominally 32 kHz, which operates in all power modes. The ILO can be calibrated against a higher accuracy clock for better accuracy.

GPIOs and peripheral blocks. function properly. POR activates automatically at power-up. minimum required logic operating voltage. Figure 5. XRES Connection Diagram firmware fails to service it within a specified timeout period. reaching a debug breakpoint while executing privileged code. determine the cause of the reset. reference voltages may be used for the ADC reference voltage. which includes calibration and linearization.

Document Number: 002-30703 Rev. *F Page 16 of 73 PSoC 6 MCU: CY8C61x5 Datasheet Fixed-Function Digital Timer/Counter/Pulse-width Modulator (TCPWM) ■ The TCPWM supports the following operational modes: ❐ Timer-counter with compare ❐ Timer-counter with capture ❐ Quadrature decoding ❐ Pulse width modulation (PWM) ❐ Pseudo-random PWM ❐ PWM with dead time ■ Up, down, and up/down counting modes. ■ Clock prescaling (division by 1, 2, 4, ... 64, 128) ■ Double buffering of compare/capture and period values ■ Underflow, overflow, and capture/compare output signals ■ Supports interrupt on: ❐ Terminal count – Depends on the mode; typically occurs on overflow or underflow ❐ Capture/compare – The count is captured to the capture reg- ister or the counter value equals the value in the compare register ■ Complementary output for PWMs ■ Selectable start, reload, stop, count, and capture event signals for each TCPWM; with rising edge, falling edge, both edges, and level trigger options. The TCPWM has a Kill input to force outputs to a predetermined state. In this device there are: ■ Four 32-bit TCPWMs ■ Eight 16-bit TCPWMs Serial Communication Blocks (SCB) This product line has seven SCBs: ■ Six can implement either I2C, UART, or SPI. ■ One SCB (SCB #6) can operate in system Deep Sleep mode with an external clock; this SCB can be either SPI slave or I2C slave. I2C Mode: The SCB can implement a full multi-master and slave interface (it is capable of multimaster arbitration). This block can operate at speeds of up to 1 M bps (Fast Mode Plus). It also supports EZI2C, which creates a mailbox address range and effectively reduces I 2C communication to reading from and writing to an array in memory. The SCB supports a 256-byte FIFO for receive and transmit. The I 2C peripheral is compatible with I 2C standard-mode, Fast Mode, and Fast Mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. UART Mode: This is a full-feature UART operating at up to 8 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. A 256-byte FIFO allows much greater CPU service latencies to be tolerated. SPI Mode: The SPI mode supports full Motorola SPI, TI Secure Simple Pairing (SSP) (essentially adds a start pulse that is used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block supports an EZSPI mode in which the data interchange is reduced to reading and writing an array in memory. The SPI interface operates with a 25-MHz clock. USB Full-Speed Device Interface This product line incorporates a full-speed USB device interface. The device can have up to eight endpoints. A 512-byte SRAM buffer is provided and DMA is supported. Note: If the USB pins are not used, connect V DDUSB to ground and leave the P14.0/USBDP and P14.1/USBDM pins unconnected. Quad-SPI/Serial Memory Interface (SMIF) A serial memory interface is provided, running at up to 80 MHz. It supports single, dual, and quad SPI configurations, and supports up to four external memory devices. It supports two modes of operation: ■ Memory-mapped I/O (MMIO), a command mode interface that provides data access via registers and FIFOs ■ Execute in Place (XIP), in which AHB reads and writes are directly translated to SPI read and write transfers. In XIP mode, the external memory is mapped into the PSoC 6 MCU internal address space, enabling code execution directly from the external memory. To improve performance, a 4-KB cache is included. XIP mode also supports AES-128 on-the-fly encryption and decryption, enabling secured storage and access of code and data in the external memory. LCD This block drives LCD commons and segments; routing is available to most of the GPIOs. One to eight of the GPIOs must be used for commons, the rest can be used for segments. The LCD block has two modes of operation: high speed (8 MHz) and low speed (32 kHz). Both modes operate in system LP, ULP, and Deep Sleep modes, however the low-speed mode operates with reduced contrast in system Deep Sleep mode. The 8-MHz IMO is available in system Deep Sleep mode, and can be used to generate a clock for the L CD block. Review the number of common and segment lines, viewing angle requirements, and prototype performance, and then select the appropriate LCD clock frequency before using system Deep Sleep mode. SD Host Controller This product line contains one Secure Digital (SD) host controller. It provides communication with IoT connectivity devices such as Bluetooth, Bluetooth Low-Energy and WiFi radios, as well as combination devices. The controller also supports embedded MultiMediaCards (eMMC) and Secure Digital (SD) cards. Several bus speed modes under the SD specification are supported: ■ DS (default speed) ■ HS (high speed) ■ SDR12 (single data rate) ■ SDR25

The SD Host Controller complies with the following standards. the protocol and operations. (up to 32 GB) and SDXC (up to 2 TB). FIFO allowing double buffering of 512-byte blocks. are supported. DMA transfers are supported. interrupt request (IRQ) associated with it. operation, where the input voltage may be higher than V DDD. operating I2C bus without affecting its functionality. higher than the absolute maximum; see Electrical Specifications. not to crowbar any inputs and/or cause excess turn-on current. analog signals that may connect to an I/O pin. See also Table 5 for additional restrictions for ECO use. Table 6. DRIVE_SEL Values

Figure 7. CapSense Hardware Subsystem

Table 7. Packages and Pin Information

Table 7. Packages and Pin Information (continued)

Figure 9. Device Pinout for 100-TQFP Package

Figure 10. Device Pinout for 68-QFN Package[1] Note: If the USB pins are not used, connect VDDUSB to ground and leave the P14.0/USBDP and P14.1/USBDM pins unconnected.

  1. The center pad on the QFN package should be connected to PCB ground relative to device VDDx for best mechanical, thermal, and electrical performance. For more

information, see AN72845, Design Guidelines for QFN Devices.

The notation for a signal is of the form IPName[x].signal_name[u]:y. a particular signal name, y = Designates copies of the signal name. fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize use of on-chip resources. Table 8. Multiple Alternate Functions

Table 8. Multiple Alternate Functions (continued)

Analog and Smart I/O alternate port pin functionality is provided in Table 9. Table 9. Port Pin Analog, and Smart I/O Functions

by that pin is also shown, for example "VBACKUP, 6; I/O port P0". Figure 11. 100-TQFP Power Connection Diagram

1 KΩ at

100 MHz

Figure 12. 100-TQFP (No Buck) Power Connection Diagram

In the QFN package, all internal grounds are routed to the metal pad (epad) in the package. This pad must be grounded on the PCB. Figure 13. 68-QFN Power Connection Diagram Figure 14. 68-QFN (No Buck) Power Connection Diagram

Figure 15. 49-WLCSP Power Connection Diagram Figure 16. 49-WLCSP (No Buck) Power Connection Diagram

applied to this pin for correct device initialization and boot up. device package, it must be connected to VDDA. ■ VDDIO0: the supply for I/O ports 11 and 12. are not available depending on package. ■ VDDIO2: the supply for I/O ports 2 and 3. DDD. It powers I/O port 0[2]. Figure 17. Separate Battery Connection to VBACKUP be used as limited-capability GPIOs on I/O port 14. Table 10. I/O Power Supplies be connected together to a common ground. ■ VDD_NS: the regulator supply. are at the voltage levels required for proper operation. battery during product manufacture and storage. percentage of the rated working voltage.

14 V DDUSB –

  1. It is not available in the 49-WLCSP package. V DDD powers port 0.

All specifications are valid for –40 °C ≤ TA ≤ 85 °C and for 1.71 V to 3.6 V except where noted. generate the CPU clocks; FLL is not used when the CPU clock frequency is 8 MHz. Table 11. Absolute Maximum Ratings[3] Table 12. CPU Current Specifications Summary

  1. Usage above the absolute maximum conditions listed in Table 11 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended

Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.

Figure 18. Typical Device Currents vs. CPU Frequency; System Low Power (LP) Mode Table 13. Power Supply DC Specifications GPIO supply for Ports 9 and 10 when present.

Table 14. CPU Current and Transition Times CM0+ Sleep 25 MHz. With IMO and FLL. CM0+ Sleep 8 MHz.With IMO. While(1). CM0+ Sleep 75 MHz. IMO and PLL. CM0+ Sleep 100MHz. IMO and FLL. CM0+ Sleep 25MHz. IMO and FLL. CM0+ Sleep 8 MHz. IMO. Dhrystone.

50 MHz. With IMO and FLL. While (1). 100 MHz. With IMO and FLL. Dhrystone. CM4 Sleep 100 MHz, CM0+ Sleep 25 MHz. CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz. Table 14. CPU Current and Transition Times (continued)

SIDS5 I DD15 CM4 Off, CM0+ Sleep 8 MHz. With IMO. CM0+ Sleep 8 MHz. With IMO. While (1). CM0+ Sleep 8 MHz. With IMO. Dhrystone.

SIDLPS3 I DD22 CM4 Off, CM0+ Sleep 8 MHz. With IMO. ULP RANGE POWER SPECIFICATIONS (for VCCD = 0.9 V using the Buck). ULP mode is valid from –20 to +85 °C. CM0+ Sleep 25 MHz. With IMO and FLL. CM0+ Sleep 8 MHz. With IMO. While (1). CM0+ Sleep 25 MHz. With IMO and FLL. CM0+ Sleep 8 MHz. With IMO. Dhrystone. 25 MHz. With IMO and FLL. Write(1). 25 MHz. With IMO and FLL. Dhrystone. CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz.

SIDS10 I DD24 CM4 Off, CM0+ Sleep 8 MHz. With IMO. CM0+ Sleep 8 MHz. With IMO. While(1). CM0+ Sleep 8 MHz. With IMO. Dhrystone. SIDLPS7 I DD31 CM4 Off, CM0+ Sleep 8 MHz. With IMO. SRAM retention – 7 – µA Max value is at 60 °C. SRAM retention – 9 – µA Max value is at 60 °C.

Table 15. XRES DC Specifications Table 16. XRES AC Specifications Table 17. GPIO DC Specifications

Table 18. GPIO AC Specifications

1.71 V  V

Table 17. GPIO DC Specifications (continued)

Table 19. LP Comparator DC Specifications Table 20. LP Comparator AC Specifications

Table 21. Temperature Sensor Specifications Table 22. Internal Reference Specification Table 23. 12-bit SAR ADC DC Specifications SID95 A_CHNLS_S Number of channels - single-ended –– 1 6 8 full speed. SID97 A-MONO Monotonicity ––- Yes. SID98 A_GAINERR Gain error –– ± 0 . 2 % With external reference. Table 24. 12-bit SAR ADC AC Specifications

SID108C A_SAMP_4 Sample rate with Internal Reference. SID111A A_INL Integral non-linearity. SID111B A_INL Integral non-linearity. SID112A A_DNL Differential non-linearity. SID112B A_DNL Differential non-linearity. Table 24. 12-bit SAR ADC AC Specifications (continued) Table 25. CapSense Sigma-Delta (CSD) Specifications SNRC of the following is Ratio of counts of finger to noise. Guaranteed by characterization.

Table 25. CapSense Sigma-Delta (CSD) Specifications (continued)

SID321 IDACGAIN Full-scale error less offset – – ±15 % LSB = 2.4-µA typ. IDAC2 in Low mode – – 9.2 LSB LSB = 37.5-nA typ. SID325 CMOD External modulator capacitor. – 2.2 – nF 5-V rating, X7R or NP0 cap. Table 26. CSD ADC Specifications

2.2 V),

2.7 V),

setting. Settling to within 0.05%. conversion rate = Fhclk / (2"(N + 2)). Does not include acquisition time. conversion rate = Fhclk / (2"(N + 2)). Does not include acquisition time. Table 26. CSD ADC Specifications (continued)

Table 27. Timer/Counter/PWM (TCPWM) Specifications mode of operation is selected. Table 28. Serial Communication Block (SCB) Specifications SID152 II2C4 I2C enabled in Deep Sleep mode – – 1.7 µA At 60°C.

Fixed SPI AC Specifications for LP Mode (1.1 V) unless noted otherwise. Fixed SPI Master mode AC Specifications for LP Mode (1.1 V) unless noted otherwise. Fixed SPI Slave mode AC Specifications for LP Mode (1.1 V) unless noted otherwise. MISO valid after Sclock driving edge in Ext. Table 28. Serial Communication Block (SCB) Specifications (continued)

Table 29. LCD Direct Drive DC Specifications Table 30. LCD Direct Drive AC Specifications

Table 31. Flash Specifications[6]

  1. It can take as much as 16 millis econds to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied

on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.

Table 32. System Resources

Table 33. SWD and Trace Specifications SID214L F_SWDCLK2L 1.7 V VDDD  3.6 V – – 12 MHz ULP Mode. 2/1 ns respectively – – 50 MHz LP Mode. VDD = 1.1 V. Table 34. IMO DC Specifications Table 35. IMO AC Specifications Table 36. ILO DC Specification Table 37. ILO AC Specifications

Table 38. ECO Specifications SID317 F_MHz Crystal frequency range 16 – 35 MHz Some restrictions apply. Table 39. External Clock Specifications Table 40. PLL Specifications SID307P PLL_IDD PLL current – 0.55 1.1 mA Typ. at 100 MHz out.

  1. As an example, if the clk_pat h[1] source is changed from the IMO to the FLL (see Figure 3) then clk1 is the IMO and clk2 is the FLL.

Table 41. Clock Source Switching Time

Table 42. Frequency Locked Loop (FLL) Specifications SID450 FLL_RANGE Input frequency range. SID451 FLL_OUT_DIV2 Output frequency range. SID451A FLL_OUT_DIV2 Output frequency range. Table 43. USB Specifications (USB requires LP Mode 1.1-V internal supply)

Table 44. QSPI Specifications SMIF QSPI Specifications. All specs with 15-pF load. Measured from 50% to 50% waveform transitions. SID390QU Fsmifclocku SMIF QSPI output clock frequency – – 50 MHz ULP mode (0.9 V). Table 45. Smart I/O Specifications Table 46. SD Host Controller and eMMC Specifications

Table 46. SD Host Controller and eMMC Specifications (continued)

SID_SD440 SD_CLK Interface clock pe riod (LP mode) – – 40 MHz (25-ns pe riod).

Table 47. JTAG Boundary Scan

Table 47. JTAG Boundary Scan (continued)

Document Number: 002-30703 Rev. *F Page 64 of 73 PSoC 6 MCU: CY8C61x5 Datasheet

Ordering Information

Table 53 lists the CY8C61x5 part numbers and features. See also the product selector guide. Note: In PSoC 61 the Cortex M0+ is reserved for system functions, and is not available for applications. Table 48. Ordering Information

Document Number: 002-30703 Rev. *F Page 65 of 73 PSoC 6 MCU: CY8C61x5 Datasheet PSoC 6 MPN Decoder CY XX 6 A B C DD E - FF G H I JJ K L Field Description Values Meaning Field Description Values Meaning CY Cypress CY Cypress E Temperature Range C Consumer XX Firmware 8C Standard I Industrial B0 “Secure Boot” v1 Q Extended Industrial S0 “Standard Secure” - AWS FF Feature Code Cypress internal

6 Architecture 6 PSoC 6 S2-S6

0 Value BL Integrated Bluetooth LE

1 Programmable GC P U C o r e F Single Core

2 Performance D Dual Core

3 Connectivity H Attributes Code 0–9 Feature set

4 Secured

(Flash/SRAM) 0-3 Reserved JJ Engineering sample (optional) ES Engineering samples or not 4 256K/128K K Die Revision (optional) Base 5 512K/256K A1-A9 Die revision 6 512K/128K L Tape/Reel Shipment (optional) T Tape and Reel shipment 7 1024K/288K 8 1024K/512K

9 Reserved

AZ, AX TQFP LQ QFN BZ BGA FM M-CSP FN, FD, FT WLCSP

This product line is offered in 100 TQFP, 68 QFN, and 49 WLCSP packages. Table 49. Package Dimensions Table 50. Package Characteristics Table 51. Solder Reflow Peak Temperature Table 52. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

100 TQFP and 68 QFN MSL 3

49 WLCSP MSL 1

Figure 21. 49-Ball WLCSP Package Diagram

Document Number: 002-30703 Rev. *F Page 69 of 73 PSoC 6 MCU: CY8C61x5 Datasheet Acronyms Acronym Description 3DES triple DES (data encryption standard) ADC analog-to-digital converter ADMA3 advanced DMA version 3, a Secure Digital data transfer mode AES advanced encryption standard AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm data transfer bus AMUX analog multiplexer AMUXBUS analog multiplexer bus API application programming interface Arm ® advanced RISC machine, a CPU architecture BGA ball grid array BOD brown-out detect BREG backup registers BWC backward compatibility (eMMC data transfer mode) CAD computer aided design CCO current controlled oscillator ChaCha a stream cipher CM0+ Cortex-M0+, an Arm CPU CM4 Cortex-M4, an Arm CPU CMAC cypher-based messge authentication code CMOS complementary metal-oxide-semicondutor, a process technology for IC fabrication CMRR common-mode rejection ratio CPU central processing unit CRC cyclic redundancy check, an error-checking protocol CSD CapSense Sigma-Delta CSV clock supervisor CSX Cypress mutual capacitance sensing method. See also CSD CTI cross trigger interface DAC digital-to-analog converter, see also IDAC, VDAC DAP debug access port DDR double data rate DES data encryption standard DFT design for test DMA direct memory access, see also TD DNL differential nonlinearity, see also INL DSI digital system interconnect DU data unit DW data wire, a DMA implementation ECC error correcting code ECC elliptic curve cryptography ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory EMI electromagnetic interference eMMC embedded MultiMediaCard ESD electrostatic discharge ETM embedded trace macrocell FIFO first-in, first-out FLL frequency locked loop FPU floating-point unit FS full-speed GND Ground GPIO general-purpose input/output, applies to a PSoC pin HMAC Hash-based message authentication code HSIOM high-speed I/O matrix I/O input/output, see also GPIO, DIO, SIO, USBIO I 2C, or IIC Inter-Integrated Circuit, a communications protocol I2S inter-IC sound IC integrated circuit IDAC current DAC, see also DAC, VDAC IDE integrated development environment ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO INL integral nonlinearity, see also DNL IOSS input output subsystem IoT internet of things IPC inter-processor communication IRQ interrupt request ISR interrupt service routine ITM instrumentation trace macrocell JTAG Joint Test Action Group LCD liquid crystal display LIN Local Interconnect Network, a communications protocol LP low power LS low-speed LUT lookup table LVD low-voltage detect, see also LVI LVI low-voltage interrupt LVTTL low-voltage transistor-transistor logic Acronym Description

Document Number: 002-30703 Rev. *F Page 70 of 73 PSoC 6 MCU: CY8C61x5 Datasheet MAC multiply-accumulate MCU microcontroller unit MISO master-in slave-out MMIO memory-mapped input output MOSI master-out slave-in MPU memory protection unit MSL moisture sensitivity level Msps million samples per second MTB micro trace buffer MUL multiplier NC no connect NMI nonmaskable interrupt NVIC nested vectored interrupt controller NVL nonvolatile latch, see also WOL OTP one-time programmable OVP over voltage protection OVT overvoltage tolerant PASS programmable analog subsystem PCB printed circuit board PCM pulse code modulation PDM pulse density modulation PHY physical layer PICU port interrupt control unit PLL phase-locked loop PMIC power management integrated circuit POR power-on reset PPU peripheral protection unit PRNG pseudo random number generator PSoC ® Programmable System-on-Chip™ PSRR power supply rejection ratio PWM pulse-width modulator QD quadrature decoder QSPI quad serial peripheral interface RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square ROM read-only memory RSA Rivest–Shamir–Adleman, a public-key cryptog- raphy algorithm RTC real-time clock RWW read-while-write RX receive S/H sample and hold Acronym Description SAR successive approximation register SARMUX SAR ADC multiplexer bus SC/CT switched capacitor/continuous time SCB serial communication block SCL I 2C serial clock SD Secure Digital SDA I 2C serial data SDHC Secure Digital host controller SDR single data rate Sflash supervisory flash SHA secure hash algorithm SINAD signal to noise and distortion ratio SMPU shared memory protection unit SNR signal-to-noise ration SOF start of frame SONOS silicon-oxide-nitride-oxide-silicon, a flash memory technology SPI Serial Peripheral Interface, a communications protocol SRAM static random access memory SROM supervisory read-only memory SRSS system resources subsystem SWD serial wire debug, a test protocol SWJ serial wire JTAG SWO single wire output SWV single-wire viewer TCPWM timer, counter, pulse-width modulator TDM time division multiplexed THD total harmonic distortion TQFP thin quad flat package TRM technical reference manual TRNG true random number generator TX transmit UART Universal Asynchronous Transmitter Receiver, a communications protocol ULP ultra-low power USB Universal Serial Bus WCO watch crystal oscillator WDT watchdog timer WIC wakeup interrupt controller WLCSP wafer level chip scale package XIP execute-in-place XRES external reset input pin Acronym Description

Table 53. Units of Measure Table 53. Units of Measure (continued)

Document Number: 002-30703 Rev. *F Page 72 of 73 PSoC 6 MCU: CY8C61x5 Datasheet

Revision History

Description Title: PSoC 6 MCU: CY8C61x5 Datasheet Document Number: 002-30703 Revision ECN Submission Date Description of Change ** 6894902 07/29/2020 New datasheet. *A 6981432 11/16/2020 Updated Flexible Clocking Options, Block Diagram, and CPUs. Updated list of application notes and links in PSoC 6 MCU Resources. Removed Secure Boot information. Updated ModusToolbox Software. Updated Quad-SPI (QSPI)/Serial Memory Interface (SMIF). Added InterProcessor Communication (IPC). Updated Analog Subsystem diagram. Updated Direct Memory Access (DMA) Controllers. Updated VDDA bullet in Power Supply Considerations. Updated the XRES bullet in Reset, SID15 Description and Conditions, and System Resources (Power-On-Reset specifications). Updated SID7A conditions, SID7D description, and SID8 conditions. Integrated ECO erratum into External Crystal Oscillators. Added ECO Usage Guidelines table. *B 7139142 05/17/2021 Updated Security terminology to Infineon standards. Changed BLE references to Bluetooth LE. Added Table 14 and Figure 33 in Electrical Specifications *C 7487079 12/06/2021 Updated Figure 6. Added note regarding unused USB pins in USB Full-Speed Device Interface, Power Supply Considerations, and Pinouts. Updated SIDC1 description. Updated details/conditions for SID7A. Updated SID325U, SID328, and SID329 description. *D 7750278 04/12/2022 Updated eFuse description in the Memory section. *E 7758801 05/05/2022 Corrected typo in Figure 11, Figure 12, Figure 13, and Figure 14. *F 7788568 10/26/2022 Added device identification and revision information in Features. Added spec SID304P. Updated PLL Specifications and Clock System. Updated Protection Units.

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