AMMC-5040 AVAGO | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 10

Technical content

Features

  • Frequency range: 20 – 45 GHz
  • High gain: 25 dB
  • Gain flatness: ±1.5 dB
  • Return loss: Input: 17 dB, Output: 11 dB
  • Output power: P-1dB = 21 dBm at 38 GHz P-3dB = 22.5 dBm at 38 GHz

Applications

  • Broadband gain block
  • Broadband driver amplifier
  • Point-to-point radio
  • LMDS
  • EW
  • Instrumentation
  • Frequency Multiplier (X2 and X3) Absolute Maximum Ratings[1] Symbol Parameters/Conditions Units Min. Max. VD1,2-3-4 Drain Voltage V 5 VG1,2-3-4 Gate Voltage V -3.0 0.5 IDD Total Drain Current mA 550 Pin CW Input Power dBm 21 Tch Operating Channel Temperature °C +160 Tb Operating Backside Temperature °C -55 +75 Tstg Storage Temperature °C -65 +165 Tmax Max. Assembly Temp (60 sec max) °C +300 Notes: 1. Operation in excess of any one of these conditions may result in permanent damage to this device. Chip Size: 1720 x 760 µm (67.7 x 29.9 mils) Chip Size Tolerance: ±10 µm (±0.4 mils) Chip Thickness: 100 ± 10 µm (4 ± 0.4 mils) Pad Dimensions: 75 x 75 µm (3 ± 0.4 mils)

AMMC-5040 DC Specifications/Physical Properties[1] Symbol Parameters and Test Conditions Units Min. Typ. Max. VD1,2-3-4 Drain Supply Operating Voltage V 2 4.5 5 ID1 First Stage Drain Supply Current (VDD = 4.5 V, VG1 = -0.5 V) mA 50 ID2-3-4 Total Drain Supply Current for Stages 2, 3 and 4 (VDD = 4.5 V, VGG= -0.5 V) mA 225 VG1,2-3-4 Gate Supply Operating Voltages (IDD = 300 mA) V -0.45 VP Pinch-off Voltage (VDD = 4.5 V, IDD < 10 mA) V -1.5 θch-b Thermal Resistance[2] (Backside Temp. Tb = 25°C) °C/W 49 Notes: 1. Measured in wafer form with Tchuck = 25°C (except θch-bs.) 2. Channel-to-backside Thermal Resistance (θch-b) = 58°C/W at Tchannel (Tc) = 150°C as measured using the liquid crystal method. Thermal Resistance at backside temperature (Tb) = 25°C calculated from measured data. RF Specifications[3,4] (VDD = 4.5V, IDD (Q) = 300 mA, Z0 = 50Ω) Units Broadband Narrow Band Typical Performance GHz 3– 40 1–4 7–9 37–40 40–45 Symbol Parameters and Test Conditions Min. Typ. Typical |S21|2 Small-signal Gain dB 20 25 25.5 25 22.4 21.3 RLin Input Return Loss dB 15 17 17 18 21 17 RLout Output Return Loss dB 8 11 10 14 13 13 P-1dB Output Power @ 1 dB Gain Compression dBm 19.5 20 22.5 21 20 f = 22 GHz P-3dB Output Power @ 3 dB Gain Compression, f = 22 GHz dBm 21 21.6 23.5 22.5 21.5 OIP3 Output 3rd Order Intercept Point, dBm 30 29 29 31 27 ∆f = 2 MHz, Pin = -8 dBm, f = 22 GHz |S12|2 Isolation dB 40 55 55 55 55 55 Notes: 3. Data measured in wafer form, Tchuck = 25°C. 4. 100% on-wafer RF test is done at frequency = 24, 27, 29, 37 and 40 GHz, except as noted.

AMMC-5040 RF Performance for Frequency Multiplier Applications Typical Performance as a X Frequency Multiplier, Input Power Optimized for Conversion Gain [1] Input Frequency Input Power Output Frequency Output Power Conversion Gain (GHz) (dBm) (GHz) (dBm) (dB) 10 6 20 18.2 12.2 11 6 22 18.9 12.9 12 6.5 24 20.5 14.0 13 6.5 26 20.8 14.3 14 7.5 28 20.0 12.4 15 7.5 30 19.6 12.1 16 7.5 32 18.0 10.5 17 7.5 34 16.0 8.5 18 7 36 11.7 4.7 19 7 38 7.1 0.1 20 3 40 7.0 4.0 21 5 42 10.7 5.7 22 5 44 11.3 6.3 23 5 46 11.7 6.7 Typical Performance as a X Frequency Multiplier, Input Power Optimized for Output Power [1] Input Frequency Input Power Output Frequency Output Power Conversion Gain (GHz) (dBm) (GHz) (dBm) (dB) 10 10 20 20.2 10.2 11 10 22 20.9 10.9 12 10 24 22.0 12.0 13 9.5 26 22.2 12.7 14 9.5 28 20.8 11.3 15 9.5 30 20.6 11.1 16 9.5 32 19.0 9.5 Typical Performance as a X3 Frequency Multiplier [1] Input Frequency Input Power Output Frequency Output Power Conversion Gain (GHz) (dBm) (GHz) (dBm) (dB) 7 14.3 21 19.6 5.3 8 14.2 24 20.6 6.4 9 15.1 27 20.0 4.9 10 15.9 30 18.6 2.6 11 15.8 33 16.0 0.2 12 15.8 36 14.7 -1.0 13 15.7 39 12.9 -2.7 14 15.6 42 10.0 -5.5 Note: 1. T = 25°C. Refer to “Multiplier Biasing and Operation” section for bias conditions for operation as a multiplier.

AMMC-5040 Typical Scattering Parameters[1] (Tchuck = 25°C, VDD = 4.5V, IDD = 300 mA, Zin = Zout = 50Ω) Freq. S11 S1 S1 S GHz dB Mag Ang dB Mag Ang dB Mag Ang dB Mag Ang Note: 1. Data obtained from on-wafer measurements.

AMMC-5040 Typical Scattering Parameters[1] (Tchuck = 25°C, VDD = 4.5V, IDD = 350 mA, Zin = Zout = 50Ω) Freq. S11 S1 S1 S GHz dB Mag Ang dB Mag Ang dB Mag Ang dB Mag Ang Note: 1. Data obtained from on-wafer measurements.

The recommended DC bias condition for the AMMC-5040 is with all four drains connected to a single 4.5V supply and all four gates connected to an adjustable negative voltage supply as shown in Figure 15. The gate voltage is adjusted for a total drain supply current of typically 300 mA. Figures 1–12 can be used to help estimate the minimum drain voltage and current necessary for a given RF gain and output power. As shown in Figure 13, the second, third, and fourth stage DC drain bias lines are connected internally and therefore require only a single bond wire. An additional bond wire is needed for the first stage DC drain bias, Vd1. Only the third and fourth stage DC gate bias lines are con- nected internally. A total of three DC gate bond wires are required: one for Vg1, one for Vg2, and one for the Vg3/Vg4 connection. The internal matching circuitry at the RF input creates a 50-ohm DC and RF path to ground. A blocking capacitor should be used at the RF input. Any DC voltage applied to the RF input must be maintained below 1V. The RF output is AC coupled. No ground bond wires are needed since the ground connection is made by means of plated through via holes to the backside of the chip. Frequency Multiplier Biasing and Operation The AMMC-5040 can also be used as a frequency doubler, tripler or quadrupler. A s a f re q u e n c y d o u b l e r, t h e A M M C - 5 0 4 0 p ro- vides conversion gain for input signals in the 10–23 GHz frequency range for output frequencies of 20–46 GHz. Similarly, 5–10 GHz signals can be quadrupled up to 20–40 GHz with some conversion loss. Optimum conversion efficiency as a doubler is obtained with an input power level of 3–8 dBm. For use as a fre - quency tripler, an input power level of 14–16 dBm is recommended. Frequency multiplication is achieved by reducing the bias on the first stage FET to efficiently generate harmonics. The remaining three stages are then used to provide amplification. While many bias schemes may be used to generate and amplify the desired harmonics within the AMMC-5040, the following information is suggested as a starting point for multiplier applications. Frequency doubling or quadrupling (generation of even harmonics) is accomplished by biasing the first stage FET at pinch-off by setting Vg1 = Vp ≈ -1.1 volts. The remaining three stages are biased for nor- mal amplification, e.g., Vgg is adjusted such that Id2 + Id3 + Id4 ≈ 250 mA. The drain voltage, Vdd, for all four stages should be 3.5 – 4.5 volts. The assembly diagram shown in Figure 16 can be used as a guideline. To operate the AMMC-5040 as a frequency tripler (odd harmonic), the device is biased as shown in Figure 17. The drain voltage for the first stage FET is biased separately with Vd1 reduced to 1.1 - 1.2 volts. The drain voltage for the remaining three stages, Vd2, Vd3, and Vd4, should be 3.5 - 4.5 volts. All four gate voltages, Vgg, are set to ap - proximately –0.6 volts. If desired, Vgg can be adjusted to minimize second harmonics. Improved multiplier perfor- mance can be obtained by biasing both the gate and drain voltages for the first stage separately from stages 2–4. In all cases, Cb > 100 nF to assure stability. Assembly Techniques The chip should be attached directly to the ground plane using either a fluxless AuSn solder preform or electrically conductive epoxy [1]. For conductive epoxy, the amount should be just enough to provide a thin fillet around the bottom perimeter of the die. The ground plane should be free of any residue that may jeopardize electrical or mechanical attachment. Caution should be taken to not exceed the Absolute Maximum Rating for assembly tem- perature and time. Thermosonic wedge bonding is the preferred method for wire attachment to the bond pads. The RF connections should be kept as short as possible to minimize inductance. Gold mesh[2] or double-bonding with 0.7 mil gold wire is recommended. Mesh can be attached using a 2 mil round tracking tool and a tool force of approximately 22 grams with an ultra- sonic power of roughly 55 dB for a duration of 76 ± 8 mS. A guided wedge at an ultrasonic power level of 64 dB can be used for the 0.7 mil wire. The recommended wire bond stage temperature is 150 ± 2°C. The chip is 100 mm thick and should be handled with care. This MMIC has exposed air bridges on the top surface. Handle at edges or with a custom collet (do not pick up die with vacuum on die center.) This MMIC is also static sensitive and ESD handling precau- tions should be taken. For more information, see Avago Application Note 54 “GaAs MMIC ESD, Die Attach and Bonding Guidelines. ” Notes: 1. Ablebond 84-1 LM1 silver epoxy is recommended. 2. Buckbee-Mears Corporation, St. Paul, MN, 800-262-3824