AMMC-5033 AVAGO | Alldatasheet
Document overview
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- PDF pages: 9
Technical content
Features
- Wide frequency range: 17.7 – 32 GHz
- High power: P-1dB @ 25 GHz = 27 dBm
- High gain: 20 dB
- Return loss: Input: -13 dB, Output: –20 dB
- Integrated RF power detector
Applications
- Designed for use in transmitters that operate in various frequency bands between 17.7 GHz and 32 GHz.
- Can be driven by the AMMC-5040 (20-40 GHz) or the AMMC-5618 (6-20 GHz) MMIC amplifiers, increasing the power handling capability of transmitters requiring linear operation. Chip Size: 2730 x 1300 µm (108 x 51.6 mils) Chip Size Tolerance: ± 10 µm (±0.4 mils) Chip Thickness: 100 ± 10 µm (4 ± 0.4 mils) Pad Dimensions: 80 x 80 µm (2.95 ± 0.4 mils) Note: These devices are ESD sensitive. The following precautions are strongly recommended: Ensure that an ESD approved carrier is used when dice are transported from one destination to another. Personal grounding is to be worn at all times when handling these devices. AMMC-5033 17.7 - 32 GHz Power Amplifier Data Sheet Symbol Parameters/Conditions Units Min. Max. Vd1,2 Positive Drain Voltage V 7 Vg1, Vgg Gate Supply Voltage V -3 0.5 Det Bias Applied Detector Bias V 7 (Optional) Id1 First Stage Drain Current mA 320 Id2 Second Stage Drain Current mA 640 Pin CW Input Power dBm 23 Tch Operating Channel Temp. °C +150 Tstg Storage Case Temp. °C -65 +150 Tmax Maximum Assembly Temp. °C +300 (60 sec max) Note: 1. Operation in excess of any one of these conditions may result in permanent damage to this device.
AMMC-5033 DC Specifications/Physical Properties [1] Symbol Parameters and Test Conditions Units Min. Typ. Max. Id1 First Stage Drain Supply Current mA 280 320 (Vd1 = 3.5 V, Vg1 = Open, Vgg set for Id2 Typical) Id2 Second Stage Drain Supply Current V 500 (Vd2 = 5 V, Vg1 = Open, Vgg set for Id2 Typical) Vgg Gate Supply Operating Voltage V -0.75 -0.6 -0.4 (Id1(Q) + Id2(Q) = 780 (mA)) DETBias Detector Bias Voltage (Optional) V Vd2 θc1(ch-bs) First Stage Thermal Resistance[2] °C/W 31 (Backside Temperature, Tb = 25°C) θc2(ch-bs) Second Stage Thermal Resistance[2, 3] °C/W 19 (Backside Temperature, Tb = 25°C) Notes: 1. Backside temperature Tb = 25°C unless otherwise noted. 2. Channel-to-backside Thermal Resistance (θch-b) = 42°C/W at Tchannel (Tc) = 150°C as measured using infrared microscopy. Thermal Resis- tance at backside temperature (Tb) = 25°C calculated from measured data. 3. Channel-to-backside Thermal Resistance (θch-b) = 24°C/W at Tchannel (Tc) = 150°C as measured using infrared microscopy. Thermal Resis- tance at backside temperature (Tb) = 25°C calculated from measured data. AMMC-5033 RF Specifications[4, 5] Tb = 25°C, Vd1 = 3.5 V, Vd2 = 5 V, Id1(Q) = 280 mA, Id2(Q) = 500 mA, Zo = 50 Ω Lower Band Mid Band Upper Band Specifications Specifications Specifications Parameters and (17.7 - 21 GHz) (21 - 26.5 GHz) (26.5 - 32 GHz) Gain Small-Signal Gain[5] dB 20 22 17.5 20 16.5 18.5 P-1dB Output Power at 1dB Gain dB 23.5 25 25.5 27 25 26.5 Compression[6] P-3dB Output Power at 3dB Gain dB 27 28 27 Compression[6] OIP3 Output Third Order Intercept dBm 27 29 29.5 32 29 32 Point;[6]; ∆f = 2 MHz; Pin = +2 dBm RLin Input Return Loss[5] dB 11.5 13.5 11 13 11 13 RLout Output Return Loss[5] dB 14 20 14 19 15 22 Isolation Min. Reverse Isolation dB 47 48 46 Notes: 4. Data measured in wafer form Tb = 25°C. 5. 100% on-wafer RF test is done at frequency = 17.7, 21, 26.5 and 32 GHz. 6. 100% on-wafer test frequency = 17.7, 26.5 and 32 GHz.
Typical Scattering Parameters[1] (Tb = 25°C, Vd1 = 3.5 V, ID1 = 280 mA, Vd2 = 5 V, ID2 = 500 mA, Zin = Zout = 50 Ω) Freq S11 S21 S12 S22 [GHz] dB Mag Phase dB Mag Phase dB Mag Phase dB Mag Phase Note: 1. Data obtained from on-wafer measurements.
The recommended quiescent DC bias condition for optimum efficiency, performance, and reliability is Vd1 = 3.5 volts and V d2 = 5 volts with V gg set for Id1 + I d2 = 780 mA (no connection to V g1). This bias ar - rangement results in default quiescent drain currents Id1 = 280 mA, I d2 = 500 mA. A single DC gate supply connected to V gg will bias all gain stages. If operation with both V d1 and V d2 at 5 volts is desired, an additional wire bond connection from the V g1 pad to V gg external bypass chip capacitor (shorting V g1 to Vgg) will balance the current in each gain stage. V gg (= Vg1) can be adjusted for I d1 + I d2 = 780 mA. Muting can be accomplished by setting V g1 and/or Vgg to the pinch- off voltage V p. An optional output power detector network is also provided. Detector sensitivity can be adjusted by bias - ing the diodes with typically 1 to 5 volts applied to the Det- bias terminal. Simply connecting Det-Bias to the Vd2 supply is a convenient method of biasing this detector network. The differential voltage between the Det-Ref and Det-Out pads can be correlated with the RF power emerging from the RF output port. The detected volt - age is given by: V = (V ref - Vdet) - V ofs Where V ref is the voltage at the DET_REF port, V det is a voltage at the DET_OUT port, and V ofs is the zero-in - put-power offset voltage. There are three methods to calculate Vofs: 1. Vofs can be measured before each detector measure - ment (by removing or switching off the power source and measuring Vref - Vdet ). This method gives an error due to temperature drift of less than 0.0002 dB/°C. 2. Vofs can be measured at a single reference temperature. The drift error will be less than 0.25 dB. 3. Vofs can either be characterized over temperature and stored in a lookup table, or it can be measured at two temperatures and a linear fit used to calculate Vofs at any temperature. This method gives an error close to method #1. With reference to Figure 13, the RF input is DC coupled to a shunt 50 Ω resistor but it is DC blocked to the input of the first stage. The RF output is DC blocked to the output of the second stage, however, it is DC coupled to the detector bias circuit. If the output detector is biased using the on-chip optional Det-Bias network, an external DC blocking capacitor may be required at the RF Output port. No ground wires are needed since ground connections are made with plated through-holes to the backside of the device. Assembly Techniques The backside of the AMMC- 5033 chip is RF ground. For microstripline applications, the chip should be attached directly to the ground plane (e.g., circuit carrier or heat - sink) using electrically conductive epoxy. [1] For best performance, the topside of the MMIC should be brought up to the same height as the circuit sur - rounding it. This can be accomplished by mounting a gold plated metal shim (same length and width as the MMIC) under the chip, which is of the correct thickness to make the chip and adjacent circuit coplanar. The amount of epoxy used for chip and or shim at - tachment should be just enough to provide a thin fillet around the bottom perimeter of the chip or shim. The ground plane should be free of any residue that may jeopardize electrical or mechanical attachment. The location of the RF bond pads is shown in Figure 14. Note that all the RF input and output ports are in a Ground-Signal-Ground configuration. RF connections should be kept as short as reasonable to minimize performance degradation due to undesirable series inductance. A single bond wire is sufficient for signal connections, however double-bonding with 0.7 mil gold wire or the use of gold mesh[2] is recommended for best performance, especially near the high end of the frequency range. Thermosonic wedge bonding is the preferred method for wire attachment to the bond pads. Gold mesh can be attached using a 2 mil round tracking tool and a tool force of approximately 22 grams with an ultrasonic power of roughly 55 dB for a duration of 76 ± 8 mS. A guided wedge at an ultrasonic power level of 64 dB can be used for the 0.7 mil wire. The recommended wire bond stage temperature is 150 ± 2°C. Caution should be taken to not exceed the Absolute Maximum Rating for assembly temperature and time. The chip is 100 µm thick and should be handled with care. This MMIC has exposed air bridges on the top surface and should be handled by the edges or with a custom collet (do not pick up die with vacuum on die center.) This MMIC is also static sensitive and ESD handling precautions should be taken. Notes: 1. Ablebond 84-1 LM1 silver epoxy is recommended. 2. Buckbee-Mears Corporation, St. Paul, MN, 800-262-3824
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Figure 15. AMMC-5033 assembly diagram
- 1µF capacitors on gate and drain lines not shown required.