AMMC-5024_08 AVAGO | Alldatasheet
Document overview
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Technical content
Features
- Wide frequency range: 30 KHz – 40 GHz
- High gain: 16 dB
- Gain flatness: ±0.75 dB
- Return loss: Input: 13 dB, Output: 13 dB
- Medium power: P-1dB = 22.5 dBm at 22 GHz
- Low noise figure: 4.6 dB at 26 GHz
Applications
- Communication systems
- Microwave instrumentation
- Optical systems
- Broadband applications requiring flat gain and group delay with excellent input and output port matches over the 30 KHz and 40 GHz frequency range Absolute Maximum Ratings[1] Symbol Parameters/Conditions Units Min. Max. Vdd Positive Drain Voltage V 10 Idd Total Drain Current mA 340 Vg1 First Gate Voltage V -9.5 0 Ig1 First Gate Current mA -38 +1 Vg2 Second Gate Voltage V -3.5 +4 Ig2 Second Gate Current mA -20 Pin CW Input Power dBm 17 Tch Operating Channel Temperature °C +150 Tb Operating Backside Temperature °C -55 Tstg Storage Temperature °C -65 +165 Tmax Max. Assembly Temp (60 sec max) °C +300 Notes: 1. Absolute maximum ratings for continuous operation unless otherwise noted.
Description
Avago Technologies' AMMC-5024 is a broadband PHEMT GaAs MMIC TWA designed for medium output power and high gain over the full 30 KHz to 40 GHz frequency range. The design employs a 9-stage,cascade-connected FET structure to ensure flat gain and power as well as uni- form group delay. E-beam lithography is used to produce uniform gate lengths of 0.15 mm and MBE technology as- sures precise semiconductor layer control. For improved reliability and moisture protection, the die is passivated at the active areas. Chip Size: 2350 x 1050 µm (92.5 x 41.3 mils) Chip Size Tolerance: ±10 µm (±0.4 mils) Chip Thickness: 100 ± 10 µm (4 ± 0.4 mils) Pad Dimensions: 80 x 80 µm (2.95 ± 0.4 mils)
AMMC-5024 DC Specifications/Physical Properties [1] Symbol Parameters and Test Conditions Units Min. Typ. Max. Idss Saturated Drain Current (V dd=7 V, Vg1=0 V, Vg2=open circuit) mA 265 350 385 Vp First Gate Pinch-off Voltage (Vdd=7 V, Idd=30 mA, Vg2=open circuit) V -8.2 Vg2 Second Gate Self-bias Voltage (Vdd=7 V, Idd = 200 mA, Vg2=open circuit) V 2.75 Idsmin First Gate Minimum Drain Current mA 47 (Vg1) (V dd =7 V, Vg1=-7 V, Vg2=open circuit) Idsmin Second Gate Minimum Drain Current mA 105 (Vg2) (V dd =7 V, Vg1=0 V, Vg2= -3.5 V) θch-b Thermal Resistance[2] (Backside temperature, Tb = 25°C) °C/W 16.2 RF Specifications for High Gain and Low Power Applications [2, 3] (Vdd=4 V, Idd(Q)= 160 mA, Zin= Zo =50Ω) Symbol Parameters and Test Conditions Units Min. Typ. Max. |S21|2 Small-signal Gain dB 17.5 ∆|S21|2 Small-signal Gain Flatness dB ±1.5 RLin Minimum Input Return Loss dB 13 RLout Minimum Output Return Loss dB 13 |S12|2 Isolation dB 30 P-1dB Output Power @ 1 dB Gain Compression f = 22 GHz dBm 17.3 Psat Saturated Output Power f = 22 GHz dBm 20.5 OIP3 Output 3 rd Order Intercept Point, dBm 22.5 Rfin1 = Rfin2 = 2 dBm, f = 22 GHz, ∆f = 2 MHz NF Noise Figure f = 26 GHz dB 3.7 f = 40 GHz dB 5.5 Notes: 1. Backside temperature Tb = 25°C unless otherwise noted. 2. Channel to board Thermal Resistance is measured using QFI method. 3. 100% on-wafer RF test is done at frequency = 2, 10, 20, 30 and 40 GHz, except as noted. RF Specifications for High Power Applications [2, 3] (Vdd=7 V, Idd(Q)= 200 mA, Zin= Zo =50Ω Symbol Parameters and Test Conditions Units Min. Typ. Max. |S21|2 Small-signal Gain dB 14 16 18 ∆|S21|2 Small-signal Gain Flatness dB ±0.75 ±2 RLin Input Return Loss dB 12 16.9 RLout Output Return Loss dB 10 16.8 |S12|2 Isolation dB 26 28 P-1dB Output Power @ 1 dB Gain Compression f = 22 GHz dBm 21 22.5 Psat Saturated Output Power f = 22 GHz dBm 23 24.5 OIP3 Output 3 rd Order Intercept Point, dBm 27 30 Rfin1 = Rfin2 = 2 dBm, f = 22 GHz, ∆f = 2 MHz NF Noise Figure (V ds = 3V, Ids = 140 mA) f = 26 GHz dB 4.6 6.5 f = 40 GHz dB 7.2 9
AMMC-5024 Typical Scattering Parameters[1] (Tchuck = 25°C, VDD = 7V, IDD = 200 mA, Z in = Zout = 50Ω) Freq. S11 S21 S12 S22 GHz dB Mag Phase dB Mag Phase dB Mag Phase dB Mag Phase Note: 1. Data obtained from on-wafer measurements.
AMMC-5024 Typical Scattering Parameters [1] (Tchuck = 25°C, VDD = 4V, IDD = 160 mA, Z in = Zout = 50Ω) Freq. S11 S21 S12 S22 GHz dB Mag Phase dB Mag Phase dB Mag Phase dB Mag Phase Note: 1. Data obtained from on-wafer measurements.
AMMC-5024 is biased with a single positive drain supply (Vdd) a negative gate supply (Vg1). For best overall perfor- mance the recommended bias is Vdd =7V and Idd = 200 mA. To achieve this drain current level, Vg1 is typically between –2.5 to –3.5V. Typically, DC current flow for Vg1 is –10 mA. The AMMC-5024 has a second gate bias (Vg2) that may be used for gain control. When not being utilized, Vg2 should be left open-circuited. This feature further enhances the versatility of applica- tions where variable gain over a broad bandwidth is necessary. This second gate bias (Vg2) is connected to the gates of the upper FETs in each cascode stage through a small de-queing resistor. The other end of the gate line is termi- nated in an on-chip resistive/diode divider network, which allows the second gate to self-bias. Thus, with Vg2 left open-circuited, the drain current is set by the (Vg1) gate bias voltage applied to the lower FET in each stage. The nominal open circuit voltage for Vg2 is approximately 2 volts. Under this operating condition, maximum gain and power are achieved from the TWA. By applying an external voltage to the second gate bias (Vg2) less than the open-circuit potential, the drain volt- age on the lower FET can be decreased to a point where the lower FET enters the linear operating region. This reduces the current drawn by each stage. Decreasing Vg2 further will reduce the drain voltage on the lower FET to- wards zero while pinching off the upper FET in each stage. At larger negative values of Vg2 (between 0 and -2.5 volts) the gain of the TWA will decrease significantly. Using the simplest form of assembly (Figure 20), the device is capable of delivering flat gain over a 2 – 50 GHz range with a minimum of gain slope and ripple. However, this device is designed with DC coupled RF I/O ports, and operation may be extended to lower frequencies (<2 GHz) through the use of off-chip low-frequency extension circuitry and proper external biasing components. With low frequency bias extension it may be used in a variety of time-domain applications (through 40 Gb/s). Figure 21 shows a typical assembly configuration. When bypass capacitors are connected to the AUX pads, the low frequency limit is extended down to the corner frequency determined by the bypass capacitor and the combination of the on-chip 50 ohm load and small de- queing resistor. At this frequency the small signal gain will increase in magnitude and stay at this elevated level down to the point where the Caux bypass capacitor acts as an open circuit, effectively rolling off the gain completely. The low frequency limit can be approximated from the following equation: fCaux = 1 2πCaux(Ro + RDEQ) where: Ro is the 50Ω gate or drain line termination resistor. RDEQ is the small series de-queing resistor and 10Ω. Caux is the capacitance of the bypass capacitor con- nected to the AUX Drain pad in farads. With the external bypass capacitors connected to the AUX gate and AUX drain pads, gain will show a slight increase between 1.0 and 1.5 GHz. This is due to a series combina- tion of Caux and the on chip resistance but is exaggerated by the parasitic inductance (Lc) of the bypass capacitor and the inductance of the bond wire (Ld). Therefore the bond wire from the Aux pads to the bypass capacitors should be made as short as possible. Input and output RF ports are DC coupled; therefore, DC decoupling capacitors are required if there are DC paths. (Do not attempt to apply bias to these pads.) RF bond connections should be kept as short as possible to reduce RF lead inductance which will degrade perfor- mance above 20 GHz. An optional output power detector network is also pro- vided. A >0.5 µF capacitor is required for the Det_Out pad to expand power detection performance below 100 MHz. Ground connections are made with plated through-holes to the backside of the device; therefore, ground wires are not needed.
Figure 19. AMMC-5024 Schematic. cally conductive epoxy [1,2]. may jeopardize electrical or mechanical attachment. wire bond stage temperature is 150°c ± 2°c. mum Rating for assembly temperature and time. The chip is 100um thick and should be handled with care. (do not pick up the die with a vacuum on die center). Bonding pads and chip backside metallization are gold. may jeopardize reliability of the device.
- Ablebond 84-1 LMl silver epoxy is recommended
- Eutectic attach is not recommended and may jeopardize reliability
Figure 21. AMMC-5024 Assembly Diagram.
Ordering Information
AMMC-5024-W10 = 10 devices per tray AMMC-5024-W50 = 50 devices per tray For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2008 Avago Technologies. All rights reserved. Obsoletes 5989-3931EN AV02-0632EN - September 8, 2008 Figure 20. AMMC-5024 Bonding Pad Locations. (dimensions in micrometers)