AM1K-67132L-30R

M67132 TEMIC | Alldatasheet

Document overview

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Technical content

Features

© Fast Access Time @ BUSY Output Flag on Master 35 ns to 55 ns © BUSY Input Flag on Slave 30 ns Preliminary for Commercial only © Fully Asynchronous Operation from Bither Port © 671321/671421 Low Power © Battery Backup Operation : 2 V Data Retention 67132V/67142V Very Low Power © TTL Compatible © Expandable Data Bus to 16 Bits or More Using Master/Slave@ Single 5V + 10 % Power Supply Devices when Using More than One Device. 3.3V versions are also available. Please consult sales. © On Chip Arbitration Logic Versions with interrupt are also available. Plcase consult sales. MATRA MHS 1 Rev. D (11 April. 97)

M67132/M67142 Semiconductors Interface Pin Configuration

48 PIN DIL (top view), plastic, 52 PIN PLCC (top view) 48 PIN PLCC (top view)

INDEX. 22 lida 88 Be? osx ae ee eetbie mh a8 veo Te vassece \\ sissies ram, le an ate rae ou ir , 2 hag susy Cs 46D RW eat EO ven act Ain ara Ola 452) BUSYa meet ean MSc ES tn on Gs ‘af A108 mee aoha mee mee pede Ng mein Bee ee ie ag dy oD Aon Sadi sgn ae aie Aa G10 sD An see em a eanenazenens rr es = neannezasey on gasenanas ns» WG 16 sD Aa Bees Oo mei MSH Iw vou 17 2D Wor aay, oh Oh vu O18 31D Wen Made ee it Vx C19 90 Vos was Sein teu C}2 29) in 64 PIN VQEP sage ee ie woud ae 10m (top view) Ae oe walf2 = 7D Wan wee ee anoles 25) ¥00 Pees =o ie eat 28 fn SessFFeaessShsss Block Diagram RAM, Riv = Tj > C f-I shal oe LF IT = a CH ce, Aa. Ht 4 ee Yt An Ws, tA mu Wm 3 | coL, |_| COLUMN COLUMN coL | 3 On SEL irs) jo SEL hom Busy!” » ° Busy, Ato-> ROW, MEMORY ROW = Aion ha AgK Arce = ; Avon A : ARBITRATION : % Logic Aon RW RW,

2 MATRA MHS

Rev. D (11 April. 97)

Semiconductors M67132/M67142 Pin Names LEFT PORT RIGHT PORT NAMES Po vee Power Functional Description The M 67132/M67142 has two ports with separate control logic arbitrates between the left and right control, address and 1/0 pins that permit independent — addresses for access (refer to table 2). The inhibited port’s read/write access to any memory location. These devices BUSY flag is set and will reset when the port granted have an automatic power-down feature controlled by CS. access completes its operation in both arbitration modes. CS controls on-chip power-down circuitry which causes the port concerned to go into stand-by mode when not Data Bus Width Expansion selected (CS high). When a port is selected access to the eae ; full memory array is permitted. Each port has its own — Master/Slave Description Output Enable control (OE). In read mode, the port’s OE ~~ Expanding the data bus width to 16 or more bits in a turns the Output drivers on when set LOW, dual-port RAM system means that several chips may be Non-conflicting READ/WRITE conditions are active simultaneously. If every chip has a hardware illustrated in table 1. arbitrator, and the addresses for each chip arrive at the same time one chip may activate its L BUSY signal while epg . another activates its R BUSY signal. Both sides are now Arbitration Logic busy and the CPUs will wait indefinitely for their port to The arbitration logic will resolve an address match or a become free. chip select match down to a minimum of 5 ns and — To overcome this “Busy Lock-Out” problem, MHS has determine which port has access. In all cases, an active developed a MASTER/SLAVE system which uses a BUSY flag will be set for the inhibited port. single hardware arbitrator located on the MASTER. The The BUSY flags are required when both ports attempt to SLAVE has BUSY inputs which allow direct interface t0 access the same location simultaneously.Should this thc MASTER with no external components, giving a conflict arise, on-chip arbitration logic will determine Speed advantage over other systems. which port has access and set the BUSY flag for the When dual-port RAMs are expanded in width, the inhibited port. BUSY is set at speeds that allow the SLAVE RAMs must be prevented from writing until the processor to hold the operation with its associated address BUSY input has been setlled. Otherwise, the SLAVE chip and data. It should be noted that the operation is invalid may begin a write cycle during a conflict situation, On the for the port for which BUSY is set LOW. The inhibited opposite, the write pulse must extend a hold time beyond port will be given access when BUSY goes inactive. BUSY to ensure that a write cycle occurs once the conflict A conflict will occur when both left and right ports are #8 resolved. This timing is inherent in all dual-port active and the two addresses coincide. The on-chip ™©™Ory systems where more than one chip is active at the arbitration determines access in these circumstances, S4™me time. Two modes of arbitration arc provided : (1) if the The write pulse to the SLAVE must be inhibited by the addresses match and are valid before CS on-chip control MASTER’s maximum arbitration time. If a conflict then logic arbitrates between TS), and CSR for access ; or (2) occurs, the write to the SLAVE will be inhibited because if the CSs are low before an address match, on-chip _ of the MASTER’s BUSY signal. MATRA MHS 3 Rev. D (11 April. 97)

M67132/M67142 Semiconductors Truth Table Table 1: Non Contention Read/Write Control LEBT OR RIGHT PORT® FUNCTION a Notes: 1.Aox Ato. # Aor Ator: 2. IF BUSY = L, data is not written, 3. If BUSY = L, data may not be valid, see twp and tppp timing 4. H= HIGH, L = LOW, X = DON’T CARE, Z = HIGH IMPEDANCE. Table 2; Arbitration LEFT PORT RIGHT PORT FLAGS FUNCTION a A a ee ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH a a a TS ARBITRATION WITH ADDRESS MATCIT BEFORE CS. twse | Aue ioe [wer | Awa | || aston Rese sk wwer | rw vm | ob | | tivation Rested Notes: 5. X ~ DON’T CARE, L ~ LOW, H ~ HIGH. LYSR = Lett Address Valid 2 5 ns before right address. RSL = Right address Valid 2 5 ns before left address. Same ~ Left and Right Addresses match within 5 ns of each other. LLSR = Left CS = LOW 2 5 ns before Right CS RLSL = Right CS = LOW > 5 ns before lefi CS. LWSR = Left and Right CS = LOW within 5 ns of each other.

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Rev. D (11 April. 97)

Semiconductors M67132/M67142

Electrical Characteristics

Absolute Maximum Ratings * Notice Stresses greater than those listed under ABSOLUTE MAXIMUM Supply voltage (VCC-GND) : 0.3V107.0V RATINGS may cause permanent damage to the device.This is a stress Input or output voll lied: ... (GND 03 V)to(VCC 40.3 Vy Mlitig only and functional operation of the device at these or any other “ipa or ouput vetabe SPP “ rom 2 conditions above those indicated in the operational sections of this conditions for extented periods may affect reliability. OPERATING RANGE OPERATING SUPPLY VOLTAGE OPERATING TEMPERATURE DC Parameters ] 67132/142-30 | 67132/142-35 | 67132/142-45 | 67132/142-S5 | Versio i Description | iris IND IND IND | Unit |Value a a — com | Mit. | com} Mit. | Com | MIT. | AUTO! AUTO) AUTO) Tecsp (6) | Standby supply current Vv 5 5 5 5 5 5 5) | mA | Max (Both ports TTL level inputs) L 40 40 50, 40 50 40 50, mA | Max TccsBi 7) | Standby supply current v 100 100 | 200 | 100 | 200 | 100 | 200 | wa | Max (Both ports CMOS level inputs) L 1000 1000 | 2000 | 1000 | 2000 | 1000 | 2000 | WA | Max Tecor (8) | Operating supply current Vv 160 145 | 180 | 135 | 150 | 130 | 140 | mA | Max (Both ports active) L 175 155 200 150 170 M40 170 | mA | Max Tecori (yy | Operating supply current Vv 100 as | 100 | 75 | 85 | 70 | 75 | mA | Max (One port active ~ One port standby) L 105 9s_| 110 | 85 | 90 | so | 80 | ma | Max Notes: 6, CS), =CSp 22.2. 7. Cy, = CSp 2 VXX -0.2V. 8. Both ports active ~ Maximum frequency ~ Outputs open - OF = VIH. 9. One port active (f =MAX) — Output open — One port stand-by TTL or CMOS Level inputs — CS, = CSp 2 2.2 V. shee 67132-30/35/45/55 si PARAMETER DESCRIPTION sib Ea UNIT VALUE Notes: 10. Voc = 5 V, Vin = Gnd to Vor, CS = VIH, Vout = 0t0 Vec. IL. VIH max = Vec + 0.3 V, VIL min —0.3 V or 1 V pulse width 50 ns. 12. Voc min, IOL=4mA,10H= 4 mA. 13, To, = 16 mA. MATRA MHS 3 Rev. D (11 April. 97)

mind. Data retention voltage and supply current are during the power up and power down transitions. data retention: reaches the minimum operating voltage (4.5 volts). retention ; within Vec to VCCpr. Notes: 14. CS = Vee, Vin = Gnd to Vee. Figure 1. Output Load. Figure 2. Output load.

6 MATRA MHS

somiconaueters M67132/M67142 AC Parameters M67132-30(¢) | Mo7132-35¢%5 | Mo7132-45 | M67132-85 [| wancrcts | READ CLE ‘Mo7142-30(%) | M67L42-35¢") | MOTLA24S__M 67142-55 PARAMETER UNIT: ay) 20) [PRELIMINARY Sc a [mat [ver [abstaining » | «|| s[~] [rio nce [Ourssnticasasime [| |» | [| a [reo [inoiseeianerininet [eee | Loop |v | crinsisaicrorowerdownsineciy | — so | ~ | - | 0 | m | Notes: 16. ‘Transition is measured + 500 mV from low or high impedance voltage with load (figures 1 and 2). 17. ‘This parameter is guaranteed but not tested. 18. To access RAM CS = VIL. 19. STD symbol 20. ALT symbol. ). Commercial only, not available in DIP. (**), DIP package available for commercial only. Timing Waveform of Read Cycle n° 1, Either Side 7! 22,24) ‘ke ADDRESS Ey 10H to Timing Waveform of Read Cycle n° 2, Either Side ?!, 23,25) to w DATA cr tt te tro loo aa CURRENT 7 ise a oo % Notes: 21. R/Wis high for read cycles. 22. Device is continuously enabled, CN = Vip. 23. Addresses valid prior to or coincident with CS transition low. 24. OE= Vi 25. To access RAM, CS = Vi MATRA MHS 7 Rev. D (11 April. 97)

M67132/M67142 Semiconductors AC Parameters POOLE M67132-30(+) | M67132-35(**) | M67132-45 | M67132-55 caliente itis MOT142-30¢*) | M67142-35(4#) | M67142-45. | M 67142-55 PARAMETER a a . UNI (30) GBD PRELIMINARY TAVWL | tas Address Set up Time 0 0 0 0 ns “TWLWH twe Write Pulse Width 25 - 30, - 3s - 40 - ns [wit [oe | ota [ee Joe! rwioz | wwe, Write enable to output in high Z: - b _ i | 2 | — 30 (26,27) ‘Ourput active from end of write ; mes low | (26,27, 29) pe fe fe fo fe] Notes: 26, ‘Transition is measured + 500 mV from low or high impedance voltage with load (figures 1 and 2), 27. This parameter is guaranteed but not tested. 28, To access RAM CS = VIL. ‘This condition must be valid for entire tgw time. 29. ‘The specification for tp}; must be met by the device supplying write data to the RAM under all operating conditions. Although tpx and tow values vary over voltage and temperature, the actual tpg; will always be smaller than the actual tow. 30. STD symbol. 31. ALT symbol (*). Commercial only, not available in DIP. (©), DIP package available for commercial only,

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Semiconductors M67132/M67142 Timing Waveform of Write Cycle n° 1, R/W Controlled Timing 2:33. 34, 38) twe: “ ~~“ Ra a wz) ilideien GE Co) tow on DATAW Timing Waveform of Write Cycle n° 2, CS Controlled Timing 33,34, 36) two ADDRESS & ea tas tsw ‘wr RW tow: ‘bH DATAN Notes: 32. R/W must be high during all address transitions. 33. A write occurs during the overlap (tgw of wp) of a low CS and a low RAW. 34. twr is measured from the earlier of CS or R/W going high to the end of write cycle. 35. During this period, the I/O pins are in the ontpit state, and input signals mst not be applied. 36. Ifthe CS low transition occurs simultaneously with or after the RAV low transition, the outputs remain in the high impedance state 37, ‘Transition is measured + 500 mY from steady state with a 5 pF load (ineluding scope and jig). This parameter is sampled and not 100 % tested 38. I OB is low during a RAW controlled write cycle, the write pulse width must be the larger of twp oF (twz, | tw) toallow the /O drivers to turn off and data o be placed on the bus forthe required tpw. If OE is high during an RAW controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twr. 39, Toaccess RAM, CS ~ VIL. MATRA MHS 9 Rev. D (11 April. 97)

M67132/M67142 bemiconductors AC Parameters sYM- = ‘Mo7132 300%) | Mo7132-35(+*) | Mo7132.48 | M67132-55 BOL aati Mo7142-30(%) | M67L42-35(¢*) | MO7I42-45 | _M67142-55 BUSY TIMING (For M67132 only) PRELIMINARY teoc BUSY Disable time to Chip Select 25 23 25 twop | Write Pulse to data delay (40) - 55 - w - 10 Notes: 40. Port-to-port delay through RAM cells from writing port to reading por, refer to “Timing Waveform of Read with BUSY (For M67132 only)” 41, ‘To ensure that the earlier ofthe two ports wins. 42. tgpp is 4 calculated parameter and is the greater of 0, twp — wp (actual) oF tppp — tpw (actual). 43. ‘To ensure that the write eycle is inhibited during contention. 44. To ensure that a write cycle is completed after contention. 45. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read with Port to port delay (For M67132 only)”. (*). Commercial only, not available in DIP. (°*). DIP package for commercial only.

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Rev. D (11 April. 97)

Semiconductors M67132/M67142 Timing Waveform of Read with BUSY (46 47, 48) (For M67132) 00Fe nn Rn ——-— [Fo fe DATs ae a 10m Ae ee pe opm ery Notes: 46. ‘To ensure that the carlier of the two port wins. 48. Device is continuously enabled for both ports. 49. OE at L for the reading port. Timing Waveform of Write with Port-to-port ‘% 51; 52) (For M67142 only) a OH Phe 08 es Notes: 50. Assume BUSY = H for the writing port, and OF = L for the reading port. MATRA MHS. il Rev. D (11 April. 97)

M67132/M67142 Semiconductors Timing Waveform of Write with BUSY (For M67132) Wwe RW Wwe ety BUSY Timing Waveform of Contention Cycle n° 1, CS Arbitration (For M67132 only) L AND R taPS Sr 'Bac tepo BUSYR LAND R Sn taps SB {BAC tee BUSY.

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Rev. D (11 April. 97)

Semiconductors M67132/M67142 Timing Waveform of Contention Cycle n° 2, Address Valid Abritration (For M67132 only) 3) Left Address Valid First : tro OR two: “APS| teAA: 1BDA’ Right Address Valid First : trae OR two: tars || IBAA’ "BDA Erg Note: 53. TS, —TSk- Vin

16 Bit Master/Slave Dual-port Memory Systems

SLAVE®™? Busy Busy Note : 54, No arbitration in M67142 (SLAVE). BUSY IN inhibits write in M67142 (SLAVE). MATRA MHS 13 Rev. D (11 April. 97)

M67132/M67142 Semiconductors

Ordering Information

‘TEMPERATURE RANGE PACKAGE DEVICE SPEED FLOW Cc M so 67132V — _30 1K = 48 pin DIL ceramic 600 mils. 30 . CK = 48 pin DIL side-brazed 600 mils us blank = MIIS standards 4K = 48 pin LCC 35 ns 1883 = MIL STD 883 Class B or S 83 = 52 pin PLCC 45 ns P883 = MIL STD 883 + PIND test 3K = 48 pin DIL plastic 600 mils 55s SBISC_— = SCC 9000 level B/C RD — 64 pin VQrP SHXXX = Special customer request KK = Flat pack 48 pins 400 mils FHXXX = Flight models (space) Q3 = COPIS2 EHXXX = Engineering models (space) 0 =Dice form MHXXX = Mechanical paris (space) . . LHXXX = Life test parts (space) C= Commercial 0° to +70°C R = Tape and reel I= Industrial 40° to 485°C RD = Tape and reel dry pack A= Automotive 40° to +125°C = M=Milit 55° to +125°C » = Dry pack = Milita 9 4125°C $= Space 330 13sec 67132 = 16K (2K x 8) Master a ~ ~~ 67142 = 16K (2K x 8) Slave L = Low power Vv = Very low power

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Rev. D (11 April. 97)

Semiconductors M67132/M67142 Military and Space Versions The following tables give package/consumption/access time/process flow available combinations Temp. | Packages | Consumption | Access Time (ns) Std process RT process range 67132 67I32E Vv 3s | as | 55 Mil flows Mil flows Space flows (including (including SMD5962-87002) SCC9301033) M IK . . efele . ak . . eo lele . cK . . elele . KK x x x | x | x x @ . . eo lele . 0 x . x |x |e . 4K . ele . . cK . «je . . KK x x | x x x 0 x x |e . . Temp. | Packages | Consumption | Access Time (ns) Std process RT process range 67142 67142E v L as | 45 | 55 Mil flows Mil flows Space flows (including including SMD5962-87002) SCC9BO1033) Ik . . ele ie . aK . . eleie . cK . . eleie . KK x x x |x |x x @ . . ele ie . 0 x . x |x oe . ak . oe . . CK . oe . . KK x x Xx x x 0 x x oe . . © = product in production X= call sales office for availibility The information contained herein is subject to change without notice. No responsibility is assumed by TEMIC for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use. MATRA MHS 15 Rev. D (11 April. 97)