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Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 16
Technical content
Features
- Very Low Noise Figure: 0.82 dB typical
- High Gain: 13.5 dB typical
- High IIP3 and IP1dB
- Exceptional Cell/PCS-Band rejection
- Advanced GaAs E-pHEMT Technology
- Low external component count
- Wide Supply Voltage: 1 V to 3.6 V
- Shutdown current: < 0.1 μA
- CMOS compatible shutdown pin (SD) current @ 2.8 V: 0.1 mA
- Adjustable current via single external resistor/voltage
- Meets MSL3 and Lead-Free
- ESD-protected RF input: 3 kV HBM
- Small package dimension: 3.3(L)x2.1(W)x1.1(H) mm 3 Specifi cations (Typical Performance at 25°C) At 1.575 GHz, Vdd = 2.85 V, Idd = 8.0 mA
- Gain = 13.5 dB
- NF = 0.82 dB
- IIP3 = +7.0 dBm, IP1dB = +2.7 dBm
- Cell-Band Rejection: 54 dBc
- PCS-Band Rejection: 63 dBc At 1.575 GHz, 1.0 V supply
- S21 = 8.8 dB
- NF = 1.22 dB
- Idd = 1.9 mA Note: Package marking provides orientation and identifi cation “1412” = Product Code “YY” = Year of manufacture “WW” = Work Week of manufacture SURFACE MOUNT 3.3 x 2.1 x 1.1 mm3 12-Lead MCOB TOP VIEW BOTTOM VIEW RF_IN 1 Gnd 2 SD 3
9 Gnd
8 FILTER-OUT
7 Gnd
1 RF_IN
2 Gnd
12 VDD
11 Gnd
10 Gnd
Attention: Observe precautions for handling electrostatic sensitive devices. For RF_IN (Pin 1): ESD Human Body Model = 3 kV All other pins: ESD Machine Model = 40 V ESD Human Body Model = 300 V Refer to Avago Technologies Application Note A004R: Electrostatic Discharge, Damage and Control
Symbol Parameter Units Absolute Max.
- Operation of this device in excess of
- Assuming DC quiescent conditions.
- Thermal resistance measured using
Infra-Red measurement technique.
- Board (module belly) temperature T
Table 1. Performance Table at Nominal Operating Conditions Symbol Parameter and Test Condition Units Min. Typ Max. Table 2. Typical Performance at Vdd = +2.85V, Vsd = +1.8V, Idd = 4.5mA (typ) Symbol Parameter and Test Condition Units Typ.
- For noise fi gure measurement, input board loss has not been deducted.
- Measurements at 1.575 GHz obtained using demo board described in Figures 6 and 7.
- 1.575 GHz IIP3 test condition: F
Table 3. Typical Performance at Low Operating Voltages with R2 (See Figures 6 and 7) Set to 0 ohms
- For noise fi gure measurement, input board loss has not been deducted.
- Measurements at 1.575 GHz obtained using demo board described in Figures 6 and 7.
- 1.575 GHz IIP3 test condition: F
Figure 1. Demoboard and application circuit components table
Figure 2. Demoboard and application schematic diagram
- The demoboard of Figure 6 is Rogers® RO4350 with typical Dk=3.48 (@10GHz).
- L3 and the module’s internal input pre-match form the input matching network. The RFin pin, pin 1, is directly connected to a shunt inductor that is grounded. The RF output fi lter blocks DC.
- This circuit demonstrates that very low noise fi gure is obtainable with standard 0402 chip inductors instead of high-Q wirewound inductors.
- C2 and L2 form a matching network at the output of the LNA stage, which can be tuned to optimize gain and return loss. For exa mple, higher gain can be obtained by increasing the value of C2 but at the expense of stability. Changing the value of L2 can improve the P CS rejection, but impacts output return loss.
- L1 is a choke which isolates the demoboard from external disturbances during measurement. It is not needed in actual applicati on. Likewise, C1 and C3 mitigate the eff ect of external noise pickup on the Vdd and SD lines respectively. These components are not required in actual operation.
- R1 is a stability-enhancing resistor.
- C9 is a DC-blocking capacitor. It is also not required in actual operation.
- Bias control is achieved by either varying the SD voltage (Vsd) with/without R2, or fi xing the SD voltage to Vdd and adjusting R2 for the desired current. Typical value for R2 is 10k Ohms for 8 mA total current at Vdd = 2.85 V and Vsd = +2.60 V. For applications where it is more appropriate to have SD (Vsd) connected to Vdd, a 12 k Ohms resistor value for R2 is suggested (where Vdd = 2.85 V).
- For low-voltage operation such as Vdd = 1.5 V or 1.0 V, R2 may be omitted and SD (Vsd) connected directly to Vdd.
- The grounding regime for the ALM-1412 is critical to achieving the PCS- and Cell-Band Rejections shown in Figure 9. Please re fer to the PCB Land Patterns section of this document for the exact locations of the grounding vias.
Figure 18. Scattering and noise parameter reference planes
ALM-1412 Typical Scattering Parameters at 25°C, Vdd = 2.85 V, Vsd = +2.6V, Idd = 8mA (typ) The S- and Noise Parameters are measured using the PCB described in Figures 6 and 7. The PCB material is 10 mils Rogers® RO4350. Figure 23 shows the input and output reference planes. The circuit values, with the exception of L3, are as indicated in Figure 6. Freq. S11 S11 S21 S21 S21 S12 S12 S22 S22
ALM-1412 Typical Scattering Parameters at 25°C, Vdd = 2.85 V, Vsd = +1.8V, Idd = 4.5mA (typ) Freq. S11 S11 S21 S21 S21 S12 S12 S22 S22
ALM-1412 Typical Noise Parameters at 25°C, Freq = 1.575 GHz, Vdd = 2.85 V, Vsd = +2.6V, Idd = 8mA (typ) Freq Fmin GAMMA OPT (GHz) (dB) Mag Ang Rn/50 1.575 0.7 0.55 62 0.36 ALM-1412 Typical Noise Parameters at 25°C, Freq = 1.575 GHz, Vdd = 2.85 V, Vsd = +1.8V, Idd = 4.5mA (typ) Freq Fmin GAMMA OPT (GHz) (dB) Mag Ang Rn/50 1.575 0.85 0.54 71 0.36 Part Number Ordering Information Part Number No. of Devices Container ALM-1412-BLKG 100 Antistatic bag ALM-1412 -TR1G 3000 13” Reel Notes:
- The exceptional noise fi gure performance of the ALM-1412 is due to its highly optimized design. In this regard, the Fmin of the ALM-1412 shown above is locked down by the internal input pre-match. This allows the use of relatively inexpensive chip inductors for ex ternal matching.
- The NF performance of the ALM-1412 is also very resilient to operating conditions. For example, at Idd = 4.5 mA, the degradation in NF is only 0.1 dB, and not more than 0.15 dB degradation over temperature.
PCB Land Patterns and Stencil Design PCB land pattern and suggested grounding vias Stencil outline drawing Dimensions are in mm Combined PCB land pattern and stencil outline 2x–0.47 3.30 0.10 TOP VIEW 0.50 PIN 1 ORIENTATION NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONS ARE INCLUSIVE OF PLATING. 3. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR. 0.10 2x–0.69 2x–1.76 2x–0.28 7x–0.16 5x–0.35 SQ 0.10 ALL EDGES 0.07 GAPS 2x–0.20 2.10 0.10 1.550.60 2x–0.28 1412 WWYY 1.10 0.10 SIDE VIEW BOTTOM VIEW 5x – 0.350 SQ 0.670 ∅ 0.200 0.350 0.337 0.650 0.688 0.702 0.727 0.100 1.163 0.300 0.300 REF. 2.921 0.300 BA A A 0.00 REF. 0.775 0.775 0.709 0.740 (For B and C)0.267 0.00 REF. 0.157 0.688 1.473 1.991 2.521 EF G A A C D A B C D E F G 0.315 (SQUARE) 0.280 x 0.306 mm 0.257 x 0.306 mm 0.303 x 0.367 mm 0.544 x 0.492 mm 0.824 x 0.618 mm 0.257 x 0.617 mm BC D 1.201 1.991 2.750 0.712 0.2830.037 BA A A 0.00 REF. 3.100 0.00 REF. EF G A A C D BC D
Y Y P2 (1) P10 (3) D0 XX P1 (2) D1 F (1) W A SECTION X - X SECTION Y - Y REF. 0.50 NOTES: 1. MEASURE FROM CENTER LINE OF SPROCKET HOLE TO CENTER LINE OF POCKET. 2. MEASURE FROM CENTER LINE OF POCKET HOLE TO CENTER LINE OF POCKET. 3. PITCH TOLERANCE FOR SPROCKET HOLE: 10 PITCH CUMULATIVE TOLERANCE IS ± O.2 mm. 4. ALLOWABLE CAMBER TO BE 1 mm PER 250 mm IN LENGTH. REF. R 0.25 REF. R 0.25 REF. R 0.65 DETAIL A T 5 MAX. F DIMENSIONS NOTATION MILLIMETERS A0 3.60 ± 0.10 B0 2.40 ± 0.10 K0 1.35 ± 0.10 D0 1.55 ± 0.05 D1 1.60 ± 0.10 P0 4.00 ± 0.10 P1 8.00 ± 0.10 P2 2.00 ± 0.10 P10 40.00 ± 0.20 E 1.75 ± 0.10 F 5.50 ± 0.10 W 12.00 ± 0.30 T 0.30 ± 0.05 USER FEED DIRECTION TOP VIEW END VIEW 1412 WWYY 1412 WWYY 1412 WWYY USER FEED DIRECTION COVER TAPE CARRIER TAPE REEL
For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. AV02-0205EN - March 2, 2012 Reel Dimensions - 13 inch PS 21121110987 203546 6PS PS6 CPN 12MM MPN Detail "X" RECYCLE LOGO SEE DETAIL "X" R19.0±0.5 Ø12.3±0.5(3x) Ø100.0±0.5 Ø329.0±1.0 11.9-15.4** 18.4 MAX.* SLOT 5.0±0.5(3x) 12.4 +2.0* -0.0 16.0mm HEIGHT x MIN. 0.4mm THICK. EMBOSSED LETTERING EMBOSSED LINE (2x) 89.0mm LENGTH LINES 147.0mm AWAY FROM CENTER POINT 7.5mm HEIGHT EMBOSSED LETTERING DATE CODE ESD LOGO Ø16.0 7.5mm HEIGHT EMBOSSED LETTERING HUB Ø100.0±0.5 Ø329.0±1.0 20.2(MIN.) 1.5(MIN.) Ø13.0 -0.2 +0.5 BACK VIEW FRONT VIEW 8 7 6 5