AGM2416B

AGM2416B AZDISPLAYS | Alldatasheet

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PART NUMBER: AGM2416B DATE: AZ DISPLAYS, INC. September 13, 2005

AZ DISPLAYS, INC.

1 General Specifications

Mono. Grayscale FSTN Module Dimension 92.0 X 71.8 X 2.0 mm Viewing Area 67.0 X 46.8 mm Active Area 62.38 X 42.38 mm Character Size / mm Character Pitch / mm DOT Size 0.245 X 0.24 mm DOT Pitch 0.265 X 0.26 mm LCD Type TN, Positive TN, Negative HTN, Positive HTN, Negative STN, Yellow-Green STN , Gray STN, Blue FSTN, Positive FSTN, Negative Color STN FM LCD Polarizer Type Transflective Transmissive Reflective Anti-Glare View Direction 12H LCD Controller & Driver ST8016 & ST8024 LCD Driving Method 1/160duty, 1/14bias Interface Type I2C 4-wire Serial 3-wire Serial 6800 8080 4-bit Backlight Type / Backlight Color / EL/CCFL Driver type / DC-DC Converter Build-in External Operation Temperature (oC) - 1 0 ~ 6 0 ( T OPL – TOPH)° C Storage Temperature (oC ) - 2 0 ~ 7 0 ( T STL -- TSTH)° C

AZ DISPLAYS, INC.

3.1 Pin Description

Pin No. Symbol Function Description 1V 0 L 2V 1 2 L 3V 3 4 L 4V 5 L Bias power supply pins for LCD drive voltage Normally use the bias voltages set by a resistor divider Ensure that voltages are set such that V SS • V 5 < V43< V12< V0. ViL and ViR (i = 0,12, 43, 5) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin 5V S S 6V S S Ground 7V D D 8V D D Logic power supply 9 DBLKB Use as contrast control, use PWM signal as input. Connect to V DD for no contrast control. 10 D0 11 D1 12 D2 13 D3 Data bus

14 XCK

Clock input pin for taking display data * Data is read at the falling edge of the clock pulse.

15 DOFFB

Control input pin for output of non-select level The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to V SS level "L", the LCD drive output pins (Y1-Y240) are set to level Vss. When set to "L", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of DISPOFF. When the DISPOFF function is canceled, the driver outputs non-select level (V12or V43), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if DISPOFF removal time does not correspond to what is shown in AC characteristics, it can not output the reading data correctly. Table of truth values is shown in "TRUTH TABLE" in Functional Operations.

16 LP Latch pulse input pin for display data

Data is latched at the falling edge of the clock pulse. 17 FR AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. 18 MD Mode selection pin When set to V SS level "L", 8-bit parallel input mode is set. When set to V DD level "H", 4-bit parallel input mode is set. Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations.

19 V5R Bias power supply pins for LCD drive voltage

AZ DISPLAYS, INC.

20 V34R

21 V12R

22 V0R

Normally use the bias voltages set by a resistor divider Ensure that voltages are set such that V SS • V 5 < V43< V12< V0. ViL and ViR (i = 0,12, 43, 5) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin Common Pin Pin No. Symbol Function Description

23 V0L

24 V12L

Bias power supply pins for LCD drive voltage Normally use the bias voltages set by a resistor divider. Ensure that voltages are set such that V SS < V43< V12< V0. ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular voltage that is assigned by specification for each power pin.

26 VSS

27 VSS

28 VSS

29 VDD

30 VDD

31 VDD

32 EIO2

Shift data input for shift register at common mode

33 D7 Dual mode data input at common mode

Control input pin for output of non-select level The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to V SS level "L", the LCD drive output pins (Y1-Y160) are set to level Vss. When set to "L¡± , the contents of the shift register are reset to not reading data. When the /DISPOFF function is canceled, the driver outputs non-select level (V 12 or V43), and the shift data is read at the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, the shift data is not read correctly. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.

35 LP Shift clock pulse input pin for bi-directional shift register

• Data is shifted at the falling edge of the clock pulse. FR AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the shift register output signal and the FR signal. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.

37 V34R

38 V12R

Bias power supply pins for LCD drive voltage Normally use the bias voltages set by a resistor divider. Ensure that voltages are set such that V SS < V43< V12< V0. ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular voltage that is assigned by specification for each power pin.

AZ DISPLAYS, INC.

3.2 Block Diagram

AZ DISPLAYS, INC. 4. Electrical-optical Specifications

4.1 Absolute Maximum Ratings

4.2 Electrical-Optical Characteristics

No Item Symbol Condition Min. Typ. Max. Unit 1 Current (all SEG on) I Ta=25 oC - 15.0 30.0 •  A

2 Contrast Ratio Cr Ta=25oC

VLCD = 19.5V 4.5 5.0 - - 3 Threshold voltage Vth Ta=25oC 1.85 1.90 - V 4 Saturation voltage Vsat Ta=25 oC - 2.05 2.10 V Rise time Tr Ta=25 oC- 2 5 0 3 5 0 m s Fall time Tf Ta=25 oC- 2 0 0 3 0 0 m s5 On time T ON Ta=25oC- 3 0 0 4 5 0 m s Response time Off time T OFF Ta=25oC- 2 5 0 3 5 0 m s 76 H   1 4 5 --D e g . 81 2 H   2 2 5 --D e g . 93 H   3 4 5 --D e g . Viewing Angle 9H   4 Cr = 2 Ta=25oC 4 5 --D e g .

11 Frame frequency f M Ta=25oC3 2 6 4 1 2 8 H z

4.3 Electrical Characteristics

No Item Symbol Condition Min. Typ. Max. Unit 1 Supply Voltage for Logic V DD-VSS - 2.5 - 5.5 V

2 Supply Voltage for LCD Driver VDD-VO

(VLCD) Ta=25 oC 19.3 19.5 19.7 V

3 Supply Current for Logic I DD

Ta=25 oC VDD=5.0V -2 3 2 6 m A

4 Frame Frequency f M Ta=25oC- 8 0 - H z

AZ DISPLAYS, INC. 5 Input High Voltage V IH -0 . 8 X V DD -V DD V 6 Input Low Voltage V IL -G N D - 0 . 2 X V DD V 7 Output High Voltage V OH - VDD-0.4 -- V 8 Output Low Voltage V OL -- - + 0 . 4 V

4.3 Timming Characteristics

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AZ DISPLAYS, INC. 5 Input High Voltage V IH -0 . 8 X V DD -V DD V 6 Input Low Voltage V IL -G N D - 0 . 2 X V DD V 7 Output High Voltage V OH - VDD-0.4 -- V 8 Output Low Voltage V OL -- - + 0 . 4 V

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AZ DISPLAYS, INC.

AZ DISPLAYS, INC.

AZ DISPLAYS, INC.

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