AFBR-57F5PZ AVAGO | Alldatasheet
Document overview
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Technical content
Features
- Compliant to RoHS directives
- 850nm Vertical Cavity Surface Emitting Laser (VCSEL)
- Class 1 eye safe per IEC60825-1 and CDRH
- Wide temperature range (0°C to 70°C)
- LC duplex connector optical interface conforming to ANSI TIA/EIA604-10 (FOCIS 10A)
- Diagnostic features per SFF-8472 “Diagnostic Monitor- ing Interface for Optical Transceivers”
- Enhanced operational features including EWRAP , OWRAP and variable electrical EQ/emphasis settings
- Real time monitoring of: - Transmitter average optical power - Received average optical power - Laser bias current - Temperature - Supply Voltage
- SFP+ mechanical specifications per SFF-8432
- SFP+ compliant low speed interface
- Fibre Channel FC-PI-5 compliant high speed interface - 1600-SN-M6-S, 800-SN-M6-S, 400-SN-M6-I - 1600-SN-M5-S, 800-SN-M5-S, 400-SN-M5-I - 1600-SN-M5E-I, 800-SN-M5E-I, 400-SN-M5E-I - 1600-SN-M5F-I, 800-SN-M5F-I, 400-SN-M5F-I
- Fibre Channel FC-PI-5 compliant optical link distances
Applications
- Fibre Channel switches (director, stand alone, blade)
- Fibre Channel Host Bus Adapters
- Fibre Channel RAID controllers
- Fibre Channel tape drive
- Port side connections
- Inter-switch or inter-chassis aggregated links
Description
Avago Technologies’ AFBR-57F5PZ optical transceiver sup- ports high speed serial links over multi-mode optical fiber at signalling rates up to 14.025Gb/s (the serial line rate of 16GFC). The product is compliant with Small Form Plug - gable industry agreements SFP and SFP+ for mechanical and low speed electrical specifications. High speed elec - trical and optical specifications are compliant with ANSI Fibre Channel FC-PI-5. The AFBR-57F5PZ is a multi-rate 850nm transceiver which ensures compliance with FC-PI-5 16GFC, 8GFC and 4GFC specifications. Per the requirements of 16GFC, internal clock and data recovery circuits (CDRs) are present on both electrical input and electrical output of this trans - ceiver. These CDRs will lock at 14.025Gb/s (16GFC) but must be bypassed for operation at 8.5Gb/s (8GFC) and 4.25Gb/s (4GFC), accomplished by using two Rate Select inputs to configure transmit and receive sides. Transmitter and receiver can operate at different data rates, as is often seen during Fibre Channel speed negotiation. Digital diagnostic monitoring information (DMI) is pres - ent in the AFBR-57F5PZ per the requirements of SFF-8472, providing real time monitoring information of transceiver laser, receiver and environment conditions over a SFF- 8431 2-wire serial interface. AFBR-57F5PZ 16GFC SFP+ Digital Diagnostic SFP , 850nm, 16G/8G/4G Low Voltage (3.3V) Fibre Channel Optical Transceiver Data Sheet
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The AFBR-57F5PZ can be installed in any SFF-8074i com - pliant Small Form Pluggable (SFP) port regardless of host equipment operating status. The AFBR-57F5PZ is hot- pluggable, allowing the module to be installed while the host system is operating and on-line. Upon insertion, the transceiver housing makes initial contact with the host board SFP cage, mitigating potential damage due to Elec- tro-Static Discharge (ESD). Digital Diagnostic Interface and Serial Identification The 2-wire serial interface is based on ATMEL AT24C01A series EEPROM protocol and signaling detail. Conven - tional EEPROM memory, bytes 0-255 at memory address 0xA0, is organized in compliance with SFF-8074i. New digital diag nostic information, bytes 0-255 at memory ad- dress 0xA2, is compliant to SFF-8472. The new diagnostic information provides the opportunity for Predictive Fail - ure Identification, Com pliance Prediction, Fault Isolation and Component Monitoring. Predictive Failure Identification The AFBR-57F5PZ predictive failure feature allows a host to identify potential link problems before system perfor - mance is impacted. Prior identification of link problems enables a host to service an application via “fail over” to a redundant link or replace a suspect device, maintaining system uptime in the process. For applications where ul - tra-high system uptime is required, a digital SFP provides a means to monitor two real-time laser metrics asso ciated with observing laser degradation and predicting failure: average laser bias current (Tx_Bias) and average laser op - tical power (Tx_Power). Compliance Prediction Compliance prediction is the ability to determine if an optical transceiver is operating within its operating and environmental requirements. AFBR-57F5PZ devices pro - vide real-time access to transceiver internal supply volt - age and temperature, allowing a host to identify potential component compliance issues. Received optical power is also available to assess compliance of a cable plant and remote transmitter. When operating out of requirements, the link cannot guarantee error free transmission. Fault Isolation The fault isolation feature allows a host to quickly pin - point the location of a link failure, minimizing downtime. For optical links, the ability to identify a fault at a local de- vice, remote device or cable plant is crucial to speeding service of an installation. AFBR-57F5PZ real-time monitors of Tx_Bias, Tx_Power, Vcc, Temperature and Rx_Power can be used to assess local transceiver current operating con- ditions. In addition, status flags Tx_Disable and Rx Loss of Signal (LOS) are mirrored in memory and available via the two-wire serial interface. Component Monitoring Component evaluation is a more casual use of the AFBR- 57F5PZ real-time monitors of Tx_Bias, Tx_Power, Vcc, Tem- perature and Rx_Power. Potential uses are as debugging aids for system installation and design, and transceiver parametric evaluation for factory or field qualification. For example, temperature per module can be observed in high density applications to facilitate thermal evaluation of blades, PCI cards and systems.
Figure 1. Transceiver functional diagram. two-wire serial interface (address A2, byte 110, bit 2). unsafe condition beyond the scope of Class 1 certification.
The receiver section includes a Receiver Optical SubAs - sembly (ROSA), pre-amplification and post-amplification circuit, Clock and Data Recovery Circuit and an electrical output stage with variable emphasis controls. The ROSA, containing a high speed PIN detector, pre-amplifier and imaging optics efficiently couple light from the LC con - nector interface and perform an optical to electrical con - version. The resulting differential electrical signal passes through a post amplification circuit and into a Clock and Data Recovery circuit (CDR) for cleaning up accumulated jitter. The resulting signal is passed to a high speed output line driver stage with variable, i2c controlled, emphasis settings allowing the host to optimize signal characteris - tics between the SFP and host ASIC. Note the Rx CDR is engaged only with Rx_RATE=high (16GFC) and bypassed with Rx_RATE=low (8G/4G). Receiver Loss of Signal (Rx_LOS) The post-amplification IC also includes transition detec - tion circuitry which monitors the ac level of incoming op- tical signals and provides a TTL/CMOS compatible status signal to the host (pin 8). An adequate optical input results in a low Rx_LOS output while a high Rx_LOS output in - dicates an unusable optical input. The Rx_LOS thresholds are factory set so that a high output indicates a definite optical fault has occurred. Rx_LOS can also be monitored via the two-wire serial interface (address A2h, byte 110, bit 1). Functional Data I/O The AFBR-57F5PZ interfaces with the host circuit board through twenty I/O pins (SFP electrical connector) identi - fied by function in Table 2. The board layout for this inter- face is depicted in Figure 6. The AFBR-57F5PZ high speed transmit and receive inter - faces require SFP MSA compliant signal lines on the host board. To simplify board requirements, biasing resistors and ac coupling capacitors are incorporated into the SFP transceiver module (per SFF-8074i) and hence are not re - quired on the host board. The Tx_Disable, Tx_Fault, and Rx_LOS lines require TTL lines on the host board (per SFF- 8074i) if used. If an application chooses not to take advan- tage of the functionality of these pins, care must be taken to ground Tx_Disable (for normal operation). Figure 2 depicts the recom mended interface circuit to link the AFBR-57F5PZ to supporting physical layer ICs. Timing for MSA compliant control signals implemented in the transceiver are listed in Figure 4. Application Support An Evaluation Kit and Reference Designs are available to assist in evaluation of the AFBR-57F5PZ. Please contact your local Field Sales representative for availability and ordering details. Caution There are no user serviceable parts nor maintenance re - quirements for the AFBR-57F5PZ. All mechanical adjust - ments are made at the factory prior to shipment. Tam - pering with, modifying, misusing or improperly handling the AFBR-57F5PZ will void the product warranty. It may also result in improper operation and possibly overstress the laser source. Performance degrada tion or device fail - ure may result. Connection of the AFBR-57F5PZ to a light source not compliant with ANSI FC-PI specifications, oper- ating above maximum operating conditions or in a man - ner inconsistent with it’s design and function may result in exposure to hazardous light radiation and may constitute an act of modifying or manufacturing a laser product. Per- sons performing such an act are required by law to re-cer- tify and re-identify the laser product under the provisions of U.S. 21 CFR (Subchapter J) and TUV.
Ordering Information
Please contact your local field sales engineer or one of Avago Technologies franchised distributors for ordering information. For technical information, please visit Avago Technologies’ WEB page at www.avagotech.com or contact Avago Technologies Semiconductor Products Customer Response Center at 1-800-235-0312. For information re - lated to SFF Committee documentation visit www.sffcom- mittee.org. Regulatory Compliance The AFBR-57F5PZ complies with all applicable laws and regulations as detailed in Table 1. Certification level is de- pendent on the overall configuration of the host equip - ment. The transceiver performance is offered as a figure of merit to assist the designer.
57F5PZ exceeds typical industry standards. 94V-0 flame retardant plastic. benches and floor wherever a transceiver is handled. exterior of the host equipment chassis after installation. Table 1. Regulatory Compliance contacted by a Human Body Model probe. with device inserted into a panel. to the Optical Connector connector without damage. (EMI) CENELEC EN55022 Class B board and chassis design. 10 V/m field swept from 10 MHz to 1 GHz. and polybrominated biphenyl ethers.
- TX_FAULT is an open collector/drain output, which must be pulled up with a 4.7 k – 10 kΩ resistor on the host board. When high, this output indi-
cates a laser fault of some kind. Low indicates normal operation. In the low state, the output will be pulled to < 0.8 V.
- TX_DISABLE is an input that is used to shut down the transmitter optical output. It is internally pulled up (within the transceiver) with a 6.8 kΩ
- The signals Mod-Def 0, 1, 2 designate the two wire serial interface pins. They must be pulled up with a 4.7 k – 10 kΩ resistor on the host board.
- RX_LOS (Rx Loss of Signal) is an open collector/drain output that must be pulled up with a 4.7 k – 10 kΩ resistor on the host board. When high, this
operation. In the low state, the output will be pulled to < 0.8 V.
- RD-/+ designate the differential receiver outputs. They are AC coupled 100 Ω differential lines which should be terminated with 100 Ω differential
be between 370 and 850 mV differential (185 – 425 mV single ended) when properly terminated.
- VccR and VccT are the receiver and transmitter power supplies. They are defined at the SFP connector pin. The maximum supply current is 300 mA
and the associated in-rush current will typically be no more than 30 mA above steady state after 2 microseconds.
- TD-/+ designate the differential transmitter inputs. They are AC coupled differential lines with 100 Ω differential termination inside the module.
- Rate_Select is an input that is used to control transmit and receive high speed parametric optimizaton. It is internally pulled down (within the
transceiver) with a 40kOhm resistor. Low (0 - 0.8V) or Open: Rate is set to 8.5Gb/s and below optimization. The CDR is bypassed. High (2.0 - Vcc max): Rate is set to 14.025Gb/s optimization. The CDR is engaged. Table 3. Pin Description
1 VeeT Transmitter Ground
2 TX_FAULT Transmitter Fault Indication – High indicates a fault condition Note 1
3 TX_DISABLE Transmitter Disable – Module electrical input disables on high or open Note 2
4 MOD-DEF2 Module Definition 2 – Two wire serial ID interface data line (SDA) Note 3
5 MOD-DEF1 Module Definition 1 – Two wire serial ID interface clock line (SCL) Note 3
6 MOD-DEF0 Module Definition 0 – Grounded in module (module present indicator) Note 3
8 RX_LOS Loss of Signal – High indicates loss of received optical signal Note 4
10 VeeR Receiver Ground
11 VeeR Receiver Ground
12 RD- Inverse Received Data Out Note 5
13 RD+ Received Data Out Note 5
14 VeeR Receiver Ground
17 VeeT Transmitter Ground
18 TD+ Transmitter Data In Note 7
19 TD- Inverse Transmitter Data In Note 7
20 VeeT Transmitter Ground
Table 4. Absolute Maximum Ratings
- Absolute Maximum Ratings are those values beyond which damage to the device may occur if these limits are exceeded for other than a short
period of time. See Reliability Data Sheet for specific reliability performance.
- Between Absolute Maximum Ratings and the Recommended Operating Conditions functional performance is not intended, device reliability is
not implied, and damage to the device may occur over an extended period of time.
- The module supply voltages, VCCT and VCCR must not differ by more than 0.5 V or damage to the device may occur.
Table 5. Recommended Operating Conditions
- The Ambient Operating Temperature limitations are based on the Case Operating Temperature limitations and are subject to the host system
- Recommended Operating Conditions are those values for which functional performance and device reliability is implied.
Table 6. Transceiver Electrical Characteristics
- Filter per SFP specification is required on host board to remove 10 Hz to 2 MHz content.
- Pulled up externally with a 4.7 k – 10 kΩ resistor on the host board to 3.3 V.
- Mod-Def1 and Mod-Def2 must be pulled up externally with a 4.7 k – 10 kΩ resistor on the host board to 3.3 V.
Table 7. Transmitter and Receiver Electrical Characteristics
- Internally ac coupled and terminated (100Ω differential).
- Internally ac coupled but requires an external load termination (100Ω differential).
- CDR is engaged with Rx_Rate = high. Received output jitter for 14.025 Gb/s.
Table 8. Transmitter Optical Characteristics
- Max Pout is the lesser of Class 1 safety limits (CDRH and EN 60825) or received power, max.
- CDR is engaged with Tx_Rate = high. Transmitter output jitter for 14.025 Gb/s.
Table 9. Receiver Optical and Electrical Characteristics
- Input Optical Modulation Amplitude (commonly known as sensitivity] requires a valid Fibre Channel encoded input.
- 14.025 Gb/s stressed received vertical eye closure penalty (ISI) min is 2.5dB for all fiber types.
- 8.5 Gb/s stressed received vertical eye closure penalty (ISI) min is 3.1dB for all fiber types.
Table 10. Transceiver SOFT DIAGNOSTIC Timing Characteristics
- Time from rising edge of TX_DISABLE to when the optical output falls below 10% of nominal.
- Time from falling edge of TX_DISABLE to when the modulated optical output rises above 90% of nominal.
- Time from power on or falling edge of Tx_Disable to when the modulated optical output rises above 90% of nominal.
- From power on or negation of TX_FAULT using TX_DISABLE.
- Time TX_DISABLE must be held high to reset the laser fault shutdown circuitry.
- Time from loss of optical signal to Rx_LOS Assertion.
- Time from valid optical signal to Rx_LOS De-Assertion.
- Time from two-wire interface assertion of TX_DISABLE (A2h, byte 110, bit 6) to when the optical output falls below 10% of nominal. Measured
from falling clock edge after stop bit of write transaction.
- Time from two-wire interface de-assertion of TX_DISABLE (A2h, byte 110, bit 6) to when the modulated optical output rises above 90% of nomi-
- Time from fault to two-wire interface TX_FAULT (A2h, byte 110, bit 2) asserted.
- Time for two-wire interface assertion of Rx_LOS (A2h, byte 110, bit 1) from loss of optical signal.
- Time for two-wire interface de-assertion of Rx_LOS (A2h, byte 110, bit 1) from presence of valid optical signal.
- From power on to data ready bit asserted (A2h, byte 110, bit 0). Data ready indicates analog monitoring circuitry is functional.
- Time from power on until module is ready for data transmission over the serial bus (reads or writes over A0h and A2h).
- Time from stop bit to completion of a 1-8 byte write command.
- Time between STOP and START commands.
- Time from rising or falling edge of Rate_Select input until transceiver is successfully passing traffic as designated by RS(0) and RS(1). For Rate_
the internal CDR will be bypassed within the specified time for transmission of valid 8b/10b encoded 8.5Gb/s or 4.25Gb/s data.
- Time from two-wire interface Assertion of Rate_Select (either RS(0) in A2h, byte 110, bit 3 or RS(1) in A2h, byte 118, bit 3) to when the respective
CDR is engaged at 14.025Gb/s data rate.
- Time from two-wire interface Deassertion of Rate_Select (either RS(0) in A2h, byte 110, bit 3 or RS(1) in A2h, byte 118, bit 3) to when the respec-
tive CDR is bypassed for low speed 8.5Gb/s or 4.25Gb/s operation.
Table 11. Transceiver Digital Diagnostic Monitor (Real Time Sense) Characteristics Transceiver Internal Temperature TINT ±3.0 °C Temperature is measured internal to the transceiver. Accuracy Valid from = 0°C to 70°C case temperature. voltage at the SFP Vcc pin. Valid over 3.3 V ± 10%. Transmitter Laser DC Bias Current IINT ±10 % IINT is better than ±10% of the nominal value. Output Power Accuracy 100 µW to 500 µW, avg. Power Accuracy 31 µW to 500 µW, avg. Figure 5. Transceiver timing diagrams (module installed except where noted).
Table 12. EEPROM Serial ID Memory Contents – Address A0h
- The IEEE Organizationally Unique Identified (OUI) assigned to Avago Technologies is 00-17-64 (3 bytes of hex).
- Laser Wavelength is represented in 16 unsigned buts. The hex representation of 850nm is 0352.
- Addresses 63 and 95 are checksums calculated (per SFF-8472 and SFF-8074) and stored prior to product shipment.
- Address 68-83 specify the AFBR-57F5PZ ASCII serial number and will vary on a per unit basis.
- Address 84-91 specify the AFBR-57F5PZ ASCII data code and will vary on a per date code basis.
Table 13. EEPROM Serial ID Memory Contents – Enhanced Feature Set Memory (Address A2h)
0 Temp H Alarm MSB[1] 26 Tx Pwr L Alarm MSB[4] 104 Real Time Rx Pwr MSB[5]
1 Temp H Alarm LSB[1] 27 Tx Pwr L Alarm LSB[4] 105 Real Time Rx Pwr LSB[5]
2 Temp L Alarm MSB[1] 28 Tx Pwr H Warning MSB[4] 106 Reserved
3 Temp L Alarm LSB[1] 29 Tx Pwr H Warning LSB[4] 107 Reserved
4 Temp H Warning MSB[1] 30 Tx Pwr L Warning MSB[4] 108 Reserved
5 Temp H Warning LSB[1] 31 Tx Pwr L Warning LSB[4] 109 Reserved
6 Temp L Warning MSB[1] 32 Rx Pwr H Alarm MSB[5] 110 Status/Control - See Table 14
7 Temp L Warning LSB[1] 33 Rx Pwr H Alarm LSB[5] 111 Status/Control - See Table 15
8 Vcc H Alarm MSB[2] 34 Rx Pwr L Alarm MSB[5] 112 Flag Bits - See Table 16
9 Vcc H Alarm LSB[2] 35 Rx Pwr L Alarm LSB[5] 113 Flag Bits - See Table 16
10 Vcc L Alarm MSB[2] 36 Rx Pwr H Warning MSB[5] 114 Reserved
11 Vcc L Alarm LSB[2] 37 Rx Pwr H Warning LSB[5] 115 Reserved
12 Vcc H Warning MSB[2] 38 Rx Pwr L Warning MSB[5] 116 Flag Bits - See Table 16
13 Vcc H Warning LSB[2] 39 Rx Pwr L Warning LSB[5] 117 Flag Bits - See Table 16
14 Vcc L Warning MSB[2] 40-55 Control Settings - See Table 18 118 Status/Control - See Table 17
15 Vcc L Warning LSB[2] 56-94 External Calibration Constants[6] 119-127 Reserved
16 Tx Bias H Alarm MSB[3] 95 Checksum for Bytes 0-94[7] 128-247 Customer Writeable
17 Tx Bias H Alarm LSB[3] 96 Real Time Temperature MSB[1] 248-255 Vendor Specific
18 Tx Bias L Alarm MSB[3] 97 Real Time Temperature LSB[1]
19 Tx Bias L Alarm LSB[3] 98 Real Time Vcc MSB[2]
20 Tx Bias H Warning MSB[3] 99 Real Time Vcc LS[2]
21 Tx Bias H Warning LSB[3] 100 Real Time Tx Bias MSB[3]
22 Tx Bias L Warning MSB[3] 101 Real Time Tx Bias LSB[3]
23 Tx Bias L Warning LSB[3] 102 Real Time Tx Power MSB[4]
24 Tx Pwr H Alarm MSB[4] 103 Real Time Tx Power LSB[4]
25 Tx Pwr H Alarm LSB[4]
- Temperature (Temp) is decoded as a 16 bit signed twos compliment integer in increments of 1/256°C.
- Supply Voltage (Vcc) is decoded as a 16 bit unsigned integer in increments of 100 µV.
- Laser bias current (Tx Bias) is decoded as a 16 bit unsigned integer in increments of 2 µA.
- Transmitted average optical power (Tx Pwr) is decoded as a 16 bit unsigned integer in increments of 0.1 µW.
- Received average optical power (Rx Pwr) is decoded as a 16 bit unsigned integer in increments of 0.1 µW.
- Bytes 56-94 are not intended for use with AFBR-57F5PZ, but have been set to default values per SFF-8472.
- Byte 95 is a checksum calculated (per SFF-8472) and stored prior to product shipment.
Table 14. EEPROM Serial ID Memory Contents – Soft Commands (Address A2h, Byte 110)
7 TX_DISABLE State Digital state of TX_DISABLE Input Pin (1 = TX_DISABLE asserted) Note 1
6 Soft TX_DISABLE Control Read/write bit for changing digital state of TX_DISABLE function Note 1, 2
5 RS(1) State Digital state of TX Rate_Select Input Pin RS(1) (1 = Rate High asserted)
4 RS(0) State Digital state of RX Rate_Select Input Pin RS(0) (1 = Rate High asserted)
3 Soft RS(0) Control Read/write bit for changing digital state of Rx Rate_Select RS(0) function Note 3
2 TX_FAULT State Digital state of TX_FAULT Output Pin (1 = TX_FAULT asserted) Note 1
1 RX_LOS State Digital state of SFP RX_LOS Output Pin (1 = RX_LOS asserted) Note 1
0 Data Ready (Bar) Indicates transceiver is powered and real time sense data is ready
- The response time for soft commands of the AFBR-57F5PZ is 100msec as specified by MSA SFF-8472.
- Bit 6 is logic OR’d with the SFP TX_DISABLE input pin 3 …. either asserted will disable the SFP transmitter.
- Bit 3 is logic OR’d with the SFP RS(0) RX Rate_Select input pin 7 …. either asserted will set receiver to Rate = High.
Table 15. EEPROM Serial ID Memory Contents – Soft Commands (Address A2h, Byte 111).
3 OWRAP FORWARD
Rx optical data to both the Tx optical output and the Rx electrical output. Enabling sets bit 2 and clears all other bits in byte 111.
2 OWRAP
output. Enabling clears all other bits in byte 111.
1 EWRAP FORWARD
SFP Tx electrical data to both Rx electrical output and Tx optical output. Enabling sets bit 0 and clears all other bits in byte 111.
0 EWRAP
output. Enabling clears all other bits in byte 111.
Table 16. EEPROM Serial ID Memory Contents – Alarms and Warnings (Address A2h, Bytes 112, 113, 116, 117)
6 Temp Low Alarm Set when transceiver internal temperature exceeds low alarm threshold
5 Vcc High Alarm Set when transceiver internal supply voltage exceeds high alarm threshold
4 Vcc Low Alarm Set when transceiver internal supply voltage exceeds low alarm threshold
3 Tx Bias High Alarm Set when transceiver laser bias current exceeds high alarm threshold
2 Tx Bias Low Alarm Set when transceiver laser bias current exceeds low alarm threshold
1 Tx Power High Alarm Set when transmitted average optical power exceeds high alarm threshold
0 Tx Power Low Alarm Set when transmitted average optical power exceeds low alarm threshold
6 Rx Power Low Alarm Set when received average optical power exceeds low alarm threshold
6 Temp Low Warning Set when transceiver internal temperature exceeds low warning threshold
5 Vcc High Warning Set when transceiver internal supply voltage exceeds high warning threshold
4 Vcc Low Warning Set when transceiver internal supply voltage exceeds low warning threshold
3 Tx Bias High Warning Set when transceiver laser bias current exceeds high warning threshold
2 Tx Bias Low Warning Set when transceiver laser bias current exceeds low warning threshold
1 Tx Power High Warning Set when transmitted average optical power exceeds high warning threshold
0 Tx Power Low Warning Set when transmitted average optical power exceeds low warning threshold
6 Rx Power Low Warning Set when received average optical power exceeds low warning threshold
Table 17. EEPROM Serial ID Memory Contents – Soft Commands (Address A2h, Byte 118).
3 Soft RS(1) Control Read/write bit for changing digital state of Tx Rate_Select RS(1) function Note 1
2 Reserved
0 Power Level Select Unused. This device supports power level zero (1 Watt max) only.
- Bit 3 is logic OR’d with the SFP RS(1) TX Rate_Select input pin 9 …. either asserted will set transmitter to Rate = High.
40 Tx Input EQ Setting for
EQ is set to 0dB (no EQ). With LSB = 1, the Tx input EQ is set to 6dB gain at 7 GHz. Writing FFh to this byte resets to factory settings, EQ = 0dB.
41 Tx Input EQ Setting for
EQ is set to 0dB (no EQ). With LSB = 1, the Tx input EQ is set to 6dB gain at 7 GHz. Writing FFh to this byte resets to factory settings, EQ = 0dB.
42 Rx Output Pre Emphasis
Writing FFh to this byte resets to factory settings, EMPH = 0dB.
43 Rx Output Pre Emphasis
Writing FFh to this byte resets to factory settings, EMPH = 0dB. 44-55 Unallocated Contents 00h. Note: Checksum at address A2h byte 95 will be updated within 100ms of a value change in these bytes.
Figure 6. Module drawing.
0.65 UNCOMPRESSED
0.94 UNCOMPRESSED
Figure 7. SFP host board mechanical layout.
0.06 L A S B S
- PADS AND VIAS ARE CHASSIS GROUND
- THROUGH HOLES, PLATING OPTIONAL
- HATCHED AREA DENOTES COMPONENT
This module is pluggable and is not designed for aqueous wash, IR reflow, or wave soldering processes. Figure 8. SFP Assembly drawing.
10 REF
11.73 REF
For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. AV02-2508EN - January 28, 2013 RS0 RX Rate Select control flow RS0 Control Input RX OperationHardware Software 0 0 4/8G FC RX CDR bypassed 0 1 16G FC RX CDR enabled 1 0 16G FC 1 1 16G FC RS1 TX Rate Select control flow RS1 Control Input TX OperationHardware Software 0 0 4/8G FC TX CDR bypassed 0 1 16G FC TX CDR enabled 1 0 16G FC 1 1 16G FC Appendix I. Rate Select Control RX and TX rates can be independently controlled by either hardware input pins or via register writes. Module electrical input pins 7 and 9 are used to select RX and TX rate respectively. Status of each logic level is reflected to register byte 110 bit 4 and 5 on address A2h as shown in the diagram below. RX and TX rates can also be controlled by register writes to byte 110 bit 3 and 118 bit 3. Power on default of these bits are logic low. Hardware and software control inputs are OR’d to allow flexible control. RS0 (PIN7) Voltage "1"...V>2.0 "0"...V<0.8 A2h, byte 110 Bit 3 OR A2h, byte 110 Bit 4 RX Rate Control Software Input Hardware Input RS1 (PIN9) Voltage "1"...V>2.0 "0"...V<0.8 A2h, byte 118 Bit 3 OR A2h, byte 110 Bit 5 TX Rate Control Software Input Hardware Input